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21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "qemu/module.h"
24#include "hw/intc/arm_gicv3_its_common.h"
25#include "hw/qdev-properties.h"
26#include "sysemu/runstate.h"
27#include "sysemu/kvm.h"
28#include "kvm_arm.h"
29#include "migration/blocker.h"
30#include "qom/object.h"
31
32#define TYPE_KVM_ARM_ITS "arm-its-kvm"
33typedef struct KVMARMITSClass KVMARMITSClass;
34
35DECLARE_OBJ_CHECKERS(GICv3ITSState, KVMARMITSClass,
36 KVM_ARM_ITS, TYPE_KVM_ARM_ITS)
37
38struct KVMARMITSClass {
39 GICv3ITSCommonClass parent_class;
40 void (*parent_reset)(DeviceState *dev);
41};
42
43
44static int kvm_its_send_msi(GICv3ITSState *s, uint32_t value, uint16_t devid)
45{
46 struct kvm_msi msi;
47
48 if (unlikely(!s->translater_gpa_known)) {
49 MemoryRegion *mr = &s->iomem_its_translation;
50 MemoryRegionSection mrs;
51
52 mrs = memory_region_find(mr, 0, 1);
53 memory_region_unref(mrs.mr);
54 s->gits_translater_gpa = mrs.offset_within_address_space + 0x40;
55 s->translater_gpa_known = true;
56 }
57
58 msi.address_lo = extract64(s->gits_translater_gpa, 0, 32);
59 msi.address_hi = extract64(s->gits_translater_gpa, 32, 32);
60 msi.data = le32_to_cpu(value);
61 msi.flags = KVM_MSI_VALID_DEVID;
62 msi.devid = devid;
63 memset(msi.pad, 0, sizeof(msi.pad));
64
65 return kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi);
66}
67
68
69
70
71
72
73
74static void vm_change_state_handler(void *opaque, bool running,
75 RunState state)
76{
77 GICv3ITSState *s = (GICv3ITSState *)opaque;
78 Error *err = NULL;
79
80 if (running) {
81 return;
82 }
83
84 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
85 KVM_DEV_ARM_ITS_SAVE_TABLES, NULL, true, &err);
86 if (err) {
87 error_report_err(err);
88 }
89}
90
91static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
92{
93 GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
94
95 s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_ITS, false);
96 if (s->dev_fd < 0) {
97 error_setg_errno(errp, -s->dev_fd, "error creating in-kernel ITS");
98 return;
99 }
100
101
102 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
103 KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort);
104
105
106 kvm_arm_register_device(&s->iomem_its_cntrl, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
107 KVM_VGIC_ITS_ADDR_TYPE, s->dev_fd, 0);
108
109 gicv3_its_init_mmio(s, NULL, NULL);
110
111 if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
112 GITS_CTLR)) {
113 error_setg(&s->migration_blocker, "This operating system kernel "
114 "does not support vITS migration");
115 if (migrate_add_blocker(s->migration_blocker, errp) < 0) {
116 error_free(s->migration_blocker);
117 return;
118 }
119 } else {
120 qemu_add_vm_change_state_handler(vm_change_state_handler, s);
121 }
122
123 kvm_msi_use_devid = true;
124 kvm_gsi_direct_mapping = false;
125 kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
126}
127
128
129
130
131
132
133
134static void kvm_arm_its_pre_save(GICv3ITSState *s)
135{
136 int i;
137
138 for (i = 0; i < 8; i++) {
139 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
140 GITS_BASER + i * 8, &s->baser[i], false,
141 &error_abort);
142 }
143
144 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
145 GITS_CTLR, &s->ctlr, false, &error_abort);
146
147 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
148 GITS_CBASER, &s->cbaser, false, &error_abort);
149
150 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
151 GITS_CREADR, &s->creadr, false, &error_abort);
152
153 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
154 GITS_CWRITER, &s->cwriter, false, &error_abort);
155
156 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
157 GITS_IIDR, &s->iidr, false, &error_abort);
158}
159
160
161
162
163static void kvm_arm_its_post_load(GICv3ITSState *s)
164{
165 int i;
166
167 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
168 GITS_IIDR, &s->iidr, true, &error_abort);
169
170
171
172
173
174 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
175 GITS_CBASER, &s->cbaser, true, &error_abort);
176
177 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
178 GITS_CREADR, &s->creadr, true, &error_abort);
179
180 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
181 GITS_CWRITER, &s->cwriter, true, &error_abort);
182
183
184 for (i = 0; i < 8; i++) {
185 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
186 GITS_BASER + i * 8, &s->baser[i], true,
187 &error_abort);
188 }
189
190 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
191 KVM_DEV_ARM_ITS_RESTORE_TABLES, NULL, true,
192 &error_abort);
193
194 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
195 GITS_CTLR, &s->ctlr, true, &error_abort);
196}
197
198static void kvm_arm_its_reset(DeviceState *dev)
199{
200 GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
201 KVMARMITSClass *c = KVM_ARM_ITS_GET_CLASS(s);
202 int i;
203
204 c->parent_reset(dev);
205
206 if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
207 KVM_DEV_ARM_ITS_CTRL_RESET)) {
208 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
209 KVM_DEV_ARM_ITS_CTRL_RESET, NULL, true, &error_abort);
210 return;
211 }
212
213 warn_report("ITS KVM: full reset is not supported by the host kernel");
214
215 if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
216 GITS_CTLR)) {
217 return;
218 }
219
220 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
221 GITS_CTLR, &s->ctlr, true, &error_abort);
222
223 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
224 GITS_CBASER, &s->cbaser, true, &error_abort);
225
226 for (i = 0; i < 8; i++) {
227 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
228 GITS_BASER + i * 8, &s->baser[i], true,
229 &error_abort);
230 }
231}
232
233static Property kvm_arm_its_props[] = {
234 DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "kvm-arm-gicv3",
235 GICv3State *),
236 DEFINE_PROP_END_OF_LIST(),
237};
238
239static void kvm_arm_its_class_init(ObjectClass *klass, void *data)
240{
241 DeviceClass *dc = DEVICE_CLASS(klass);
242 GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass);
243 KVMARMITSClass *ic = KVM_ARM_ITS_CLASS(klass);
244
245 dc->realize = kvm_arm_its_realize;
246 device_class_set_props(dc, kvm_arm_its_props);
247 device_class_set_parent_reset(dc, kvm_arm_its_reset, &ic->parent_reset);
248 icc->send_msi = kvm_its_send_msi;
249 icc->pre_save = kvm_arm_its_pre_save;
250 icc->post_load = kvm_arm_its_post_load;
251}
252
253static const TypeInfo kvm_arm_its_info = {
254 .name = TYPE_KVM_ARM_ITS,
255 .parent = TYPE_ARM_GICV3_ITS_COMMON,
256 .instance_size = sizeof(GICv3ITSState),
257 .class_init = kvm_arm_its_class_init,
258 .class_size = sizeof(KVMARMITSClass),
259};
260
261static void kvm_arm_its_register_types(void)
262{
263 type_register_static(&kvm_arm_its_info);
264}
265
266type_init(kvm_arm_its_register_types)
267