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13#include "qemu/osdep.h"
14#include "qapi/error.h"
15#include "qemu/module.h"
16#include "hw/pci/msix.h"
17#include "hw/pci/pcie_port.h"
18#include "hw/qdev-properties.h"
19#include "hw/qdev-properties-system.h"
20#include "migration/vmstate.h"
21#include "qom/object.h"
22
23#define TYPE_GEN_PCIE_ROOT_PORT "pcie-root-port"
24OBJECT_DECLARE_SIMPLE_TYPE(GenPCIERootPort, GEN_PCIE_ROOT_PORT)
25
26#define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100
27#define GEN_PCIE_ROOT_PORT_ACS_OFFSET \
28 (GEN_PCIE_ROOT_PORT_AER_OFFSET + PCI_ERR_SIZEOF)
29
30#define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR 1
31#define GEN_PCIE_ROOT_DEFAULT_IO_RANGE 4096
32
33struct GenPCIERootPort {
34
35 PCIESlot parent_obj;
36
37
38 bool migrate_msix;
39
40
41 PCIResReserve res_reserve;
42};
43
44static uint8_t gen_rp_aer_vector(const PCIDevice *d)
45{
46 return 0;
47}
48
49static int gen_rp_interrupts_init(PCIDevice *d, Error **errp)
50{
51 int rc;
52
53 rc = msix_init_exclusive_bar(d, GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR, 0, errp);
54
55 if (rc < 0) {
56 assert(rc == -ENOTSUP);
57 } else {
58 msix_vector_use(d, 0);
59 }
60
61 return rc;
62}
63
64static void gen_rp_interrupts_uninit(PCIDevice *d)
65{
66 msix_uninit_exclusive_bar(d);
67}
68
69static bool gen_rp_test_migrate_msix(void *opaque, int version_id)
70{
71 GenPCIERootPort *rp = opaque;
72
73 return rp->migrate_msix;
74}
75
76static void gen_rp_realize(DeviceState *dev, Error **errp)
77{
78 PCIDevice *d = PCI_DEVICE(dev);
79 PCIESlot *s = PCIE_SLOT(d);
80 GenPCIERootPort *grp = GEN_PCIE_ROOT_PORT(d);
81 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
82 Error *local_err = NULL;
83
84 rpc->parent_realize(dev, &local_err);
85 if (local_err) {
86 error_propagate(errp, local_err);
87 return;
88 }
89
90 if (grp->res_reserve.io == -1 && s->hotplug && !s->native_hotplug) {
91 grp->res_reserve.io = GEN_PCIE_ROOT_DEFAULT_IO_RANGE;
92 }
93 int rc = pci_bridge_qemu_reserve_cap_init(d, 0,
94 grp->res_reserve, errp);
95
96 if (rc < 0) {
97 rpc->parent_class.exit(d);
98 return;
99 }
100
101 if (!grp->res_reserve.io) {
102 pci_word_test_and_clear_mask(d->wmask + PCI_COMMAND,
103 PCI_COMMAND_IO);
104 d->wmask[PCI_IO_BASE] = 0;
105 d->wmask[PCI_IO_LIMIT] = 0;
106 }
107}
108
109static const VMStateDescription vmstate_rp_dev = {
110 .name = "pcie-root-port",
111 .priority = MIG_PRI_PCI_BUS,
112 .version_id = 1,
113 .minimum_version_id = 1,
114 .post_load = pcie_cap_slot_post_load,
115 .fields = (VMStateField[]) {
116 VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
117 VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
118 PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
119 VMSTATE_MSIX_TEST(parent_obj.parent_obj.parent_obj.parent_obj,
120 GenPCIERootPort,
121 gen_rp_test_migrate_msix),
122 VMSTATE_END_OF_LIST()
123 }
124};
125
126static Property gen_rp_props[] = {
127 DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort,
128 migrate_msix, true),
129 DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort,
130 res_reserve.bus, -1),
131 DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort,
132 res_reserve.io, -1),
133 DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort,
134 res_reserve.mem_non_pref, -1),
135 DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort,
136 res_reserve.mem_pref_32, -1),
137 DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort,
138 res_reserve.mem_pref_64, -1),
139 DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot,
140 speed, PCIE_LINK_SPEED_16),
141 DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
142 width, PCIE_LINK_WIDTH_32),
143 DEFINE_PROP_END_OF_LIST()
144};
145
146static void gen_rp_dev_class_init(ObjectClass *klass, void *data)
147{
148 DeviceClass *dc = DEVICE_CLASS(klass);
149 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
150 PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
151
152 k->vendor_id = PCI_VENDOR_ID_REDHAT;
153 k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_RP;
154 dc->desc = "PCI Express Root Port";
155 dc->vmsd = &vmstate_rp_dev;
156 device_class_set_props(dc, gen_rp_props);
157
158 device_class_set_parent_realize(dc, gen_rp_realize, &rpc->parent_realize);
159
160 rpc->aer_vector = gen_rp_aer_vector;
161 rpc->interrupts_init = gen_rp_interrupts_init;
162 rpc->interrupts_uninit = gen_rp_interrupts_uninit;
163 rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET;
164 rpc->acs_offset = GEN_PCIE_ROOT_PORT_ACS_OFFSET;
165}
166
167static const TypeInfo gen_rp_dev_info = {
168 .name = TYPE_GEN_PCIE_ROOT_PORT,
169 .parent = TYPE_PCIE_ROOT_PORT,
170 .instance_size = sizeof(GenPCIERootPort),
171 .class_init = gen_rp_dev_class_init,
172};
173
174 static void gen_rp_register_types(void)
175 {
176 type_register_static(&gen_rp_dev_info);
177 }
178 type_init(gen_rp_register_types)
179
