LXR qemu/include/hw/misc/mchp_pfsoc

   1/*
   2 * Microchip PolarFire SoC DDR Memory Controller module emulation
   3 *
   4 * Copyright (c) 2020 Wind River Systems, Inc.
   5 *
   6 * Author:
   7 *   Bin Meng <bin.meng@windriver.com>
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation; either version 2 or
  12 * (at your option) version 3 of the License.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License along
  20 * with this program; if not, see <http://www.gnu.org/licenses/>.
  21 */
  22
  23#ifndef MCHP_PFSOC_DMC_H
  24#define MCHP_PFSOC_DMC_H
  25
  26/* DDR SGMII PHY module */
  27
  28#define MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE   0x1000
  29
  30typedef struct MchpPfSoCDdrSgmiiPhyState {
  31    SysBusDevice parent;
  32    MemoryRegion sgmii_phy;
  33} MchpPfSoCDdrSgmiiPhyState;
  34
  35#define TYPE_MCHP_PFSOC_DDR_SGMII_PHY "mchp.pfsoc.ddr_sgmii_phy"
  36
  37#define MCHP_PFSOC_DDR_SGMII_PHY(obj) \
  38    OBJECT_CHECK(MchpPfSoCDdrSgmiiPhyState, (obj), \
  39                 TYPE_MCHP_PFSOC_DDR_SGMII_PHY)
  40
  41/* DDR CFG module */
  42
  43#define MCHP_PFSOC_DDR_CFG_REG_SIZE         0x40000
  44
  45typedef struct MchpPfSoCDdrCfgState {
  46    SysBusDevice parent;
  47    MemoryRegion cfg;
  48} MchpPfSoCDdrCfgState;
  49
  50#define TYPE_MCHP_PFSOC_DDR_CFG "mchp.pfsoc.ddr_cfg"
  51
  52#define MCHP_PFSOC_DDR_CFG(obj) \
  53    OBJECT_CHECK(MchpPfSoCDdrCfgState, (obj), \
  54                 TYPE_MCHP_PFSOC_DDR_CFG)
  55
  56#endif /* MCHP_PFSOC_DMC_H */
  57