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20#include "qemu/osdep.h"
21#include "tcg/tcg-op.h"
22#include "tcg/tcg-op-gvec.h"
23#include "translate.h"
24#include "translate-a32.h"
25
26#include "decode-m-nocp.c.inc"
27
28
29
30
31
32
33
34
35
36
37static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
38{
39 TCGv_i32 fptr;
40
41 if (!arm_dc_feature(s, ARM_FEATURE_M) ||
42 !arm_dc_feature(s, ARM_FEATURE_V8)) {
43 return false;
44 }
45
46 if (a->op) {
47
48
49
50
51
52
53
54 if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
55 return false;
56 }
57 } else {
58
59
60
61
62
63
64 if (dc_isar_feature(aa32_simd_r32, s)) {
65 unallocated_encoding(s);
66 return true;
67 }
68 }
69
70
71
72
73
74
75 if (!s->v8m_secure) {
76 unallocated_encoding(s);
77 return true;
78 }
79
80 s->eci_handled = true;
81
82
83 if (!dc_isar_feature(aa32_vfp, s)) {
84 clear_eci_state(s);
85 return true;
86 }
87
88 fptr = load_reg(s, a->rn);
89 if (a->l) {
90 gen_helper_v7m_vlldm(cpu_env, fptr);
91 } else {
92 gen_helper_v7m_vlstm(cpu_env, fptr);
93 }
94 tcg_temp_free_i32(fptr);
95
96 clear_eci_state(s);
97
98
99
100
101
102 s->base.is_jmp = DISAS_UPDATE_EXIT;
103 return true;
104}
105
106static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a)
107{
108 int btmreg, topreg;
109 TCGv_i64 zero;
110 TCGv_i32 aspen, sfpa;
111
112 if (!dc_isar_feature(aa32_m_sec_state, s)) {
113
114 return false;
115 }
116
117
118 if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) {
119 unallocated_encoding(s);
120 return true;
121 }
122
123 s->eci_handled = true;
124
125 if (!dc_isar_feature(aa32_vfp_simd, s)) {
126
127 clear_eci_state(s);
128 return true;
129 }
130
131
132
133
134
135
136 aspen = load_cpu_field(v7m.fpccr[M_REG_S]);
137 sfpa = load_cpu_field(v7m.control[M_REG_S]);
138 tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
139 tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
140 tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK);
141 tcg_gen_or_i32(sfpa, sfpa, aspen);
142 arm_gen_condlabel(s);
143 tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel);
144
145 if (s->fp_excp_el != 0) {
146 gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
147 syn_uncategorized(), s->fp_excp_el);
148 return true;
149 }
150
151 topreg = a->vd + a->imm - 1;
152 btmreg = a->vd;
153
154
155 if (a->size == 3) {
156 topreg = topreg * 2 + 1;
157 btmreg *= 2;
158 }
159
160 if (topreg > 63 || (topreg > 31 && !(topreg & 1))) {
161
162 unallocated_encoding(s);
163 return true;
164 }
165
166
167 if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) {
168 topreg = 31;
169 }
170
171 if (!vfp_access_check(s)) {
172 return true;
173 }
174
175
176 zero = tcg_const_i64(0);
177 if (btmreg & 1) {
178 write_neon_element64(zero, btmreg >> 1, 1, MO_32);
179 btmreg++;
180 }
181 for (; btmreg + 1 <= topreg; btmreg += 2) {
182 write_neon_element64(zero, btmreg >> 1, 0, MO_64);
183 }
184 if (btmreg == topreg) {
185 write_neon_element64(zero, btmreg >> 1, 0, MO_32);
186 btmreg++;
187 }
188 assert(btmreg == topreg + 1);
189 if (dc_isar_feature(aa32_mve, s)) {
190 TCGv_i32 z32 = tcg_const_i32(0);
191 store_cpu_field(z32, v7m.vpr);
192 }
193
194 clear_eci_state(s);
195 return true;
196}
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216
217typedef void fp_sysreg_storefn(DisasContext *s, void *opaque, TCGv_i32 value,
218 bool do_access);
219
220
221
222
223
224
225typedef TCGv_i32 fp_sysreg_loadfn(DisasContext *s, void *opaque,
226 bool do_access);
227
228
229typedef enum FPSysRegCheckResult {
230 FPSysRegCheckFailed,
231 FPSysRegCheckDone,
232 FPSysRegCheckContinue,
233} FPSysRegCheckResult;
234
235static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)
236{
237 if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)) {
238 return FPSysRegCheckFailed;
239 }
240
241 switch (regno) {
242 case ARM_VFP_FPSCR:
243 case QEMU_VFP_FPSCR_NZCV:
244 break;
245 case ARM_VFP_FPSCR_NZCVQC:
246 if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
247 return FPSysRegCheckFailed;
248 }
249 break;
250 case ARM_VFP_FPCXT_S:
251 case ARM_VFP_FPCXT_NS:
252 if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
253 return FPSysRegCheckFailed;
254 }
255 if (!s->v8m_secure) {
256 return FPSysRegCheckFailed;
257 }
258 break;
259 case ARM_VFP_VPR:
260 case ARM_VFP_P0:
261 if (!dc_isar_feature(aa32_mve, s)) {
262 return FPSysRegCheckFailed;
263 }
264 break;
265 default:
266 return FPSysRegCheckFailed;
267 }
268
269
270
271
272
273
274
275 if (regno != ARM_VFP_FPCXT_NS && !vfp_access_check(s)) {
276 return FPSysRegCheckDone;
277 }
278 return FPSysRegCheckContinue;
279}
280
281static void gen_branch_fpInactive(DisasContext *s, TCGCond cond,
282 TCGLabel *label)
283{
284
285
286
287
288
289
290
291
292
293
294
295
296 assert(cond == TCG_COND_EQ || cond == TCG_COND_NE);
297
298
299 TCGv_i32 aspen, fpca;
300 aspen = load_cpu_field(v7m.fpccr[M_REG_NS]);
301 fpca = load_cpu_field(v7m.control[M_REG_S]);
302 tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
303 tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
304 tcg_gen_andi_i32(fpca, fpca, R_V7M_CONTROL_FPCA_MASK);
305 tcg_gen_or_i32(fpca, fpca, aspen);
306 tcg_gen_brcondi_i32(tcg_invert_cond(cond), fpca, 0, label);
307 tcg_temp_free_i32(aspen);
308 tcg_temp_free_i32(fpca);
309}
310
311static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
312 fp_sysreg_loadfn *loadfn,
313 void *opaque)
314{
315
316 TCGv_i32 tmp;
317 TCGLabel *lab_end = NULL;
318
319 switch (fp_sysreg_checks(s, regno)) {
320 case FPSysRegCheckFailed:
321 return false;
322 case FPSysRegCheckDone:
323 return true;
324 case FPSysRegCheckContinue:
325 break;
326 }
327
328 switch (regno) {
329 case ARM_VFP_FPSCR:
330 tmp = loadfn(s, opaque, true);
331 gen_helper_vfp_set_fpscr(cpu_env, tmp);
332 tcg_temp_free_i32(tmp);
333 gen_lookup_tb(s);
334 break;
335 case ARM_VFP_FPSCR_NZCVQC:
336 {
337 TCGv_i32 fpscr;
338 tmp = loadfn(s, opaque, true);
339 if (dc_isar_feature(aa32_mve, s)) {
340
341 TCGv_i32 qc = tcg_temp_new_i32();
342 tcg_gen_andi_i32(qc, tmp, FPCR_QC);
343
344
345
346
347 tcg_gen_gvec_dup_i32(MO_32, offsetof(CPUARMState, vfp.qc),
348 16, 16, qc);
349 }
350 tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
351 fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
352 tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK);
353 tcg_gen_or_i32(fpscr, fpscr, tmp);
354 store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]);
355 tcg_temp_free_i32(tmp);
356 break;
357 }
358 case ARM_VFP_FPCXT_NS:
359 {
360 TCGLabel *lab_active = gen_new_label();
361
362 lab_end = gen_new_label();
363 gen_branch_fpInactive(s, TCG_COND_EQ, lab_active);
364
365
366
367
368 loadfn(s, opaque, false);
369 tcg_gen_br(lab_end);
370
371 gen_set_label(lab_active);
372
373
374
375
376
377 if (!vfp_access_check_m(s, true)) {
378
379
380
381
382 s->base.is_jmp = DISAS_NEXT;
383 break;
384 }
385 }
386
387 case ARM_VFP_FPCXT_S:
388 {
389 TCGv_i32 sfpa, control;
390
391
392
393
394 tmp = loadfn(s, opaque, true);
395 sfpa = tcg_temp_new_i32();
396 tcg_gen_shri_i32(sfpa, tmp, 31);
397 control = load_cpu_field(v7m.control[M_REG_S]);
398 tcg_gen_deposit_i32(control, control, sfpa,
399 R_V7M_CONTROL_SFPA_SHIFT, 1);
400 store_cpu_field(control, v7m.control[M_REG_S]);
401 tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
402 gen_helper_vfp_set_fpscr(cpu_env, tmp);
403 s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
404 tcg_temp_free_i32(tmp);
405 tcg_temp_free_i32(sfpa);
406 break;
407 }
408 case ARM_VFP_VPR:
409
410 if (IS_USER(s)) {
411 loadfn(s, opaque, false);
412 break;
413 }
414 tmp = loadfn(s, opaque, true);
415 store_cpu_field(tmp, v7m.vpr);
416 s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
417 break;
418 case ARM_VFP_P0:
419 {
420 TCGv_i32 vpr;
421 tmp = loadfn(s, opaque, true);
422 vpr = load_cpu_field(v7m.vpr);
423 tcg_gen_deposit_i32(vpr, vpr, tmp,
424 R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH);
425 store_cpu_field(vpr, v7m.vpr);
426 s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
427 tcg_temp_free_i32(tmp);
428 break;
429 }
430 default:
431 g_assert_not_reached();
432 }
433 if (lab_end) {
434 gen_set_label(lab_end);
435 }
436 return true;
437}
438
439static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
440 fp_sysreg_storefn *storefn,
441 void *opaque)
442{
443
444 TCGv_i32 tmp;
445 TCGLabel *lab_end = NULL;
446 bool lookup_tb = false;
447
448 switch (fp_sysreg_checks(s, regno)) {
449 case FPSysRegCheckFailed:
450 return false;
451 case FPSysRegCheckDone:
452 return true;
453 case FPSysRegCheckContinue:
454 break;
455 }
456
457 if (regno == ARM_VFP_FPSCR_NZCVQC && !dc_isar_feature(aa32_mve, s)) {
458
459 regno = QEMU_VFP_FPSCR_NZCV;
460 }
461
462 switch (regno) {
463 case ARM_VFP_FPSCR:
464 tmp = tcg_temp_new_i32();
465 gen_helper_vfp_get_fpscr(tmp, cpu_env);
466 storefn(s, opaque, tmp, true);
467 break;
468 case ARM_VFP_FPSCR_NZCVQC:
469 tmp = tcg_temp_new_i32();
470 gen_helper_vfp_get_fpscr(tmp, cpu_env);
471 tcg_gen_andi_i32(tmp, tmp, FPCR_NZCVQC_MASK);
472 storefn(s, opaque, tmp, true);
473 break;
474 case QEMU_VFP_FPSCR_NZCV:
475
476
477
478
479 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
480 tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
481 storefn(s, opaque, tmp, true);
482 break;
483 case ARM_VFP_FPCXT_S:
484 {
485 TCGv_i32 control, sfpa, fpscr;
486
487 tmp = tcg_temp_new_i32();
488 sfpa = tcg_temp_new_i32();
489 gen_helper_vfp_get_fpscr(tmp, cpu_env);
490 tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
491 control = load_cpu_field(v7m.control[M_REG_S]);
492 tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
493 tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT);
494 tcg_gen_or_i32(tmp, tmp, sfpa);
495 tcg_temp_free_i32(sfpa);
496
497
498
499
500 storefn(s, opaque, tmp, true);
501
502
503
504
505 tcg_gen_andi_i32(control, control, ~R_V7M_CONTROL_SFPA_MASK);
506 store_cpu_field(control, v7m.control[M_REG_S]);
507 fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
508 gen_helper_vfp_set_fpscr(cpu_env, fpscr);
509 tcg_temp_free_i32(fpscr);
510 lookup_tb = true;
511 break;
512 }
513 case ARM_VFP_FPCXT_NS:
514 {
515 TCGv_i32 control, sfpa, fpscr, fpdscr, zero;
516 TCGLabel *lab_active = gen_new_label();
517
518 lookup_tb = true;
519
520 gen_branch_fpInactive(s, TCG_COND_EQ, lab_active);
521
522 TCGv_i32 tmp = load_cpu_field(v7m.fpdscr[M_REG_NS]);
523 storefn(s, opaque, tmp, true);
524 lab_end = gen_new_label();
525 tcg_gen_br(lab_end);
526
527 gen_set_label(lab_active);
528
529
530
531
532
533 if (!vfp_access_check_m(s, true)) {
534
535
536
537
538 s->base.is_jmp = DISAS_NEXT;
539 break;
540 }
541 tmp = tcg_temp_new_i32();
542 sfpa = tcg_temp_new_i32();
543 fpscr = tcg_temp_new_i32();
544 gen_helper_vfp_get_fpscr(fpscr, cpu_env);
545 tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK);
546 control = load_cpu_field(v7m.control[M_REG_S]);
547 tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
548 tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT);
549 tcg_gen_or_i32(tmp, tmp, sfpa);
550 tcg_temp_free_i32(control);
551
552 storefn(s, opaque, tmp, true);
553
554 fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
555 zero = tcg_const_i32(0);
556 tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, zero, fpdscr, fpscr);
557 gen_helper_vfp_set_fpscr(cpu_env, fpscr);
558 tcg_temp_free_i32(zero);
559 tcg_temp_free_i32(sfpa);
560 tcg_temp_free_i32(fpdscr);
561 tcg_temp_free_i32(fpscr);
562 break;
563 }
564 case ARM_VFP_VPR:
565
566 if (IS_USER(s)) {
567 storefn(s, opaque, NULL, false);
568 break;
569 }
570 tmp = load_cpu_field(v7m.vpr);
571 storefn(s, opaque, tmp, true);
572 break;
573 case ARM_VFP_P0:
574 tmp = load_cpu_field(v7m.vpr);
575 tcg_gen_extract_i32(tmp, tmp, R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH);
576 storefn(s, opaque, tmp, true);
577 break;
578 default:
579 g_assert_not_reached();
580 }
581
582 if (lab_end) {
583 gen_set_label(lab_end);
584 }
585 if (lookup_tb) {
586 gen_lookup_tb(s);
587 }
588 return true;
589}
590
591static void fp_sysreg_to_gpr(DisasContext *s, void *opaque, TCGv_i32 value,
592 bool do_access)
593{
594 arg_VMSR_VMRS *a = opaque;
595
596 if (!do_access) {
597 return;
598 }
599
600 if (a->rt == 15) {
601
602 gen_set_nzcv(value);
603 tcg_temp_free_i32(value);
604 } else {
605 store_reg(s, a->rt, value);
606 }
607}
608
609static TCGv_i32 gpr_to_fp_sysreg(DisasContext *s, void *opaque, bool do_access)
610{
611 arg_VMSR_VMRS *a = opaque;
612
613 if (!do_access) {
614 return NULL;
615 }
616 return load_reg(s, a->rt);
617}
618
619static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
620{
621
622
623
624
625
626
627 if (a->rt == 15) {
628 if (a->l && a->reg == ARM_VFP_FPSCR) {
629 a->reg = QEMU_VFP_FPSCR_NZCV;
630 } else {
631 return false;
632 }
633 }
634
635 if (a->l) {
636
637 return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_gpr, a);
638 } else {
639
640 return gen_M_fp_sysreg_write(s, a->reg, gpr_to_fp_sysreg, a);
641 }
642}
643
644static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value,
645 bool do_access)
646{
647 arg_vldr_sysreg *a = opaque;
648 uint32_t offset = a->imm;
649 TCGv_i32 addr;
650
651 if (!a->a) {
652 offset = -offset;
653 }
654
655 if (!do_access && !a->w) {
656 return;
657 }
658
659 addr = load_reg(s, a->rn);
660 if (a->p) {
661 tcg_gen_addi_i32(addr, addr, offset);
662 }
663
664 if (s->v8m_stackcheck && a->rn == 13 && a->w) {
665 gen_helper_v8m_stackcheck(cpu_env, addr);
666 }
667
668 if (do_access) {
669 gen_aa32_st_i32(s, value, addr, get_mem_index(s),
670 MO_UL | MO_ALIGN | s->be_data);
671 tcg_temp_free_i32(value);
672 }
673
674 if (a->w) {
675
676 if (!a->p) {
677 tcg_gen_addi_i32(addr, addr, offset);
678 }
679 store_reg(s, a->rn, addr);
680 } else {
681 tcg_temp_free_i32(addr);
682 }
683}
684
685static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, void *opaque,
686 bool do_access)
687{
688 arg_vldr_sysreg *a = opaque;
689 uint32_t offset = a->imm;
690 TCGv_i32 addr;
691 TCGv_i32 value = NULL;
692
693 if (!a->a) {
694 offset = -offset;
695 }
696
697 if (!do_access && !a->w) {
698 return NULL;
699 }
700
701 addr = load_reg(s, a->rn);
702 if (a->p) {
703 tcg_gen_addi_i32(addr, addr, offset);
704 }
705
706 if (s->v8m_stackcheck && a->rn == 13 && a->w) {
707 gen_helper_v8m_stackcheck(cpu_env, addr);
708 }
709
710 if (do_access) {
711 value = tcg_temp_new_i32();
712 gen_aa32_ld_i32(s, value, addr, get_mem_index(s),
713 MO_UL | MO_ALIGN | s->be_data);
714 }
715
716 if (a->w) {
717
718 if (!a->p) {
719 tcg_gen_addi_i32(addr, addr, offset);
720 }
721 store_reg(s, a->rn, addr);
722 } else {
723 tcg_temp_free_i32(addr);
724 }
725 return value;
726}
727
728static bool trans_VLDR_sysreg(DisasContext *s, arg_vldr_sysreg *a)
729{
730 if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
731 return false;
732 }
733 if (a->rn == 15) {
734 return false;
735 }
736 return gen_M_fp_sysreg_write(s, a->reg, memory_to_fp_sysreg, a);
737}
738
739static bool trans_VSTR_sysreg(DisasContext *s, arg_vldr_sysreg *a)
740{
741 if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
742 return false;
743 }
744 if (a->rn == 15) {
745 return false;
746 }
747 return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_memory, a);
748}
749
750static bool trans_NOCP(DisasContext *s, arg_nocp *a)
751{
752
753
754
755
756
757
758 assert(arm_dc_feature(s, ARM_FEATURE_M));
759
760 if (a->cp == 11) {
761 a->cp = 10;
762 }
763 if (arm_dc_feature(s, ARM_FEATURE_V8_1M) &&
764 (a->cp == 8 || a->cp == 9 || a->cp == 14 || a->cp == 15)) {
765
766 a->cp = 10;
767 }
768
769 if (a->cp != 10) {
770 gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
771 syn_uncategorized(), default_exception_el(s));
772 return true;
773 }
774
775 if (s->fp_excp_el != 0) {
776 gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
777 syn_uncategorized(), s->fp_excp_el);
778 return true;
779 }
780
781 return false;
782}
783
784static bool trans_NOCP_8_1(DisasContext *s, arg_nocp *a)
785{
786
787 if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
788 return false;
789 }
790 return trans_NOCP(s, a);
791}
792