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12#include "qemu/osdep.h"
13#include "qapi/error.h"
14#include "hw/qdev-core.h"
15#include "exec/memory.h"
16#include "qom/object.h"
17#include "hw/pci/pci.h"
18#include "qom/object_interfaces.h"
19#include "qemu/error-report.h"
20#include "migration/vmstate.h"
21#include "hw/qdev-properties.h"
22#include "hw/acpi/acpi.h"
23#include "hw/acpi/acpi-defs.h"
24#include "hw/acpi/aml-build.h"
25#include "hw/acpi/bios-linker-loader.h"
26#include "exec/address-spaces.h"
27#include "sysemu/hostmem.h"
28#include "hw/acpi/erst.h"
29#include "trace.h"
30
31
32#define ACTION_BEGIN_WRITE_OPERATION 0x0
33#define ACTION_BEGIN_READ_OPERATION 0x1
34#define ACTION_BEGIN_CLEAR_OPERATION 0x2
35#define ACTION_END_OPERATION 0x3
36#define ACTION_SET_RECORD_OFFSET 0x4
37#define ACTION_EXECUTE_OPERATION 0x5
38#define ACTION_CHECK_BUSY_STATUS 0x6
39#define ACTION_GET_COMMAND_STATUS 0x7
40#define ACTION_GET_RECORD_IDENTIFIER 0x8
41#define ACTION_SET_RECORD_IDENTIFIER 0x9
42#define ACTION_GET_RECORD_COUNT 0xA
43#define ACTION_BEGIN_DUMMY_WRITE_OPERATION 0xB
44#define ACTION_RESERVED 0xC
45#define ACTION_GET_ERROR_LOG_ADDRESS_RANGE 0xD
46#define ACTION_GET_ERROR_LOG_ADDRESS_LENGTH 0xE
47#define ACTION_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0xF
48#define ACTION_GET_EXECUTE_OPERATION_TIMINGS 0x10
49
50
51#define STATUS_SUCCESS 0x00
52#define STATUS_NOT_ENOUGH_SPACE 0x01
53#define STATUS_HARDWARE_NOT_AVAILABLE 0x02
54#define STATUS_FAILED 0x03
55#define STATUS_RECORD_STORE_EMPTY 0x04
56#define STATUS_RECORD_NOT_FOUND 0x05
57
58
59#define INST_READ_REGISTER 0x00
60#define INST_READ_REGISTER_VALUE 0x01
61#define INST_WRITE_REGISTER 0x02
62#define INST_WRITE_REGISTER_VALUE 0x03
63#define INST_NOOP 0x04
64#define INST_LOAD_VAR1 0x05
65#define INST_LOAD_VAR2 0x06
66#define INST_STORE_VAR1 0x07
67#define INST_ADD 0x08
68#define INST_SUBTRACT 0x09
69#define INST_ADD_VALUE 0x0A
70#define INST_SUBTRACT_VALUE 0x0B
71#define INST_STALL 0x0C
72#define INST_STALL_WHILE_TRUE 0x0D
73#define INST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
74#define INST_GOTO 0x0F
75#define INST_SET_SRC_ADDRESS_BASE 0x10
76#define INST_SET_DST_ADDRESS_BASE 0x11
77#define INST_MOVE_DATA 0x12
78
79
80#define UEFI_CPER_RECORD_MIN_SIZE 128U
81#define UEFI_CPER_RECORD_LENGTH_OFFSET 20U
82#define UEFI_CPER_RECORD_ID_OFFSET 96U
83
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89
90
91
92
93#define ERST_REG_SIZE (16UL)
94#define ERST_ACTION_OFFSET (0UL)
95#define ERST_VALUE_OFFSET (8UL)
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110
111
112#define ERST_RECORD_SIZE (8192UL)
113
114#define ACPI_ERST_MEMDEV_PROP "memdev"
115#define ACPI_ERST_RECORD_SIZE_PROP "record_size"
116
117
118
119
120
121
122#define ERST_UNSPECIFIED_RECORD_ID (0UL)
123#define ERST_EMPTY_END_RECORD_ID (~0UL)
124
125#define ERST_IS_VALID_RECORD_ID(rid) \
126 ((rid != ERST_UNSPECIFIED_RECORD_ID) && \
127 (rid != ERST_EMPTY_END_RECORD_ID))
128
129
130
131
132
133
134#define ERST_EXECUTE_OPERATION_MAGIC 0x9CUL
135#define ERST_STORE_MAGIC 0x524F545354535245UL
136typedef struct {
137 uint64_t magic;
138 uint32_t record_size;
139 uint32_t storage_offset;
140 uint16_t version;
141 uint16_t reserved;
142 uint32_t record_count;
143 uint64_t map[];
144} __attribute__((packed)) ERSTStorageHeader;
145
146
147
148
149#define ACPIERST(obj) \
150 OBJECT_CHECK(ERSTDeviceState, (obj), TYPE_ACPI_ERST)
151
152
153
154
155typedef struct {
156 PCIDevice parent_obj;
157
158
159 HostMemoryBackend *hostmem;
160 MemoryRegion *hostmem_mr;
161 uint32_t storage_size;
162 uint32_t default_record_size;
163
164
165 MemoryRegion iomem_mr;
166
167
168 MemoryRegion exchange_mr;
169
170
171 uint8_t operation;
172 uint8_t busy_status;
173 uint8_t command_status;
174 uint32_t record_offset;
175 uint64_t reg_action;
176 uint64_t reg_value;
177 uint64_t record_identifier;
178 ERSTStorageHeader *header;
179 unsigned first_record_index;
180 unsigned last_record_index;
181 unsigned next_record_index;
182
183} ERSTDeviceState;
184
185
186
187typedef struct {
188 GArray *table_data;
189 pcibus_t bar;
190 uint8_t instruction;
191 uint8_t flags;
192 uint8_t register_bit_width;
193 pcibus_t register_offset;
194} BuildSerializationInstructionEntry;
195
196
197static void build_serialization_instruction(
198 BuildSerializationInstructionEntry *e,
199 uint8_t serialization_action,
200 uint64_t value)
201{
202
203 struct AcpiGenericAddress gas;
204 uint64_t mask;
205
206
207 build_append_int_noprefix(e->table_data, serialization_action, 1);
208
209 build_append_int_noprefix(e->table_data, e->instruction, 1);
210
211 build_append_int_noprefix(e->table_data, e->flags, 1);
212
213 build_append_int_noprefix(e->table_data, 0, 1);
214
215 gas.space_id = AML_SYSTEM_MEMORY;
216 gas.bit_width = e->register_bit_width;
217 gas.bit_offset = 0;
218 gas.access_width = (uint8_t)ctz32(e->register_bit_width) - 2;
219 gas.address = (uint64_t)(e->bar + e->register_offset);
220 build_append_gas_from_struct(e->table_data, &gas);
221
222 build_append_int_noprefix(e->table_data, value, 8);
223
224 mask = (1ULL << (e->register_bit_width - 1) << 1) - 1;
225 build_append_int_noprefix(e->table_data, mask, 8);
226}
227
228
229void build_erst(GArray *table_data, BIOSLinker *linker, Object *erst_dev,
230 const char *oem_id, const char *oem_table_id)
231{
232
233
234
235
236
237
238 unsigned action;
239 GArray *table_instruction_data = g_array_new(FALSE, FALSE, sizeof(char));
240 pcibus_t bar0 = pci_get_bar_addr(PCI_DEVICE(erst_dev), 0);
241 AcpiTable table = { .sig = "ERST", .rev = 1, .oem_id = oem_id,
242 .oem_table_id = oem_table_id };
243
244 BuildSerializationInstructionEntry rd_value_32_val = {
245 .table_data = table_instruction_data, .bar = bar0, .flags = 0,
246 .instruction = INST_READ_REGISTER_VALUE,
247 .register_bit_width = 32,
248 .register_offset = ERST_VALUE_OFFSET,
249 };
250 BuildSerializationInstructionEntry rd_value_32 = {
251 .table_data = table_instruction_data, .bar = bar0, .flags = 0,
252 .instruction = INST_READ_REGISTER,
253 .register_bit_width = 32,
254 .register_offset = ERST_VALUE_OFFSET,
255 };
256 BuildSerializationInstructionEntry rd_value_64 = {
257 .table_data = table_instruction_data, .bar = bar0, .flags = 0,
258 .instruction = INST_READ_REGISTER,
259 .register_bit_width = 64,
260 .register_offset = ERST_VALUE_OFFSET,
261 };
262 BuildSerializationInstructionEntry wr_value_32_val = {
263 .table_data = table_instruction_data, .bar = bar0, .flags = 0,
264 .instruction = INST_WRITE_REGISTER_VALUE,
265 .register_bit_width = 32,
266 .register_offset = ERST_VALUE_OFFSET,
267 };
268 BuildSerializationInstructionEntry wr_value_32 = {
269 .table_data = table_instruction_data, .bar = bar0, .flags = 0,
270 .instruction = INST_WRITE_REGISTER,
271 .register_bit_width = 32,
272 .register_offset = ERST_VALUE_OFFSET,
273 };
274 BuildSerializationInstructionEntry wr_value_64 = {
275 .table_data = table_instruction_data, .bar = bar0, .flags = 0,
276 .instruction = INST_WRITE_REGISTER,
277 .register_bit_width = 64,
278 .register_offset = ERST_VALUE_OFFSET,
279 };
280 BuildSerializationInstructionEntry wr_action = {
281 .table_data = table_instruction_data, .bar = bar0, .flags = 0,
282 .instruction = INST_WRITE_REGISTER_VALUE,
283 .register_bit_width = 32,
284 .register_offset = ERST_ACTION_OFFSET,
285 };
286
287 trace_acpi_erst_pci_bar_0(bar0);
288
289
290 action = ACTION_BEGIN_WRITE_OPERATION;
291 build_serialization_instruction(&wr_action, action, action);
292
293 action = ACTION_BEGIN_READ_OPERATION;
294 build_serialization_instruction(&wr_action, action, action);
295
296 action = ACTION_BEGIN_CLEAR_OPERATION;
297 build_serialization_instruction(&wr_action, action, action);
298
299 action = ACTION_END_OPERATION;
300 build_serialization_instruction(&wr_action, action, action);
301
302 action = ACTION_SET_RECORD_OFFSET;
303 build_serialization_instruction(&wr_value_32, action, 0);
304 build_serialization_instruction(&wr_action, action, action);
305
306 action = ACTION_EXECUTE_OPERATION;
307 build_serialization_instruction(&wr_value_32_val, action,
308 ERST_EXECUTE_OPERATION_MAGIC);
309 build_serialization_instruction(&wr_action, action, action);
310
311 action = ACTION_CHECK_BUSY_STATUS;
312 build_serialization_instruction(&wr_action, action, action);
313 build_serialization_instruction(&rd_value_32_val, action, 0x01);
314
315 action = ACTION_GET_COMMAND_STATUS;
316 build_serialization_instruction(&wr_action, action, action);
317 build_serialization_instruction(&rd_value_32, action, 0);
318
319 action = ACTION_GET_RECORD_IDENTIFIER;
320 build_serialization_instruction(&wr_action, action, action);
321 build_serialization_instruction(&rd_value_64, action, 0);
322
323 action = ACTION_SET_RECORD_IDENTIFIER;
324 build_serialization_instruction(&wr_value_64, action, 0);
325 build_serialization_instruction(&wr_action, action, action);
326
327 action = ACTION_GET_RECORD_COUNT;
328 build_serialization_instruction(&wr_action, action, action);
329 build_serialization_instruction(&rd_value_32, action, 0);
330
331 action = ACTION_BEGIN_DUMMY_WRITE_OPERATION;
332 build_serialization_instruction(&wr_action, action, action);
333
334 action = ACTION_GET_ERROR_LOG_ADDRESS_RANGE;
335 build_serialization_instruction(&wr_action, action, action);
336 build_serialization_instruction(&rd_value_64, action, 0);
337
338 action = ACTION_GET_ERROR_LOG_ADDRESS_LENGTH;
339 build_serialization_instruction(&wr_action, action, action);
340 build_serialization_instruction(&rd_value_64, action, 0);
341
342 action = ACTION_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES;
343 build_serialization_instruction(&wr_action, action, action);
344 build_serialization_instruction(&rd_value_32, action, 0);
345
346 action = ACTION_GET_EXECUTE_OPERATION_TIMINGS;
347 build_serialization_instruction(&wr_action, action, action);
348 build_serialization_instruction(&rd_value_64, action, 0);
349
350
351 acpi_table_begin(&table, table_data);
352
353
354 build_append_int_noprefix(table_data, 48, 4);
355
356
357 build_append_int_noprefix(table_data, 0, 4);
358
359
360
361
362
363 g_assert((table_instruction_data->len) % 32 == 0);
364 build_append_int_noprefix(table_data,
365 (table_instruction_data->len / 32), 4);
366
367
368 g_array_append_vals(table_data, table_instruction_data->data,
369 table_instruction_data->len);
370 g_array_free(table_instruction_data, TRUE);
371
372 acpi_table_end(linker, &table);
373}
374
375
376
377static uint8_t *get_nvram_ptr_by_index(ERSTDeviceState *s, unsigned index)
378{
379 uint8_t *rc = NULL;
380 off_t offset = (index * le32_to_cpu(s->header->record_size));
381
382 g_assert(offset < s->storage_size);
383
384 rc = memory_region_get_ram_ptr(s->hostmem_mr);
385 rc += offset;
386
387 return rc;
388}
389
390static void make_erst_storage_header(ERSTDeviceState *s)
391{
392 ERSTStorageHeader *header = s->header;
393 unsigned mapsz, headersz;
394
395 header->magic = cpu_to_le64(ERST_STORE_MAGIC);
396 header->record_size = cpu_to_le32(s->default_record_size);
397 header->version = cpu_to_le16(0x0100);
398 header->reserved = cpu_to_le16(0x0000);
399
400
401 mapsz = s->storage_size / s->default_record_size;
402 mapsz *= sizeof(uint64_t);
403
404 headersz = sizeof(ERSTStorageHeader) + mapsz;
405
406 headersz = QEMU_ALIGN_UP(headersz, s->default_record_size);
407 header->storage_offset = cpu_to_le32(headersz);
408
409
410
411
412
413
414}
415
416static void check_erst_backend_storage(ERSTDeviceState *s, Error **errp)
417{
418 ERSTStorageHeader *header;
419 uint32_t record_size;
420
421 header = memory_region_get_ram_ptr(s->hostmem_mr);
422 s->header = header;
423
424
425 g_assert(QEMU_PTR_IS_ALIGNED(header, sizeof(uint64_t)));
426
427
428
429
430 if (le64_to_cpu(header->magic) == 0UL) {
431 make_erst_storage_header(s);
432 }
433
434
435 record_size = le32_to_cpu(header->record_size);
436 if (!(
437 (record_size) &&
438 (record_size >= UEFI_CPER_RECORD_MIN_SIZE) &&
439 (((record_size - 1) & record_size) == 0) &&
440 (record_size >= 4096)
441 )) {
442 error_setg(errp, "ERST record_size %u is invalid", record_size);
443 }
444
445
446 if (!(
447 (le64_to_cpu(header->magic) == ERST_STORE_MAGIC) &&
448 ((le32_to_cpu(header->storage_offset) % record_size) == 0) &&
449 (le16_to_cpu(header->version) == 0x0100) &&
450 (le16_to_cpu(header->reserved) == 0)
451 )) {
452 error_setg(errp, "ERST backend storage header is invalid");
453 }
454
455
456 if (((s->storage_size % record_size) != 0) ||
457 (record_size > s->storage_size)) {
458 error_setg(errp, "ACPI ERST requires storage size be multiple of "
459 "record size (%uKiB)", record_size);
460 }
461
462
463 s->first_record_index = le32_to_cpu(header->storage_offset)
464 / record_size;
465 s->last_record_index = (s->storage_size / record_size);
466}
467
468static void update_map_entry(ERSTDeviceState *s, unsigned index,
469 uint64_t record_id)
470{
471 if (index < s->last_record_index) {
472 s->header->map[index] = cpu_to_le64(record_id);
473 }
474}
475
476static unsigned find_next_empty_record_index(ERSTDeviceState *s)
477{
478 unsigned rc = 0;
479 unsigned index = s->first_record_index;
480
481 for (; index < s->last_record_index; ++index) {
482 if (le64_to_cpu(s->header->map[index]) == ERST_UNSPECIFIED_RECORD_ID) {
483 rc = index;
484 break;
485 }
486 }
487
488 return rc;
489}
490
491static unsigned lookup_erst_record(ERSTDeviceState *s,
492 uint64_t record_identifier)
493{
494 unsigned rc = 0;
495
496
497 if (record_identifier != ERST_UNSPECIFIED_RECORD_ID) {
498
499
500
501
502 uint32_t record_count = le32_to_cpu(s->header->record_count);
503 unsigned count = 0;
504 unsigned index;
505 for (index = s->first_record_index; index < s->last_record_index &&
506 count < record_count; ++index) {
507 if (le64_to_cpu(s->header->map[index]) == record_identifier) {
508 rc = index;
509 break;
510 }
511 if (le64_to_cpu(s->header->map[index]) !=
512 ERST_UNSPECIFIED_RECORD_ID) {
513 ++count;
514 }
515 }
516 }
517
518 return rc;
519}
520
521
522
523
524
525static unsigned get_next_record_identifier(ERSTDeviceState *s,
526 uint64_t *record_identifier, bool first)
527{
528 unsigned found = 0;
529 unsigned index;
530
531
532 if (first) {
533
534 s->next_record_index = s->first_record_index;
535 }
536 index = s->next_record_index;
537
538 *record_identifier = ERST_EMPTY_END_RECORD_ID;
539
540 if (le32_to_cpu(s->header->record_count)) {
541 for (; index < s->last_record_index; ++index) {
542 if (le64_to_cpu(s->header->map[index]) !=
543 ERST_UNSPECIFIED_RECORD_ID) {
544
545 s->next_record_index = index + 1;
546 *record_identifier = le64_to_cpu(s->header->map[index]);
547 found = 1;
548 break;
549 }
550 }
551 }
552 if (!found) {
553
554 s->next_record_index = s->first_record_index;
555 }
556
557 return STATUS_SUCCESS;
558}
559
560
561static unsigned clear_erst_record(ERSTDeviceState *s)
562{
563 unsigned rc = STATUS_RECORD_NOT_FOUND;
564 unsigned index;
565
566
567 if (!ERST_IS_VALID_RECORD_ID(s->record_identifier)) {
568 return STATUS_FAILED;
569 }
570
571 index = lookup_erst_record(s, s->record_identifier);
572 if (index) {
573
574 uint32_t record_count;
575 update_map_entry(s, index, ERST_UNSPECIFIED_RECORD_ID);
576 record_count = le32_to_cpu(s->header->record_count);
577 record_count -= 1;
578 s->header->record_count = cpu_to_le32(record_count);
579 rc = STATUS_SUCCESS;
580 }
581
582 return rc;
583}
584
585
586static unsigned read_erst_record(ERSTDeviceState *s)
587{
588 unsigned rc = STATUS_RECORD_NOT_FOUND;
589 unsigned exchange_length;
590 unsigned index;
591
592
593 if (le32_to_cpu(s->header->record_count) == 0) {
594 return STATUS_RECORD_STORE_EMPTY;
595 }
596
597 exchange_length = memory_region_size(&s->exchange_mr);
598
599
600 if (s->record_identifier == ERST_UNSPECIFIED_RECORD_ID) {
601
602 get_next_record_identifier(s, &s->record_identifier, true);
603
604 }
605
606
607 if (s->record_identifier == ERST_EMPTY_END_RECORD_ID) {
608 return STATUS_FAILED;
609 }
610
611
612 if (s->record_offset > (exchange_length - UEFI_CPER_RECORD_MIN_SIZE)) {
613 return STATUS_FAILED;
614 }
615
616 index = lookup_erst_record(s, s->record_identifier);
617 if (index) {
618 uint8_t *nvram;
619 uint8_t *exchange;
620 uint32_t record_length;
621
622
623 exchange = memory_region_get_ram_ptr(&s->exchange_mr);
624 exchange += s->record_offset;
625
626 nvram = get_nvram_ptr_by_index(s, index);
627
628 memcpy((uint8_t *)&record_length,
629 &nvram[UEFI_CPER_RECORD_LENGTH_OFFSET],
630 sizeof(uint32_t));
631 record_length = le32_to_cpu(record_length);
632 if (record_length < UEFI_CPER_RECORD_MIN_SIZE) {
633 rc = STATUS_FAILED;
634 }
635 if ((s->record_offset + record_length) > exchange_length) {
636 rc = STATUS_FAILED;
637 }
638
639 if (rc != STATUS_FAILED) {
640 memcpy(exchange, nvram, record_length);
641 rc = STATUS_SUCCESS;
642 }
643 } else {
644
645
646
647
648 get_next_record_identifier(s, &s->record_identifier, true);
649 }
650
651 return rc;
652}
653
654
655static unsigned write_erst_record(ERSTDeviceState *s)
656{
657 unsigned rc = STATUS_FAILED;
658 unsigned exchange_length;
659 unsigned index;
660 uint64_t record_identifier;
661 uint32_t record_length;
662 uint8_t *exchange;
663 uint8_t *nvram = NULL;
664 bool record_found = false;
665
666 exchange_length = memory_region_size(&s->exchange_mr);
667
668
669 if (s->record_offset > (exchange_length - UEFI_CPER_RECORD_MIN_SIZE)) {
670 return STATUS_FAILED;
671 }
672
673
674 exchange = memory_region_get_ram_ptr(&s->exchange_mr);
675 exchange += s->record_offset;
676
677
678 memcpy((uint8_t *)&record_length, &exchange[UEFI_CPER_RECORD_LENGTH_OFFSET],
679 sizeof(uint32_t));
680 record_length = le32_to_cpu(record_length);
681 if (record_length < UEFI_CPER_RECORD_MIN_SIZE) {
682 return STATUS_FAILED;
683 }
684 if ((s->record_offset + record_length) > exchange_length) {
685 return STATUS_FAILED;
686 }
687
688
689 memcpy((uint8_t *)&record_identifier, &exchange[UEFI_CPER_RECORD_ID_OFFSET],
690 sizeof(uint64_t));
691 record_identifier = le64_to_cpu(record_identifier);
692
693
694 if (!ERST_IS_VALID_RECORD_ID(record_identifier)) {
695 return STATUS_FAILED;
696 }
697
698 index = lookup_erst_record(s, record_identifier);
699 if (index) {
700
701 nvram = get_nvram_ptr_by_index(s, index);
702 record_found = true;
703 } else {
704
705 index = find_next_empty_record_index(s);
706 if (index) {
707 nvram = get_nvram_ptr_by_index(s, index);
708 } else {
709
710 rc = STATUS_NOT_ENOUGH_SPACE;
711 }
712 }
713 if (nvram) {
714
715 memcpy(nvram, exchange, record_length);
716 memset(nvram + record_length, exchange_length - record_length, 0xFF);
717
718 if (!record_found) {
719 uint32_t record_count;
720 record_count = le32_to_cpu(s->header->record_count);
721 record_count += 1;
722 s->header->record_count = cpu_to_le32(record_count);
723 }
724 update_map_entry(s, index, record_identifier);
725 rc = STATUS_SUCCESS;
726 }
727
728 return rc;
729}
730
731
732
733static uint64_t erst_rd_reg64(hwaddr addr,
734 uint64_t reg, unsigned size)
735{
736 uint64_t rdval;
737 uint64_t mask;
738 unsigned shift;
739
740 if (size == sizeof(uint64_t)) {
741
742 mask = 0xFFFFFFFFFFFFFFFFUL;
743 shift = 0;
744 } else {
745
746 mask = 0x00000000FFFFFFFFUL;
747 shift = ((addr & 0x4) == 0x4) ? 32 : 0;
748 }
749
750 rdval = reg;
751 rdval >>= shift;
752 rdval &= mask;
753
754 return rdval;
755}
756
757static uint64_t erst_wr_reg64(hwaddr addr,
758 uint64_t reg, uint64_t val, unsigned size)
759{
760 uint64_t wrval;
761 uint64_t mask;
762 unsigned shift;
763
764 if (size == sizeof(uint64_t)) {
765
766 mask = 0xFFFFFFFFFFFFFFFFUL;
767 shift = 0;
768 } else {
769
770 mask = 0x00000000FFFFFFFFUL;
771 shift = ((addr & 0x4) == 0x4) ? 32 : 0;
772 }
773
774 val &= mask;
775 val <<= shift;
776 mask <<= shift;
777 wrval = reg;
778 wrval &= ~mask;
779 wrval |= val;
780
781 return wrval;
782}
783
784static void erst_reg_write(void *opaque, hwaddr addr,
785 uint64_t val, unsigned size)
786{
787 ERSTDeviceState *s = (ERSTDeviceState *)opaque;
788
789
790
791
792
793
794 trace_acpi_erst_reg_write(addr, val, size);
795
796 switch (addr) {
797 case ERST_VALUE_OFFSET + 0:
798 case ERST_VALUE_OFFSET + 4:
799 s->reg_value = erst_wr_reg64(addr, s->reg_value, val, size);
800 break;
801 case ERST_ACTION_OFFSET + 0:
802
803
804
805
806
807
808 switch (val) {
809 case ACTION_BEGIN_WRITE_OPERATION:
810 case ACTION_BEGIN_READ_OPERATION:
811 case ACTION_BEGIN_CLEAR_OPERATION:
812 case ACTION_BEGIN_DUMMY_WRITE_OPERATION:
813 case ACTION_END_OPERATION:
814 s->operation = val;
815 break;
816 case ACTION_SET_RECORD_OFFSET:
817 s->record_offset = s->reg_value;
818 break;
819 case ACTION_EXECUTE_OPERATION:
820 if ((uint8_t)s->reg_value == ERST_EXECUTE_OPERATION_MAGIC) {
821 s->busy_status = 1;
822 switch (s->operation) {
823 case ACTION_BEGIN_WRITE_OPERATION:
824 s->command_status = write_erst_record(s);
825 break;
826 case ACTION_BEGIN_READ_OPERATION:
827 s->command_status = read_erst_record(s);
828 break;
829 case ACTION_BEGIN_CLEAR_OPERATION:
830 s->command_status = clear_erst_record(s);
831 break;
832 case ACTION_BEGIN_DUMMY_WRITE_OPERATION:
833 s->command_status = STATUS_SUCCESS;
834 break;
835 case ACTION_END_OPERATION:
836 s->command_status = STATUS_SUCCESS;
837 break;
838 default:
839 s->command_status = STATUS_FAILED;
840 break;
841 }
842 s->busy_status = 0;
843 }
844 break;
845 case ACTION_CHECK_BUSY_STATUS:
846 s->reg_value = s->busy_status;
847 break;
848 case ACTION_GET_COMMAND_STATUS:
849 s->reg_value = s->command_status;
850 break;
851 case ACTION_GET_RECORD_IDENTIFIER:
852 s->command_status = get_next_record_identifier(s,
853 &s->reg_value, false);
854 break;
855 case ACTION_SET_RECORD_IDENTIFIER:
856 s->record_identifier = s->reg_value;
857 break;
858 case ACTION_GET_RECORD_COUNT:
859 s->reg_value = le32_to_cpu(s->header->record_count);
860 break;
861 case ACTION_GET_ERROR_LOG_ADDRESS_RANGE:
862 s->reg_value = (hwaddr)pci_get_bar_addr(PCI_DEVICE(s), 1);
863 break;
864 case ACTION_GET_ERROR_LOG_ADDRESS_LENGTH:
865 s->reg_value = le32_to_cpu(s->header->record_size);
866 break;
867 case ACTION_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES:
868 s->reg_value = 0x0;
869 break;
870 case ACTION_GET_EXECUTE_OPERATION_TIMINGS:
871 s->reg_value =
872 (100ULL << 32) |
873 (10ULL << 0) ;
874 break;
875 default:
876
877 break;
878 }
879 break;
880 default:
881
882 break;
883 }
884}
885
886static uint64_t erst_reg_read(void *opaque, hwaddr addr,
887 unsigned size)
888{
889 ERSTDeviceState *s = (ERSTDeviceState *)opaque;
890 uint64_t val = 0;
891
892 switch (addr) {
893 case ERST_ACTION_OFFSET + 0:
894 case ERST_ACTION_OFFSET + 4:
895 val = erst_rd_reg64(addr, s->reg_action, size);
896 break;
897 case ERST_VALUE_OFFSET + 0:
898 case ERST_VALUE_OFFSET + 4:
899 val = erst_rd_reg64(addr, s->reg_value, size);
900 break;
901 default:
902 break;
903 }
904 trace_acpi_erst_reg_read(addr, val, size);
905 return val;
906}
907
908static const MemoryRegionOps erst_reg_ops = {
909 .read = erst_reg_read,
910 .write = erst_reg_write,
911 .endianness = DEVICE_NATIVE_ENDIAN,
912};
913
914
915
916static int erst_post_load(void *opaque, int version_id)
917{
918 ERSTDeviceState *s = opaque;
919
920
921 s->header = (ERSTStorageHeader *)get_nvram_ptr_by_index(s, 0);
922 trace_acpi_erst_post_load(s->header, le32_to_cpu(s->header->record_size));
923
924 return 0;
925}
926
927static const VMStateDescription erst_vmstate = {
928 .name = "acpi-erst",
929 .version_id = 1,
930 .minimum_version_id = 1,
931 .post_load = erst_post_load,
932 .fields = (VMStateField[]) {
933 VMSTATE_UINT8(operation, ERSTDeviceState),
934 VMSTATE_UINT8(busy_status, ERSTDeviceState),
935 VMSTATE_UINT8(command_status, ERSTDeviceState),
936 VMSTATE_UINT32(record_offset, ERSTDeviceState),
937 VMSTATE_UINT64(reg_action, ERSTDeviceState),
938 VMSTATE_UINT64(reg_value, ERSTDeviceState),
939 VMSTATE_UINT64(record_identifier, ERSTDeviceState),
940 VMSTATE_UINT32(next_record_index, ERSTDeviceState),
941 VMSTATE_END_OF_LIST()
942 }
943};
944
945static void erst_realizefn(PCIDevice *pci_dev, Error **errp)
946{
947 ERSTDeviceState *s = ACPIERST(pci_dev);
948
949 trace_acpi_erst_realizefn_in();
950
951 if (!s->hostmem) {
952 error_setg(errp, "'" ACPI_ERST_MEMDEV_PROP "' property is not set");
953 return;
954 } else if (host_memory_backend_is_mapped(s->hostmem)) {
955 error_setg(errp, "can't use already busy memdev: %s",
956 object_get_canonical_path_component(OBJECT(s->hostmem)));
957 return;
958 }
959
960 s->hostmem_mr = host_memory_backend_get_memory(s->hostmem);
961
962
963 s->storage_size = object_property_get_int(OBJECT(s->hostmem), "size", errp);
964
965
966 check_erst_backend_storage(s, errp);
967
968
969 memory_region_init_io(&s->iomem_mr, OBJECT(pci_dev), &erst_reg_ops, s,
970 TYPE_ACPI_ERST, ERST_REG_SIZE);
971 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->iomem_mr);
972
973
974 memory_region_init_ram(&s->exchange_mr, OBJECT(pci_dev),
975 "erst.exchange",
976 le32_to_cpu(s->header->record_size), errp);
977 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY,
978 &s->exchange_mr);
979
980
981 vmstate_register_ram_global(s->hostmem_mr);
982
983 trace_acpi_erst_realizefn_out(s->storage_size);
984}
985
986static void erst_reset(DeviceState *dev)
987{
988 ERSTDeviceState *s = ACPIERST(dev);
989
990 trace_acpi_erst_reset_in(le32_to_cpu(s->header->record_count));
991 s->operation = 0;
992 s->busy_status = 0;
993 s->command_status = STATUS_SUCCESS;
994 s->record_identifier = ERST_UNSPECIFIED_RECORD_ID;
995 s->record_offset = 0;
996 s->next_record_index = s->first_record_index;
997
998 trace_acpi_erst_reset_out(le32_to_cpu(s->header->record_count));
999}
1000
1001static Property erst_properties[] = {
1002 DEFINE_PROP_LINK(ACPI_ERST_MEMDEV_PROP, ERSTDeviceState, hostmem,
1003 TYPE_MEMORY_BACKEND, HostMemoryBackend *),
1004 DEFINE_PROP_UINT32(ACPI_ERST_RECORD_SIZE_PROP, ERSTDeviceState,
1005 default_record_size, ERST_RECORD_SIZE),
1006 DEFINE_PROP_END_OF_LIST(),
1007};
1008
1009static void erst_class_init(ObjectClass *klass, void *data)
1010{
1011 DeviceClass *dc = DEVICE_CLASS(klass);
1012 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1013
1014 trace_acpi_erst_class_init_in();
1015 k->realize = erst_realizefn;
1016 k->vendor_id = PCI_VENDOR_ID_REDHAT;
1017 k->device_id = PCI_DEVICE_ID_REDHAT_ACPI_ERST;
1018 k->revision = 0x00;
1019 k->class_id = PCI_CLASS_OTHERS;
1020 dc->reset = erst_reset;
1021 dc->vmsd = &erst_vmstate;
1022 dc->user_creatable = true;
1023 dc->hotpluggable = false;
1024 device_class_set_props(dc, erst_properties);
1025 dc->desc = "ACPI Error Record Serialization Table (ERST) device";
1026 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
1027 trace_acpi_erst_class_init_out();
1028}
1029
1030static const TypeInfo erst_type_info = {
1031 .name = TYPE_ACPI_ERST,
1032 .parent = TYPE_PCI_DEVICE,
1033 .class_init = erst_class_init,
1034 .instance_size = sizeof(ERSTDeviceState),
1035 .interfaces = (InterfaceInfo[]) {
1036 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1037 { }
1038 }
1039};
1040
1041static void erst_register_types(void)
1042{
1043 type_register_static(&erst_type_info);
1044}
1045
1046type_init(erst_register_types)
1047