1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21#ifndef HW_ARM_SMMUV3_INTERNAL_H
22#define HW_ARM_SMMUV3_INTERNAL_H
23
24#include "hw/arm/smmu-common.h"
25
26typedef enum SMMUTranslationStatus {
27 SMMU_TRANS_DISABLE,
28 SMMU_TRANS_ABORT,
29 SMMU_TRANS_BYPASS,
30 SMMU_TRANS_ERROR,
31 SMMU_TRANS_SUCCESS,
32} SMMUTranslationStatus;
33
34
35
36REG32(IDR0, 0x0)
37 FIELD(IDR0, S1P, 1 , 1)
38 FIELD(IDR0, TTF, 2 , 2)
39 FIELD(IDR0, COHACC, 4 , 1)
40 FIELD(IDR0, ASID16, 12, 1)
41 FIELD(IDR0, TTENDIAN, 21, 2)
42 FIELD(IDR0, STALL_MODEL, 24, 2)
43 FIELD(IDR0, TERM_MODEL, 26, 1)
44 FIELD(IDR0, STLEVEL, 27, 2)
45
46REG32(IDR1, 0x4)
47 FIELD(IDR1, SIDSIZE, 0 , 6)
48 FIELD(IDR1, EVENTQS, 16, 5)
49 FIELD(IDR1, CMDQS, 21, 5)
50
51#define SMMU_IDR1_SIDSIZE 16
52#define SMMU_CMDQS 19
53#define SMMU_EVENTQS 19
54
55REG32(IDR2, 0x8)
56REG32(IDR3, 0xc)
57 FIELD(IDR3, HAD, 2, 1);
58 FIELD(IDR3, RIL, 10, 1);
59REG32(IDR4, 0x10)
60REG32(IDR5, 0x14)
61 FIELD(IDR5, OAS, 0, 3);
62 FIELD(IDR5, GRAN4K, 4, 1);
63 FIELD(IDR5, GRAN16K, 5, 1);
64 FIELD(IDR5, GRAN64K, 6, 1);
65
66#define SMMU_IDR5_OAS 4
67
68REG32(IIDR, 0x18)
69REG32(AIDR, 0x1c)
70REG32(CR0, 0x20)
71 FIELD(CR0, SMMU_ENABLE, 0, 1)
72 FIELD(CR0, EVENTQEN, 2, 1)
73 FIELD(CR0, CMDQEN, 3, 1)
74
75#define SMMU_CR0_RESERVED 0xFFFFFC20
76
77REG32(CR0ACK, 0x24)
78REG32(CR1, 0x28)
79REG32(CR2, 0x2c)
80REG32(STATUSR, 0x40)
81REG32(IRQ_CTRL, 0x50)
82 FIELD(IRQ_CTRL, GERROR_IRQEN, 0, 1)
83 FIELD(IRQ_CTRL, PRI_IRQEN, 1, 1)
84 FIELD(IRQ_CTRL, EVENTQ_IRQEN, 2, 1)
85
86REG32(IRQ_CTRL_ACK, 0x54)
87REG32(GERROR, 0x60)
88 FIELD(GERROR, CMDQ_ERR, 0, 1)
89 FIELD(GERROR, EVENTQ_ABT_ERR, 2, 1)
90 FIELD(GERROR, PRIQ_ABT_ERR, 3, 1)
91 FIELD(GERROR, MSI_CMDQ_ABT_ERR, 4, 1)
92 FIELD(GERROR, MSI_EVENTQ_ABT_ERR, 5, 1)
93 FIELD(GERROR, MSI_PRIQ_ABT_ERR, 6, 1)
94 FIELD(GERROR, MSI_GERROR_ABT_ERR, 7, 1)
95 FIELD(GERROR, MSI_SFM_ERR, 8, 1)
96
97REG32(GERRORN, 0x64)
98
99#define A_GERROR_IRQ_CFG0 0x68
100REG32(GERROR_IRQ_CFG1, 0x70)
101REG32(GERROR_IRQ_CFG2, 0x74)
102
103#define A_STRTAB_BASE 0x80
104
105#define SMMU_BASE_ADDR_MASK 0xfffffffffffc0
106
107REG32(STRTAB_BASE_CFG, 0x88)
108 FIELD(STRTAB_BASE_CFG, FMT, 16, 2)
109 FIELD(STRTAB_BASE_CFG, SPLIT, 6 , 5)
110 FIELD(STRTAB_BASE_CFG, LOG2SIZE, 0 , 6)
111
112#define A_CMDQ_BASE 0x90
113REG32(CMDQ_PROD, 0x98)
114REG32(CMDQ_CONS, 0x9c)
115 FIELD(CMDQ_CONS, ERR, 24, 7)
116
117#define A_EVENTQ_BASE 0xa0
118REG32(EVENTQ_PROD, 0xa8)
119REG32(EVENTQ_CONS, 0xac)
120
121#define A_EVENTQ_IRQ_CFG0 0xb0
122REG32(EVENTQ_IRQ_CFG1, 0xb8)
123REG32(EVENTQ_IRQ_CFG2, 0xbc)
124
125#define A_IDREGS 0xfd0
126
127static inline int smmu_enabled(SMMUv3State *s)
128{
129 return FIELD_EX32(s->cr[0], CR0, SMMU_ENABLE);
130}
131
132
133typedef struct Cmd {
134 uint32_t word[4];
135} Cmd;
136
137
138typedef struct Evt {
139 uint32_t word[8];
140} Evt;
141
142static inline uint32_t smmuv3_idreg(int regoffset)
143{
144
145
146
147
148
149 static const uint8_t smmuv3_ids[] = {
150 0x04, 0, 0, 0, 0x84, 0xB4, 0xF0, 0x10, 0x0D, 0xF0, 0x05, 0xB1
151 };
152 return smmuv3_ids[regoffset / 4];
153}
154
155static inline bool smmuv3_eventq_irq_enabled(SMMUv3State *s)
156{
157 return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, EVENTQ_IRQEN);
158}
159
160static inline bool smmuv3_gerror_irq_enabled(SMMUv3State *s)
161{
162 return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, GERROR_IRQEN);
163}
164
165
166
167#define Q_BASE(q) ((q)->base & SMMU_BASE_ADDR_MASK)
168#define WRAP_MASK(q) (1 << (q)->log2size)
169#define INDEX_MASK(q) (((1 << (q)->log2size)) - 1)
170#define WRAP_INDEX_MASK(q) ((1 << ((q)->log2size + 1)) - 1)
171
172#define Q_CONS(q) ((q)->cons & INDEX_MASK(q))
173#define Q_PROD(q) ((q)->prod & INDEX_MASK(q))
174
175#define Q_CONS_ENTRY(q) (Q_BASE(q) + (q)->entry_size * Q_CONS(q))
176#define Q_PROD_ENTRY(q) (Q_BASE(q) + (q)->entry_size * Q_PROD(q))
177
178#define Q_CONS_WRAP(q) (((q)->cons & WRAP_MASK(q)) >> (q)->log2size)
179#define Q_PROD_WRAP(q) (((q)->prod & WRAP_MASK(q)) >> (q)->log2size)
180
181static inline bool smmuv3_q_full(SMMUQueue *q)
182{
183 return ((q->cons ^ q->prod) & WRAP_INDEX_MASK(q)) == WRAP_MASK(q);
184}
185
186static inline bool smmuv3_q_empty(SMMUQueue *q)
187{
188 return (q->cons & WRAP_INDEX_MASK(q)) == (q->prod & WRAP_INDEX_MASK(q));
189}
190
191static inline void queue_prod_incr(SMMUQueue *q)
192{
193 q->prod = (q->prod + 1) & WRAP_INDEX_MASK(q);
194}
195
196static inline void queue_cons_incr(SMMUQueue *q)
197{
198
199
200
201
202 q->cons = deposit32(q->cons, 0, q->log2size + 1, q->cons + 1);
203}
204
205static inline bool smmuv3_cmdq_enabled(SMMUv3State *s)
206{
207 return FIELD_EX32(s->cr[0], CR0, CMDQEN);
208}
209
210static inline bool smmuv3_eventq_enabled(SMMUv3State *s)
211{
212 return FIELD_EX32(s->cr[0], CR0, EVENTQEN);
213}
214
215static inline void smmu_write_cmdq_err(SMMUv3State *s, uint32_t err_type)
216{
217 s->cmdq.cons = FIELD_DP32(s->cmdq.cons, CMDQ_CONS, ERR, err_type);
218}
219
220
221
222typedef enum SMMUCommandType {
223 SMMU_CMD_NONE = 0x00,
224 SMMU_CMD_PREFETCH_CONFIG ,
225 SMMU_CMD_PREFETCH_ADDR,
226 SMMU_CMD_CFGI_STE,
227 SMMU_CMD_CFGI_STE_RANGE,
228 SMMU_CMD_CFGI_CD,
229 SMMU_CMD_CFGI_CD_ALL,
230 SMMU_CMD_CFGI_ALL,
231 SMMU_CMD_TLBI_NH_ALL = 0x10,
232 SMMU_CMD_TLBI_NH_ASID,
233 SMMU_CMD_TLBI_NH_VA,
234 SMMU_CMD_TLBI_NH_VAA,
235 SMMU_CMD_TLBI_EL3_ALL = 0x18,
236 SMMU_CMD_TLBI_EL3_VA = 0x1a,
237 SMMU_CMD_TLBI_EL2_ALL = 0x20,
238 SMMU_CMD_TLBI_EL2_ASID,
239 SMMU_CMD_TLBI_EL2_VA,
240 SMMU_CMD_TLBI_EL2_VAA,
241 SMMU_CMD_TLBI_S12_VMALL = 0x28,
242 SMMU_CMD_TLBI_S2_IPA = 0x2a,
243 SMMU_CMD_TLBI_NSNH_ALL = 0x30,
244 SMMU_CMD_ATC_INV = 0x40,
245 SMMU_CMD_PRI_RESP,
246 SMMU_CMD_RESUME = 0x44,
247 SMMU_CMD_STALL_TERM,
248 SMMU_CMD_SYNC,
249} SMMUCommandType;
250
251static const char *cmd_stringify[] = {
252 [SMMU_CMD_PREFETCH_CONFIG] = "SMMU_CMD_PREFETCH_CONFIG",
253 [SMMU_CMD_PREFETCH_ADDR] = "SMMU_CMD_PREFETCH_ADDR",
254 [SMMU_CMD_CFGI_STE] = "SMMU_CMD_CFGI_STE",
255 [SMMU_CMD_CFGI_STE_RANGE] = "SMMU_CMD_CFGI_STE_RANGE",
256 [SMMU_CMD_CFGI_CD] = "SMMU_CMD_CFGI_CD",
257 [SMMU_CMD_CFGI_CD_ALL] = "SMMU_CMD_CFGI_CD_ALL",
258 [SMMU_CMD_CFGI_ALL] = "SMMU_CMD_CFGI_ALL",
259 [SMMU_CMD_TLBI_NH_ALL] = "SMMU_CMD_TLBI_NH_ALL",
260 [SMMU_CMD_TLBI_NH_ASID] = "SMMU_CMD_TLBI_NH_ASID",
261 [SMMU_CMD_TLBI_NH_VA] = "SMMU_CMD_TLBI_NH_VA",
262 [SMMU_CMD_TLBI_NH_VAA] = "SMMU_CMD_TLBI_NH_VAA",
263 [SMMU_CMD_TLBI_EL3_ALL] = "SMMU_CMD_TLBI_EL3_ALL",
264 [SMMU_CMD_TLBI_EL3_VA] = "SMMU_CMD_TLBI_EL3_VA",
265 [SMMU_CMD_TLBI_EL2_ALL] = "SMMU_CMD_TLBI_EL2_ALL",
266 [SMMU_CMD_TLBI_EL2_ASID] = "SMMU_CMD_TLBI_EL2_ASID",
267 [SMMU_CMD_TLBI_EL2_VA] = "SMMU_CMD_TLBI_EL2_VA",
268 [SMMU_CMD_TLBI_EL2_VAA] = "SMMU_CMD_TLBI_EL2_VAA",
269 [SMMU_CMD_TLBI_S12_VMALL] = "SMMU_CMD_TLBI_S12_VMALL",
270 [SMMU_CMD_TLBI_S2_IPA] = "SMMU_CMD_TLBI_S2_IPA",
271 [SMMU_CMD_TLBI_NSNH_ALL] = "SMMU_CMD_TLBI_NSNH_ALL",
272 [SMMU_CMD_ATC_INV] = "SMMU_CMD_ATC_INV",
273 [SMMU_CMD_PRI_RESP] = "SMMU_CMD_PRI_RESP",
274 [SMMU_CMD_RESUME] = "SMMU_CMD_RESUME",
275 [SMMU_CMD_STALL_TERM] = "SMMU_CMD_STALL_TERM",
276 [SMMU_CMD_SYNC] = "SMMU_CMD_SYNC",
277};
278
279static inline const char *smmu_cmd_string(SMMUCommandType type)
280{
281 if (type > SMMU_CMD_NONE && type < ARRAY_SIZE(cmd_stringify)) {
282 return cmd_stringify[type] ? cmd_stringify[type] : "UNKNOWN";
283 } else {
284 return "INVALID";
285 }
286}
287
288
289
290typedef enum {
291 SMMU_CERROR_NONE = 0,
292 SMMU_CERROR_ILL,
293 SMMU_CERROR_ABT,
294 SMMU_CERROR_ATC_INV_SYNC,
295} SMMUCmdError;
296
297enum {
298 CMD_SYNC_SIG_NONE,
299 CMD_SYNC_SIG_IRQ,
300 CMD_SYNC_SIG_SEV,
301};
302
303#define CMD_TYPE(x) extract32((x)->word[0], 0 , 8)
304#define CMD_NUM(x) extract32((x)->word[0], 12 , 5)
305#define CMD_SCALE(x) extract32((x)->word[0], 20 , 5)
306#define CMD_SSEC(x) extract32((x)->word[0], 10, 1)
307#define CMD_SSV(x) extract32((x)->word[0], 11, 1)
308#define CMD_RESUME_AC(x) extract32((x)->word[0], 12, 1)
309#define CMD_RESUME_AB(x) extract32((x)->word[0], 13, 1)
310#define CMD_SYNC_CS(x) extract32((x)->word[0], 12, 2)
311#define CMD_SSID(x) extract32((x)->word[0], 12, 20)
312#define CMD_SID(x) ((x)->word[1])
313#define CMD_VMID(x) extract32((x)->word[1], 0 , 16)
314#define CMD_ASID(x) extract32((x)->word[1], 16, 16)
315#define CMD_RESUME_STAG(x) extract32((x)->word[2], 0 , 16)
316#define CMD_RESP(x) extract32((x)->word[2], 11, 2)
317#define CMD_LEAF(x) extract32((x)->word[2], 0 , 1)
318#define CMD_TTL(x) extract32((x)->word[2], 8 , 2)
319#define CMD_TG(x) extract32((x)->word[2], 10, 2)
320#define CMD_STE_RANGE(x) extract32((x)->word[2], 0 , 5)
321#define CMD_ADDR(x) ({ \
322 uint64_t high = (uint64_t)(x)->word[3]; \
323 uint64_t low = extract32((x)->word[2], 12, 20); \
324 uint64_t addr = high << 32 | (low << 12); \
325 addr; \
326 })
327
328#define SMMU_FEATURE_2LVL_STE (1 << 0)
329
330
331
332typedef enum SMMUEventType {
333 SMMU_EVT_NONE = 0x00,
334 SMMU_EVT_F_UUT ,
335 SMMU_EVT_C_BAD_STREAMID ,
336 SMMU_EVT_F_STE_FETCH ,
337 SMMU_EVT_C_BAD_STE ,
338 SMMU_EVT_F_BAD_ATS_TREQ ,
339 SMMU_EVT_F_STREAM_DISABLED ,
340 SMMU_EVT_F_TRANS_FORBIDDEN ,
341 SMMU_EVT_C_BAD_SUBSTREAMID ,
342 SMMU_EVT_F_CD_FETCH ,
343 SMMU_EVT_C_BAD_CD ,
344 SMMU_EVT_F_WALK_EABT ,
345 SMMU_EVT_F_TRANSLATION = 0x10,
346 SMMU_EVT_F_ADDR_SIZE ,
347 SMMU_EVT_F_ACCESS ,
348 SMMU_EVT_F_PERMISSION ,
349 SMMU_EVT_F_TLB_CONFLICT = 0x20,
350 SMMU_EVT_F_CFG_CONFLICT ,
351 SMMU_EVT_E_PAGE_REQ = 0x24,
352} SMMUEventType;
353
354static const char *event_stringify[] = {
355 [SMMU_EVT_NONE] = "no recorded event",
356 [SMMU_EVT_F_UUT] = "SMMU_EVT_F_UUT",
357 [SMMU_EVT_C_BAD_STREAMID] = "SMMU_EVT_C_BAD_STREAMID",
358 [SMMU_EVT_F_STE_FETCH] = "SMMU_EVT_F_STE_FETCH",
359 [SMMU_EVT_C_BAD_STE] = "SMMU_EVT_C_BAD_STE",
360 [SMMU_EVT_F_BAD_ATS_TREQ] = "SMMU_EVT_F_BAD_ATS_TREQ",
361 [SMMU_EVT_F_STREAM_DISABLED] = "SMMU_EVT_F_STREAM_DISABLED",
362 [SMMU_EVT_F_TRANS_FORBIDDEN] = "SMMU_EVT_F_TRANS_FORBIDDEN",
363 [SMMU_EVT_C_BAD_SUBSTREAMID] = "SMMU_EVT_C_BAD_SUBSTREAMID",
364 [SMMU_EVT_F_CD_FETCH] = "SMMU_EVT_F_CD_FETCH",
365 [SMMU_EVT_C_BAD_CD] = "SMMU_EVT_C_BAD_CD",
366 [SMMU_EVT_F_WALK_EABT] = "SMMU_EVT_F_WALK_EABT",
367 [SMMU_EVT_F_TRANSLATION] = "SMMU_EVT_F_TRANSLATION",
368 [SMMU_EVT_F_ADDR_SIZE] = "SMMU_EVT_F_ADDR_SIZE",
369 [SMMU_EVT_F_ACCESS] = "SMMU_EVT_F_ACCESS",
370 [SMMU_EVT_F_PERMISSION] = "SMMU_EVT_F_PERMISSION",
371 [SMMU_EVT_F_TLB_CONFLICT] = "SMMU_EVT_F_TLB_CONFLICT",
372 [SMMU_EVT_F_CFG_CONFLICT] = "SMMU_EVT_F_CFG_CONFLICT",
373 [SMMU_EVT_E_PAGE_REQ] = "SMMU_EVT_E_PAGE_REQ",
374};
375
376static inline const char *smmu_event_string(SMMUEventType type)
377{
378 if (type < ARRAY_SIZE(event_stringify)) {
379 return event_stringify[type] ? event_stringify[type] : "UNKNOWN";
380 } else {
381 return "INVALID";
382 }
383}
384
385
386typedef struct SMMUEventInfo {
387 SMMUEventType type;
388 uint32_t sid;
389 bool recorded;
390 bool record_trans_faults;
391 bool inval_ste_allowed;
392 union {
393 struct {
394 uint32_t ssid;
395 bool ssv;
396 dma_addr_t addr;
397 bool rnw;
398 bool pnu;
399 bool ind;
400 } f_uut;
401 struct SSIDInfo {
402 uint32_t ssid;
403 bool ssv;
404 } c_bad_streamid;
405 struct SSIDAddrInfo {
406 uint32_t ssid;
407 bool ssv;
408 dma_addr_t addr;
409 } f_ste_fetch;
410 struct SSIDInfo c_bad_ste;
411 struct {
412 dma_addr_t addr;
413 bool rnw;
414 } f_transl_forbidden;
415 struct {
416 uint32_t ssid;
417 } c_bad_substream;
418 struct SSIDAddrInfo f_cd_fetch;
419 struct SSIDInfo c_bad_cd;
420 struct FullInfo {
421 bool stall;
422 uint16_t stag;
423 uint32_t ssid;
424 bool ssv;
425 bool s2;
426 dma_addr_t addr;
427 bool rnw;
428 bool pnu;
429 bool ind;
430 uint8_t class;
431 dma_addr_t addr2;
432 } f_walk_eabt;
433 struct FullInfo f_translation;
434 struct FullInfo f_addr_size;
435 struct FullInfo f_access;
436 struct FullInfo f_permission;
437 struct SSIDInfo f_cfg_conflict;
438
439
440
441
442
443
444
445
446 } u;
447} SMMUEventInfo;
448
449
450
451#define EVT_Q_OVERFLOW (1 << 31)
452
453#define EVT_SET_TYPE(x, v) ((x)->word[0] = deposit32((x)->word[0], 0 , 8 , v))
454#define EVT_SET_SSV(x, v) ((x)->word[0] = deposit32((x)->word[0], 11, 1 , v))
455#define EVT_SET_SSID(x, v) ((x)->word[0] = deposit32((x)->word[0], 12, 20, v))
456#define EVT_SET_SID(x, v) ((x)->word[1] = v)
457#define EVT_SET_STAG(x, v) ((x)->word[2] = deposit32((x)->word[2], 0 , 16, v))
458#define EVT_SET_STALL(x, v) ((x)->word[2] = deposit32((x)->word[2], 31, 1 , v))
459#define EVT_SET_PNU(x, v) ((x)->word[3] = deposit32((x)->word[3], 1 , 1 , v))
460#define EVT_SET_IND(x, v) ((x)->word[3] = deposit32((x)->word[3], 2 , 1 , v))
461#define EVT_SET_RNW(x, v) ((x)->word[3] = deposit32((x)->word[3], 3 , 1 , v))
462#define EVT_SET_S2(x, v) ((x)->word[3] = deposit32((x)->word[3], 7 , 1 , v))
463#define EVT_SET_CLASS(x, v) ((x)->word[3] = deposit32((x)->word[3], 8 , 2 , v))
464#define EVT_SET_ADDR(x, addr) \
465 do { \
466 (x)->word[5] = (uint32_t)(addr >> 32); \
467 (x)->word[4] = (uint32_t)(addr & 0xffffffff); \
468 } while (0)
469#define EVT_SET_ADDR2(x, addr) \
470 do { \
471 (x)->word[7] = (uint32_t)(addr >> 32); \
472 (x)->word[6] = (uint32_t)(addr & 0xffffffff); \
473 } while (0)
474
475void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event);
476
477
478
479
480typedef struct STEDesc {
481 uint32_t word[2];
482} STEDesc;
483
484
485typedef struct CDDesc {
486 uint32_t word[2];
487} CDDesc;
488
489
490typedef struct STE {
491 uint32_t word[16];
492} STE;
493
494
495typedef struct CD {
496 uint32_t word[16];
497} CD;
498
499
500
501#define STE_VALID(x) extract32((x)->word[0], 0, 1)
502
503#define STE_CONFIG(x) extract32((x)->word[0], 1, 3)
504#define STE_CFG_S1_ENABLED(config) (config & 0x1)
505#define STE_CFG_S2_ENABLED(config) (config & 0x2)
506#define STE_CFG_ABORT(config) (!(config & 0x4))
507#define STE_CFG_BYPASS(config) (config == 0x4)
508
509#define STE_S1FMT(x) extract32((x)->word[0], 4 , 2)
510#define STE_S1CDMAX(x) extract32((x)->word[1], 27, 5)
511#define STE_S1STALLD(x) extract32((x)->word[2], 27, 1)
512#define STE_EATS(x) extract32((x)->word[2], 28, 2)
513#define STE_STRW(x) extract32((x)->word[2], 30, 2)
514#define STE_S2VMID(x) extract32((x)->word[4], 0 , 16)
515#define STE_S2T0SZ(x) extract32((x)->word[5], 0 , 6)
516#define STE_S2SL0(x) extract32((x)->word[5], 6 , 2)
517#define STE_S2TG(x) extract32((x)->word[5], 14, 2)
518#define STE_S2PS(x) extract32((x)->word[5], 16, 3)
519#define STE_S2AA64(x) extract32((x)->word[5], 19, 1)
520#define STE_S2HD(x) extract32((x)->word[5], 24, 1)
521#define STE_S2HA(x) extract32((x)->word[5], 25, 1)
522#define STE_S2S(x) extract32((x)->word[5], 26, 1)
523#define STE_CTXPTR(x) \
524 ({ \
525 unsigned long addr; \
526 addr = (uint64_t)extract32((x)->word[1], 0, 16) << 32; \
527 addr |= (uint64_t)((x)->word[0] & 0xffffffc0); \
528 addr; \
529 })
530
531#define STE_S2TTB(x) \
532 ({ \
533 unsigned long addr; \
534 addr = (uint64_t)extract32((x)->word[7], 0, 16) << 32; \
535 addr |= (uint64_t)((x)->word[6] & 0xfffffff0); \
536 addr; \
537 })
538
539static inline int oas2bits(int oas_field)
540{
541 switch (oas_field) {
542 case 0:
543 return 32;
544 case 1:
545 return 36;
546 case 2:
547 return 40;
548 case 3:
549 return 42;
550 case 4:
551 return 44;
552 case 5:
553 return 48;
554 }
555 return -1;
556}
557
558static inline int pa_range(STE *ste)
559{
560 int oas_field = MIN(STE_S2PS(ste), SMMU_IDR5_OAS);
561
562 if (!STE_S2AA64(ste)) {
563 return 40;
564 }
565
566 return oas2bits(oas_field);
567}
568
569#define MAX_PA(ste) ((1 << pa_range(ste)) - 1)
570
571
572
573#define CD_VALID(x) extract32((x)->word[0], 31, 1)
574#define CD_ASID(x) extract32((x)->word[1], 16, 16)
575#define CD_TTB(x, sel) \
576 ({ \
577 uint64_t hi, lo; \
578 hi = extract32((x)->word[(sel) * 2 + 3], 0, 19); \
579 hi <<= 32; \
580 lo = (x)->word[(sel) * 2 + 2] & ~0xfULL; \
581 hi | lo; \
582 })
583#define CD_HAD(x, sel) extract32((x)->word[(sel) * 2 + 2], 1, 1)
584
585#define CD_TSZ(x, sel) extract32((x)->word[0], (16 * (sel)) + 0, 6)
586#define CD_TG(x, sel) extract32((x)->word[0], (16 * (sel)) + 6, 2)
587#define CD_EPD(x, sel) extract32((x)->word[0], (16 * (sel)) + 14, 1)
588#define CD_ENDI(x) extract32((x)->word[0], 15, 1)
589#define CD_IPS(x) extract32((x)->word[1], 0 , 3)
590#define CD_TBI(x) extract32((x)->word[1], 6 , 2)
591#define CD_HD(x) extract32((x)->word[1], 10 , 1)
592#define CD_HA(x) extract32((x)->word[1], 11 , 1)
593#define CD_S(x) extract32((x)->word[1], 12, 1)
594#define CD_R(x) extract32((x)->word[1], 13, 1)
595#define CD_A(x) extract32((x)->word[1], 14, 1)
596#define CD_AARCH64(x) extract32((x)->word[1], 9 , 1)
597
598
599
600
601
602
603
604static inline int tg2granule(int bits, int ttbr)
605{
606 switch (bits) {
607 case 0:
608 return ttbr ? 0 : 12;
609 case 1:
610 return ttbr ? 14 : 16;
611 case 2:
612 return ttbr ? 12 : 14;
613 case 3:
614 return ttbr ? 16 : 0;
615 default:
616 return 0;
617 }
618}
619
620static inline uint64_t l1std_l2ptr(STEDesc *desc)
621{
622 uint64_t hi, lo;
623
624 hi = desc->word[1];
625 lo = desc->word[0] & ~0x1fULL;
626 return hi << 32 | lo;
627}
628
629#define L1STD_SPAN(stm) (extract32((stm)->word[0], 0, 5))
630
631#endif
632
