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10#include "qemu/osdep.h"
11#include "qemu/log.h"
12#include "qemu/module.h"
13#include "qapi/error.h"
14#include "target/ppc/cpu.h"
15#include "sysemu/cpus.h"
16#include "sysemu/dma.h"
17#include "hw/qdev-properties.h"
18#include "monitor/monitor.h"
19#include "hw/ppc/xive.h"
20#include "hw/ppc/xive2.h"
21#include "hw/ppc/xive2_regs.h"
22
23uint32_t xive2_router_get_config(Xive2Router *xrtr)
24{
25 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
26
27 return xrc->get_config(xrtr);
28}
29
30void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, Monitor *mon)
31{
32 if (!xive2_eas_is_valid(eas)) {
33 return;
34 }
35
36 monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n",
37 lisn, xive2_eas_is_masked(eas) ? "M" : " ",
38 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w),
39 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w),
40 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w));
41}
42
43void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width,
44 Monitor *mon)
45{
46 uint64_t qaddr_base = xive2_end_qaddr(end);
47 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3);
48 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1);
49 uint32_t qentries = 1 << (qsize + 10);
50 int i;
51
52
53
54
55 monitor_printf(mon, " [ ");
56 qindex = (qindex - (width - 1)) & (qentries - 1);
57 for (i = 0; i < width; i++) {
58 uint64_t qaddr = qaddr_base + (qindex << 2);
59 uint32_t qdata = -1;
60
61 if (dma_memory_read(&address_space_memory, qaddr, &qdata,
62 sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) {
63 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%"
64 HWADDR_PRIx "\n", qaddr);
65 return;
66 }
67 monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "",
68 be32_to_cpu(qdata));
69 qindex = (qindex + 1) & (qentries - 1);
70 }
71 monitor_printf(mon, "]");
72}
73
74void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, Monitor *mon)
75{
76 uint64_t qaddr_base = xive2_end_qaddr(end);
77 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1);
78 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1);
79 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3);
80 uint32_t qentries = 1 << (qsize + 10);
81
82 uint32_t nvp_blk = xive_get_field32(END2_W6_VP_BLOCK, end->w6);
83 uint32_t nvp_idx = xive_get_field32(END2_W6_VP_OFFSET, end->w6);
84 uint8_t priority = xive_get_field32(END2_W7_F0_PRIORITY, end->w7);
85 uint8_t pq;
86
87 if (!xive2_end_is_valid(end)) {
88 return;
89 }
90
91 pq = xive_get_field32(END2_W1_ESn, end->w1);
92
93 monitor_printf(mon,
94 " %08x %c%c %c%c%c%c%c%c%c%c%c%c prio:%d nvp:%02x/%04x",
95 end_idx,
96 pq & XIVE_ESB_VAL_P ? 'P' : '-',
97 pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
98 xive2_end_is_valid(end) ? 'v' : '-',
99 xive2_end_is_enqueue(end) ? 'q' : '-',
100 xive2_end_is_notify(end) ? 'n' : '-',
101 xive2_end_is_backlog(end) ? 'b' : '-',
102 xive2_end_is_escalate(end) ? 'e' : '-',
103 xive2_end_is_escalate_end(end) ? 'N' : '-',
104 xive2_end_is_uncond_escalation(end) ? 'u' : '-',
105 xive2_end_is_silent_escalation(end) ? 's' : '-',
106 xive2_end_is_firmware1(end) ? 'f' : '-',
107 xive2_end_is_firmware2(end) ? 'F' : '-',
108 priority, nvp_blk, nvp_idx);
109
110 if (qaddr_base) {
111 monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d",
112 qaddr_base, qindex, qentries, qgen);
113 xive2_end_queue_pic_print_info(end, 6, mon);
114 }
115 monitor_printf(mon, "\n");
116}
117
118void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx,
119 Monitor *mon)
120{
121 Xive2Eas *eas = (Xive2Eas *) &end->w4;
122 uint8_t pq;
123
124 if (!xive2_end_is_escalate(end)) {
125 return;
126 }
127
128 pq = xive_get_field32(END2_W1_ESe, end->w1);
129
130 monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n",
131 end_idx,
132 pq & XIVE_ESB_VAL_P ? 'P' : '-',
133 pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
134 xive2_eas_is_valid(eas) ? 'v' : ' ',
135 xive2_eas_is_masked(eas) ? 'M' : ' ',
136 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w),
137 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w),
138 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w));
139}
140
141static void xive2_end_enqueue(Xive2End *end, uint32_t data)
142{
143 uint64_t qaddr_base = xive2_end_qaddr(end);
144 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3);
145 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1);
146 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1);
147
148 uint64_t qaddr = qaddr_base + (qindex << 2);
149 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff));
150 uint32_t qentries = 1 << (qsize + 10);
151
152 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata),
153 MEMTXATTRS_UNSPECIFIED)) {
154 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%"
155 HWADDR_PRIx "\n", qaddr);
156 return;
157 }
158
159 qindex = (qindex + 1) & (qentries - 1);
160 if (qindex == 0) {
161 qgen ^= 1;
162 end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen);
163
164
165 end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, qgen);
166 }
167 end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex);
168}
169
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182
183
184
185static void xive2_tctx_save_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx,
186 uint8_t nvp_blk, uint32_t nvp_idx)
187{
188 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
189 uint32_t pir = env->spr_cb[SPR_PIR].default_value;
190 Xive2Nvp nvp;
191 uint8_t *regs = &tctx->regs[TM_QW1_OS];
192
193 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) {
194 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n",
195 nvp_blk, nvp_idx);
196 return;
197 }
198
199 if (!xive2_nvp_is_valid(&nvp)) {
200 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n",
201 nvp_blk, nvp_idx);
202 return;
203 }
204
205 if (!xive2_nvp_is_hw(&nvp)) {
206 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n",
207 nvp_blk, nvp_idx);
208 return;
209 }
210
211 if (!xive2_nvp_is_co(&nvp)) {
212 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not checkout\n",
213 nvp_blk, nvp_idx);
214 return;
215 }
216
217 if (xive_get_field32(NVP2_W1_CO_THRID_VALID, nvp.w1) &&
218 xive_get_field32(NVP2_W1_CO_THRID, nvp.w1) != pir) {
219 qemu_log_mask(LOG_GUEST_ERROR,
220 "XIVE: NVP %x/%x invalid checkout Thread %x\n",
221 nvp_blk, nvp_idx, pir);
222 return;
223 }
224
225 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, regs[TM_IPB]);
226 nvp.w2 = xive_set_field32(NVP2_W2_CPPR, nvp.w2, regs[TM_CPPR]);
227 nvp.w2 = xive_set_field32(NVP2_W2_LSMFB, nvp.w2, regs[TM_LSMFB]);
228 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
229
230 nvp.w1 = xive_set_field32(NVP2_W1_CO, nvp.w1, 0);
231
232 nvp.w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp.w1, 0xFFFF);
233 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 1);
234}
235
236static void xive2_os_cam_decode(uint32_t cam, uint8_t *nvp_blk,
237 uint32_t *nvp_idx, bool *vo, bool *ho)
238{
239 *nvp_blk = xive2_nvp_blk(cam);
240 *nvp_idx = xive2_nvp_idx(cam);
241 *vo = !!(cam & TM2_QW1W2_VO);
242 *ho = !!(cam & TM2_QW1W2_HO);
243}
244
245uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
246 hwaddr offset, unsigned size)
247{
248 Xive2Router *xrtr = XIVE2_ROUTER(xptr);
249 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
250 uint32_t qw1w2_new;
251 uint32_t cam = be32_to_cpu(qw1w2);
252 uint8_t nvp_blk;
253 uint32_t nvp_idx;
254 bool vo;
255 bool do_save;
256
257 xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_save);
258
259 if (!vo) {
260 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVP %x/%x !?\n",
261 nvp_blk, nvp_idx);
262 }
263
264
265 qw1w2_new = xive_set_field32(TM2_QW1W2_VO, qw1w2, 0);
266 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2_new, 4);
267
268 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) {
269 xive2_tctx_save_os_ctx(xrtr, tctx, nvp_blk, nvp_idx);
270 }
271
272 return qw1w2;
273}
274
275static uint8_t xive2_tctx_restore_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx,
276 uint8_t nvp_blk, uint32_t nvp_idx,
277 Xive2Nvp *nvp)
278{
279 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
280 uint32_t pir = env->spr_cb[SPR_PIR].default_value;
281 uint8_t cppr;
282
283 if (!xive2_nvp_is_hw(nvp)) {
284 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n",
285 nvp_blk, nvp_idx);
286 return 0;
287 }
288
289 cppr = xive_get_field32(NVP2_W2_CPPR, nvp->w2);
290 nvp->w2 = xive_set_field32(NVP2_W2_CPPR, nvp->w2, 0);
291 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 2);
292
293 tctx->regs[TM_QW1_OS + TM_CPPR] = cppr;
294
295
296 nvp->w1 = xive_set_field32(NVP2_W1_CO, nvp->w1, 1);
297 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID_VALID, nvp->w1, 1);
298 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp->w1, pir);
299
300
301
302
303
304
305 nvp->w1 = xive_set_field32(NVP2_W1_CO_PRIV, nvp->w1, 0);
306
307 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 1);
308
309
310 return cppr;
311}
312
313static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx,
314 uint8_t nvp_blk, uint32_t nvp_idx,
315 bool do_restore)
316{
317 Xive2Nvp nvp;
318 uint8_t ipb;
319 uint8_t cppr = 0;
320
321
322
323
324
325 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) {
326 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n",
327 nvp_blk, nvp_idx);
328 return;
329 }
330
331 if (!xive2_nvp_is_valid(&nvp)) {
332 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n",
333 nvp_blk, nvp_idx);
334 return;
335 }
336
337
338 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE &&
339 do_restore) {
340 cppr = xive2_tctx_restore_os_ctx(xrtr, tctx, nvp_blk, nvp_idx, &nvp);
341 }
342
343 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2);
344 if (ipb) {
345 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, 0);
346 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
347 }
348
349
350 if (ipb || cppr) {
351 xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb);
352 }
353}
354
355
356
357
358void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
359 hwaddr offset, uint64_t value, unsigned size)
360{
361 uint32_t cam = value;
362 uint32_t qw1w2 = cpu_to_be32(cam);
363 uint8_t nvp_blk;
364 uint32_t nvp_idx;
365 bool vo;
366 bool do_restore;
367
368 xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore);
369
370
371 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
372
373
374 if (vo) {
375 xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, nvp_blk, nvp_idx,
376 do_restore);
377 }
378}
379
380
381
382
383
384int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
385 Xive2Eas *eas)
386{
387 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
388
389 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas);
390}
391
392static
393int xive2_router_get_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
394 uint8_t *pq)
395{
396 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
397
398 return xrc->get_pq(xrtr, eas_blk, eas_idx, pq);
399}
400
401static
402int xive2_router_set_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
403 uint8_t *pq)
404{
405 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
406
407 return xrc->set_pq(xrtr, eas_blk, eas_idx, pq);
408}
409
410int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
411 Xive2End *end)
412{
413 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
414
415 return xrc->get_end(xrtr, end_blk, end_idx, end);
416}
417
418int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
419 Xive2End *end, uint8_t word_number)
420{
421 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
422
423 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number);
424}
425
426int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
427 Xive2Nvp *nvp)
428{
429 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
430
431 return xrc->get_nvp(xrtr, nvp_blk, nvp_idx, nvp);
432}
433
434int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
435 Xive2Nvp *nvp, uint8_t word_number)
436{
437 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
438
439 return xrc->write_nvp(xrtr, nvp_blk, nvp_idx, nvp, word_number);
440}
441
442static int xive2_router_get_block_id(Xive2Router *xrtr)
443{
444 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
445
446 return xrc->get_block_id(xrtr);
447}
448
449
450
451
452
453
454
455
456static uint32_t xive2_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx)
457{
458 Xive2Router *xrtr = XIVE2_ROUTER(xptr);
459 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
460 uint32_t pir = env->spr_cb[SPR_PIR].default_value;
461 uint8_t blk = xive2_router_get_block_id(xrtr);
462 uint8_t tid_shift =
463 xive2_router_get_config(xrtr) & XIVE2_THREADID_8BITS ? 8 : 7;
464 uint8_t tid_mask = (1 << tid_shift) - 1;
465
466 return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask));
467}
468
469
470
471
472int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
473 uint8_t format,
474 uint8_t nvt_blk, uint32_t nvt_idx,
475 bool cam_ignore, uint32_t logic_serv)
476{
477 uint32_t cam = xive2_nvp_cam_line(nvt_blk, nvt_idx);
478 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]);
479 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]);
480 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
481 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]);
482
483
484
485
486
487
488 if (format == 0) {
489 if (cam_ignore == true) {
490
491
492
493
494 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n",
495 nvt_blk, nvt_idx);
496 return -1;
497 }
498
499
500
501
502 if ((be32_to_cpu(qw3w2) & TM2_QW3W2_VT) &&
503 cam == xive2_tctx_hw_cam_line(xptr, tctx)) {
504 return TM_QW3_HV_PHYS;
505 }
506
507
508 if ((be32_to_cpu(qw2w2) & TM2_QW2W2_VP) &&
509 cam == xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2)) {
510 return TM_QW2_HV_POOL;
511 }
512
513
514 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) &&
515 cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) {
516 return TM_QW1_OS;
517 }
518 } else {
519
520
521
522 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) &&
523 (cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) &&
524 (be32_to_cpu(qw0w2) & TM2_QW0W2_VU) &&
525 (logic_serv == xive_get_field32(TM2_QW0W2_LOGIC_SERV, qw0w2))) {
526 return TM_QW0_USER;
527 }
528 }
529 return -1;
530}
531
532static void xive2_router_realize(DeviceState *dev, Error **errp)
533{
534 Xive2Router *xrtr = XIVE2_ROUTER(dev);
535
536 assert(xrtr->xfb);
537}
538
539
540
541
542
543
544static bool xive2_router_end_es_notify(Xive2Router *xrtr, uint8_t end_blk,
545 uint32_t end_idx, Xive2End *end,
546 uint32_t end_esmask)
547{
548 uint8_t pq = xive_get_field32(end_esmask, end->w1);
549 bool notify = xive_esb_trigger(&pq);
550
551 if (pq != xive_get_field32(end_esmask, end->w1)) {
552 end->w1 = xive_set_field32(end_esmask, end->w1, pq);
553 xive2_router_write_end(xrtr, end_blk, end_idx, end, 1);
554 }
555
556
557 return notify;
558}
559
560
561
562
563
564
565static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk,
566 uint32_t end_idx, uint32_t end_data)
567{
568 Xive2End end;
569 uint8_t priority;
570 uint8_t format;
571 bool found;
572 Xive2Nvp nvp;
573 uint8_t nvp_blk;
574 uint32_t nvp_idx;
575
576
577 if (xive2_router_get_end(xrtr, end_blk, end_idx, &end)) {
578 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk,
579 end_idx);
580 return;
581 }
582
583 if (!xive2_end_is_valid(&end)) {
584 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n",
585 end_blk, end_idx);
586 return;
587 }
588
589 if (xive2_end_is_enqueue(&end)) {
590 xive2_end_enqueue(&end, end_data);
591
592 xive2_router_write_end(xrtr, end_blk, end_idx, &end, 1);
593 }
594
595
596
597
598 if (xive2_end_is_silent_escalation(&end)) {
599 goto do_escalation;
600 }
601
602
603
604
605
606
607
608
609
610 format = xive_get_field32(END2_W6_FORMAT_BIT, end.w6);
611 priority = xive_get_field32(END2_W7_F0_PRIORITY, end.w7);
612
613
614 if (format == 0 && priority == 0xff) {
615 return;
616 }
617
618
619
620
621
622 if (!xive2_end_is_notify(&end)) {
623
624 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx,
625 &end, END2_W1_ESn)) {
626 return;
627 }
628 }
629
630
631
632
633 nvp_blk = xive_get_field32(END2_W6_VP_BLOCK, end.w6);
634 nvp_idx = xive_get_field32(END2_W6_VP_OFFSET, end.w6);
635
636
637 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) {
638 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVP %x/%x\n",
639 nvp_blk, nvp_idx);
640 return;
641 }
642
643 if (!xive2_nvp_is_valid(&nvp)) {
644 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is invalid\n",
645 nvp_blk, nvp_idx);
646 return;
647 }
648
649 found = xive_presenter_notify(xrtr->xfb, format, nvp_blk, nvp_idx,
650 xive_get_field32(END2_W6_IGNORE, end.w7),
651 priority,
652 xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w7));
653
654
655
656 if (found) {
657 return;
658 }
659
660
661
662
663
664
665 if (xive2_end_is_backlog(&end)) {
666 uint8_t ipb;
667
668 if (format == 1) {
669 qemu_log_mask(LOG_GUEST_ERROR,
670 "XIVE: END %x/%x invalid config: F1 & backlog\n",
671 end_blk, end_idx);
672 return;
673 }
674
675
676
677
678
679
680 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2) |
681 xive_priority_to_ipb(priority);
682 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb);
683 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
684
685
686
687
688 }
689
690do_escalation:
691
692
693
694
695 if (!xive2_end_is_escalate(&end)) {
696 return;
697 }
698
699
700
701
702
703 if (!xive2_end_is_uncond_escalation(&end)) {
704
705 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx,
706 &end, END2_W1_ESe)) {
707 return;
708 }
709 }
710
711
712
713
714 xive2_router_end_notify(xrtr,
715 xive_get_field32(END2_W4_END_BLOCK, end.w4),
716 xive_get_field32(END2_W4_ESC_END_INDEX, end.w4),
717 xive_get_field32(END2_W5_ESC_END_DATA, end.w5));
718}
719
720void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked)
721{
722 Xive2Router *xrtr = XIVE2_ROUTER(xn);
723 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn);
724 uint32_t eas_idx = XIVE_EAS_INDEX(lisn);
725 Xive2Eas eas;
726
727
728 if (xive2_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) {
729 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn);
730 return;
731 }
732
733 if (!pq_checked) {
734 bool notify;
735 uint8_t pq;
736
737
738 if (xive2_router_get_pq(xrtr, eas_blk, eas_idx, &pq)) {
739
740 g_assert_not_reached();
741 }
742
743 notify = xive_esb_trigger(&pq);
744
745 if (xive2_router_set_pq(xrtr, eas_blk, eas_idx, &pq)) {
746
747 g_assert_not_reached();
748 }
749
750 if (!notify) {
751 return;
752 }
753 }
754
755 if (!xive2_eas_is_valid(&eas)) {
756 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %x\n", lisn);
757 return;
758 }
759
760 if (xive2_eas_is_masked(&eas)) {
761
762 return;
763 }
764
765
766
767
768 xive2_router_end_notify(xrtr,
769 xive_get_field64(EAS2_END_BLOCK, eas.w),
770 xive_get_field64(EAS2_END_INDEX, eas.w),
771 xive_get_field64(EAS2_END_DATA, eas.w));
772}
773
774static Property xive2_router_properties[] = {
775 DEFINE_PROP_LINK("xive-fabric", Xive2Router, xfb,
776 TYPE_XIVE_FABRIC, XiveFabric *),
777 DEFINE_PROP_END_OF_LIST(),
778};
779
780static void xive2_router_class_init(ObjectClass *klass, void *data)
781{
782 DeviceClass *dc = DEVICE_CLASS(klass);
783 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass);
784
785 dc->desc = "XIVE2 Router Engine";
786 device_class_set_props(dc, xive2_router_properties);
787
788 dc->realize = xive2_router_realize;
789 xnc->notify = xive2_router_notify;
790}
791
792static const TypeInfo xive2_router_info = {
793 .name = TYPE_XIVE2_ROUTER,
794 .parent = TYPE_SYS_BUS_DEVICE,
795 .abstract = true,
796 .instance_size = sizeof(Xive2Router),
797 .class_size = sizeof(Xive2RouterClass),
798 .class_init = xive2_router_class_init,
799 .interfaces = (InterfaceInfo[]) {
800 { TYPE_XIVE_NOTIFIER },
801 { TYPE_XIVE_PRESENTER },
802 { }
803 }
804};
805
806static inline bool addr_is_even(hwaddr addr, uint32_t shift)
807{
808 return !((addr >> shift) & 1);
809}
810
811static uint64_t xive2_end_source_read(void *opaque, hwaddr addr, unsigned size)
812{
813 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque);
814 uint32_t offset = addr & 0xFFF;
815 uint8_t end_blk;
816 uint32_t end_idx;
817 Xive2End end;
818 uint32_t end_esmask;
819 uint8_t pq;
820 uint64_t ret;
821
822
823
824
825
826 end_blk = xive2_router_get_block_id(xsrc->xrtr);
827 end_idx = addr >> (xsrc->esb_shift + 1);
828
829 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) {
830 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk,
831 end_idx);
832 return -1;
833 }
834
835 if (!xive2_end_is_valid(&end)) {
836 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n",
837 end_blk, end_idx);
838 return -1;
839 }
840
841 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn :
842 END2_W1_ESe;
843 pq = xive_get_field32(end_esmask, end.w1);
844
845 switch (offset) {
846 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF:
847 ret = xive_esb_eoi(&pq);
848
849
850 break;
851
852 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF:
853 ret = pq;
854 break;
855
856 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF:
857 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF:
858 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF:
859 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF:
860 ret = xive_esb_set(&pq, (offset >> 8) & 0x3);
861 break;
862 default:
863 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n",
864 offset);
865 return -1;
866 }
867
868 if (pq != xive_get_field32(end_esmask, end.w1)) {
869 end.w1 = xive_set_field32(end_esmask, end.w1, pq);
870 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1);
871 }
872
873 return ret;
874}
875
876static void xive2_end_source_write(void *opaque, hwaddr addr,
877 uint64_t value, unsigned size)
878{
879 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque);
880 uint32_t offset = addr & 0xFFF;
881 uint8_t end_blk;
882 uint32_t end_idx;
883 Xive2End end;
884 uint32_t end_esmask;
885 uint8_t pq;
886 bool notify = false;
887
888
889
890
891
892 end_blk = xive2_router_get_block_id(xsrc->xrtr);
893 end_idx = addr >> (xsrc->esb_shift + 1);
894
895 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) {
896 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk,
897 end_idx);
898 return;
899 }
900
901 if (!xive2_end_is_valid(&end)) {
902 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n",
903 end_blk, end_idx);
904 return;
905 }
906
907 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn :
908 END2_W1_ESe;
909 pq = xive_get_field32(end_esmask, end.w1);
910
911 switch (offset) {
912 case 0 ... 0x3FF:
913 notify = xive_esb_trigger(&pq);
914 break;
915
916 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF:
917
918 notify = xive_esb_eoi(&pq);
919 break;
920
921 case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF:
922 if (end_esmask == END2_W1_ESe) {
923 qemu_log_mask(LOG_GUEST_ERROR,
924 "XIVE: END %x/%x can not EQ inject on ESe\n",
925 end_blk, end_idx);
926 return;
927 }
928 notify = true;
929 break;
930
931 default:
932 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB write addr %d\n",
933 offset);
934 return;
935 }
936
937 if (pq != xive_get_field32(end_esmask, end.w1)) {
938 end.w1 = xive_set_field32(end_esmask, end.w1, pq);
939 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1);
940 }
941
942
943 if (notify) {
944 ;
945 }
946}
947
948static const MemoryRegionOps xive2_end_source_ops = {
949 .read = xive2_end_source_read,
950 .write = xive2_end_source_write,
951 .endianness = DEVICE_BIG_ENDIAN,
952 .valid = {
953 .min_access_size = 8,
954 .max_access_size = 8,
955 },
956 .impl = {
957 .min_access_size = 8,
958 .max_access_size = 8,
959 },
960};
961
962static void xive2_end_source_realize(DeviceState *dev, Error **errp)
963{
964 Xive2EndSource *xsrc = XIVE2_END_SOURCE(dev);
965
966 assert(xsrc->xrtr);
967
968 if (!xsrc->nr_ends) {
969 error_setg(errp, "Number of interrupt needs to be greater than 0");
970 return;
971 }
972
973 if (xsrc->esb_shift != XIVE_ESB_4K &&
974 xsrc->esb_shift != XIVE_ESB_64K) {
975 error_setg(errp, "Invalid ESB shift setting");
976 return;
977 }
978
979
980
981
982
983 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc),
984 &xive2_end_source_ops, xsrc, "xive.end",
985 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends);
986}
987
988static Property xive2_end_source_properties[] = {
989 DEFINE_PROP_UINT32("nr-ends", Xive2EndSource, nr_ends, 0),
990 DEFINE_PROP_UINT32("shift", Xive2EndSource, esb_shift, XIVE_ESB_64K),
991 DEFINE_PROP_LINK("xive", Xive2EndSource, xrtr, TYPE_XIVE2_ROUTER,
992 Xive2Router *),
993 DEFINE_PROP_END_OF_LIST(),
994};
995
996static void xive2_end_source_class_init(ObjectClass *klass, void *data)
997{
998 DeviceClass *dc = DEVICE_CLASS(klass);
999
1000 dc->desc = "XIVE END Source";
1001 device_class_set_props(dc, xive2_end_source_properties);
1002 dc->realize = xive2_end_source_realize;
1003 dc->user_creatable = false;
1004}
1005
1006static const TypeInfo xive2_end_source_info = {
1007 .name = TYPE_XIVE2_END_SOURCE,
1008 .parent = TYPE_DEVICE,
1009 .instance_size = sizeof(Xive2EndSource),
1010 .class_init = xive2_end_source_class_init,
1011};
1012
1013static void xive2_register_types(void)
1014{
1015 type_register_static(&xive2_router_info);
1016 type_register_static(&xive2_end_source_info);
1017}
1018
1019type_init(xive2_register_types)
1020