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31#include "qemu/osdep.h"
32#include "qemu/cutils.h"
33#include "qemu/error-report.h"
34#include "qapi/error.h"
35#include "hw/boards.h"
36#include "hw/loader.h"
37#include "hw/sysbus.h"
38#include "hw/char/serial.h"
39#include "hw/misc/unimp.h"
40#include "target/riscv/cpu.h"
41#include "hw/riscv/riscv_hart.h"
42#include "hw/riscv/sifive_e.h"
43#include "hw/riscv/boot.h"
44#include "hw/char/sifive_uart.h"
45#include "hw/intc/riscv_aclint.h"
46#include "hw/intc/sifive_plic.h"
47#include "hw/misc/sifive_e_prci.h"
48#include "chardev/char.h"
49#include "sysemu/sysemu.h"
50
51static const MemMapEntry sifive_e_memmap[] = {
52 [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 },
53 [SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 },
54 [SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 },
55 [SIFIVE_E_DEV_CLINT] = { 0x2000000, 0x10000 },
56 [SIFIVE_E_DEV_PLIC] = { 0xc000000, 0x4000000 },
57 [SIFIVE_E_DEV_AON] = { 0x10000000, 0x8000 },
58 [SIFIVE_E_DEV_PRCI] = { 0x10008000, 0x8000 },
59 [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000, 0x1000 },
60 [SIFIVE_E_DEV_GPIO0] = { 0x10012000, 0x1000 },
61 [SIFIVE_E_DEV_UART0] = { 0x10013000, 0x1000 },
62 [SIFIVE_E_DEV_QSPI0] = { 0x10014000, 0x1000 },
63 [SIFIVE_E_DEV_PWM0] = { 0x10015000, 0x1000 },
64 [SIFIVE_E_DEV_UART1] = { 0x10023000, 0x1000 },
65 [SIFIVE_E_DEV_QSPI1] = { 0x10024000, 0x1000 },
66 [SIFIVE_E_DEV_PWM1] = { 0x10025000, 0x1000 },
67 [SIFIVE_E_DEV_QSPI2] = { 0x10034000, 0x1000 },
68 [SIFIVE_E_DEV_PWM2] = { 0x10035000, 0x1000 },
69 [SIFIVE_E_DEV_XIP] = { 0x20000000, 0x20000000 },
70 [SIFIVE_E_DEV_DTIM] = { 0x80000000, 0x4000 }
71};
72
73static void sifive_e_machine_init(MachineState *machine)
74{
75 MachineClass *mc = MACHINE_GET_CLASS(machine);
76 const MemMapEntry *memmap = sifive_e_memmap;
77
78 SiFiveEState *s = RISCV_E_MACHINE(machine);
79 MemoryRegion *sys_mem = get_system_memory();
80 int i;
81
82 if (machine->ram_size != mc->default_ram_size) {
83 char *sz = size_to_str(mc->default_ram_size);
84 error_report("Invalid RAM size, should be %s", sz);
85 g_free(sz);
86 exit(EXIT_FAILURE);
87 }
88
89
90 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);
91 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
92
93
94 memory_region_add_subregion(sys_mem,
95 memmap[SIFIVE_E_DEV_DTIM].base, machine->ram);
96
97
98 uint32_t reset_vec[4];
99
100 if (s->revb) {
101 reset_vec[1] = 0x200102b7;
102 } else {
103 reset_vec[1] = 0x204002b7;
104 }
105 reset_vec[2] = 0x00028067;
106
107 reset_vec[0] = reset_vec[3] = 0;
108
109
110 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
111 reset_vec[i] = cpu_to_le32(reset_vec[i]);
112 }
113 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
114 memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
115
116 if (machine->kernel_filename) {
117 riscv_load_kernel(machine->kernel_filename,
118 memmap[SIFIVE_E_DEV_DTIM].base, NULL);
119 }
120}
121
122static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
123{
124 SiFiveEState *s = RISCV_E_MACHINE(obj);
125
126 return s->revb;
127}
128
129static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
130{
131 SiFiveEState *s = RISCV_E_MACHINE(obj);
132
133 s->revb = value;
134}
135
136static void sifive_e_machine_instance_init(Object *obj)
137{
138 SiFiveEState *s = RISCV_E_MACHINE(obj);
139
140 s->revb = false;
141}
142
143static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
144{
145 MachineClass *mc = MACHINE_CLASS(oc);
146
147 mc->desc = "RISC-V Board compatible with SiFive E SDK";
148 mc->init = sifive_e_machine_init;
149 mc->max_cpus = 1;
150 mc->default_cpu_type = SIFIVE_E_CPU;
151 mc->default_ram_id = "riscv.sifive.e.ram";
152 mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size;
153
154 object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb,
155 sifive_e_machine_set_revb);
156 object_class_property_set_description(oc, "revb",
157 "Set on to tell QEMU that it should model "
158 "the revB HiFive1 board");
159}
160
161static const TypeInfo sifive_e_machine_typeinfo = {
162 .name = MACHINE_TYPE_NAME("sifive_e"),
163 .parent = TYPE_MACHINE,
164 .class_init = sifive_e_machine_class_init,
165 .instance_init = sifive_e_machine_instance_init,
166 .instance_size = sizeof(SiFiveEState),
167};
168
169static void sifive_e_machine_init_register_types(void)
170{
171 type_register_static(&sifive_e_machine_typeinfo);
172}
173
174type_init(sifive_e_machine_init_register_types)
175
176static void sifive_e_soc_init(Object *obj)
177{
178 MachineState *ms = MACHINE(qdev_get_machine());
179 SiFiveESoCState *s = RISCV_E_SOC(obj);
180
181 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
182 object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
183 &error_abort);
184 object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort);
185 object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
186 TYPE_SIFIVE_GPIO);
187}
188
189static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
190{
191 MachineState *ms = MACHINE(qdev_get_machine());
192 const MemMapEntry *memmap = sifive_e_memmap;
193 SiFiveESoCState *s = RISCV_E_SOC(dev);
194 MemoryRegion *sys_mem = get_system_memory();
195
196 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
197 &error_abort);
198 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
199
200
201 memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
202 memmap[SIFIVE_E_DEV_MROM].size, &error_fatal);
203 memory_region_add_subregion(sys_mem,
204 memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom);
205
206
207 s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base,
208 (char *)SIFIVE_E_PLIC_HART_CONFIG, ms->smp.cpus, 0,
209 SIFIVE_E_PLIC_NUM_SOURCES,
210 SIFIVE_E_PLIC_NUM_PRIORITIES,
211 SIFIVE_E_PLIC_PRIORITY_BASE,
212 SIFIVE_E_PLIC_PENDING_BASE,
213 SIFIVE_E_PLIC_ENABLE_BASE,
214 SIFIVE_E_PLIC_ENABLE_STRIDE,
215 SIFIVE_E_PLIC_CONTEXT_BASE,
216 SIFIVE_E_PLIC_CONTEXT_STRIDE,
217 memmap[SIFIVE_E_DEV_PLIC].size);
218 riscv_aclint_swi_create(memmap[SIFIVE_E_DEV_CLINT].base,
219 0, ms->smp.cpus, false);
220 riscv_aclint_mtimer_create(memmap[SIFIVE_E_DEV_CLINT].base +
221 RISCV_ACLINT_SWI_SIZE,
222 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
223 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
224 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false);
225 create_unimplemented_device("riscv.sifive.e.aon",
226 memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size);
227 sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base);
228
229
230
231 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
232 return;
233 }
234
235
236 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0].base);
237
238
239 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
240
241
242 for (int i = 0; i < 32; i++) {
243 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
244 qdev_get_gpio_in(DEVICE(s->plic),
245 SIFIVE_E_GPIO0_IRQ0 + i));
246 }
247
248 sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base,
249 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
250 create_unimplemented_device("riscv.sifive.e.qspi0",
251 memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size);
252 create_unimplemented_device("riscv.sifive.e.pwm0",
253 memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size);
254 sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base,
255 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));
256 create_unimplemented_device("riscv.sifive.e.qspi1",
257 memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size);
258 create_unimplemented_device("riscv.sifive.e.pwm1",
259 memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size);
260 create_unimplemented_device("riscv.sifive.e.qspi2",
261 memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size);
262 create_unimplemented_device("riscv.sifive.e.pwm2",
263 memmap[SIFIVE_E_DEV_PWM2].base, memmap[SIFIVE_E_DEV_PWM2].size);
264
265
266 memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip",
267 memmap[SIFIVE_E_DEV_XIP].size, &error_fatal);
268 memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_DEV_XIP].base,
269 &s->xip_mem);
270}
271
272static void sifive_e_soc_class_init(ObjectClass *oc, void *data)
273{
274 DeviceClass *dc = DEVICE_CLASS(oc);
275
276 dc->realize = sifive_e_soc_realize;
277
278 dc->user_creatable = false;
279}
280
281static const TypeInfo sifive_e_soc_type_info = {
282 .name = TYPE_RISCV_E_SOC,
283 .parent = TYPE_DEVICE,
284 .instance_size = sizeof(SiFiveESoCState),
285 .instance_init = sifive_e_soc_init,
286 .class_init = sifive_e_soc_class_init,
287};
288
289static void sifive_e_soc_register_types(void)
290{
291 type_register_static(&sifive_e_soc_type_info);
292}
293
294type_init(sifive_e_soc_register_types)
295
