1/* 2 * Model of the Xilinx Versal 3 * 4 * Copyright (c) 2018 Xilinx Inc. 5 * Written by Edgar E. Iglesias 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12#ifndef XLNX_VERSAL_H 13#define XLNX_VERSAL_H 14 15#include "hw/sysbus.h" 16#include "hw/arm/boot.h" 17#include "hw/or-irq.h" 18#include "hw/sd/sdhci.h" 19#include "hw/intc/arm_gicv3.h" 20#include "hw/char/pl011.h" 21#include "hw/dma/xlnx-zdma.h" 22#include "hw/net/cadence_gem.h" 23#include "hw/rtc/xlnx-zynqmp-rtc.h" 24#include "qom/object.h" 25#include "hw/usb/xlnx-usb-subsystem.h" 26#include "hw/misc/xlnx-versal-xramc.h" 27#include "hw/nvram/xlnx-bbram.h" 28#include "hw/nvram/xlnx-versal-efuse.h" 29#include "hw/ssi/xlnx-versal-ospi.h" 30#include "hw/dma/xlnx_csu_dma.h" 31#include "hw/misc/xlnx-versal-pmc-iou-slcr.h" 32 33#define TYPE_XLNX_VERSAL "xlnx-versal" 34OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) 35 36#define XLNX_VERSAL_NR_ACPUS 2 37#define XLNX_VERSAL_NR_UARTS 2 38#define XLNX_VERSAL_NR_GEMS 2 39#define XLNX_VERSAL_NR_ADMAS 8 40#define XLNX_VERSAL_NR_SDS 2 41#define XLNX_VERSAL_NR_XRAM 4 42#define XLNX_VERSAL_NR_IRQS 192 43 44struct Versal { 45 /*< private >*/ 46 SysBusDevice parent_obj; 47 48 /*< public >*/ 49 struct { 50 struct { 51 MemoryRegion mr; 52 ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; 53 GICv3State gic; 54 } apu; 55 } fpd; 56 57 MemoryRegion mr_ps; 58 59 struct { 60 /* 4 ranges to access DDR. */ 61 MemoryRegion mr_ddr_ranges[4]; 62 } noc; 63 64 struct { 65 MemoryRegion mr_ocm; 66 67 struct { 68 PL011State uart[XLNX_VERSAL_NR_UARTS]; 69 CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; 70 XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; 71 VersalUsb2 usb; 72 } iou; 73 74 struct { 75 qemu_or_irq irq_orgate; 76 XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; 77 } xram; 78 } lpd; 79 80 /* The Platform Management Controller subsystem. */ 81 struct { 82 struct { 83 SDHCIState sd[XLNX_VERSAL_NR_SDS]; 84 XlnxVersalPmcIouSlcr slcr; 85 86 struct { 87 XlnxVersalOspi ospi; 88 XlnxCSUDMA dma_src; 89 XlnxCSUDMA dma_dst; 90 MemoryRegion linear_mr; 91 qemu_or_irq irq_orgate; 92 } ospi; 93 } iou; 94 95 XlnxZynqMPRTC rtc; 96 XlnxBBRam bbram; 97 XlnxEFuse efuse; 98 XlnxVersalEFuseCtrl efuse_ctrl; 99 XlnxVersalEFuseCache efuse_cache; 100 101 qemu_or_irq apb_irq_orgate; 102 } pmc; 103 104 struct { 105 MemoryRegion *mr_ddr; 106 } cfg; 107}; 108 109/* Memory-map and IRQ definitions. Copied a subset from 110 * auto-generated files. */ 111 112#define VERSAL_GIC_MAINT_IRQ 9 113#define VERSAL_TIMER_VIRT_IRQ 11 114#define VERSAL_TIMER_S_EL1_IRQ 13 115#define VERSAL_TIMER_NS_EL1_IRQ 14 116#define VERSAL_TIMER_NS_EL2_IRQ 10 117 118#define VERSAL_UART0_IRQ_0 18 119#define VERSAL_UART1_IRQ_0 19 120#define VERSAL_USB0_IRQ_0 22 121#define VERSAL_GEM0_IRQ_0 56 122#define VERSAL_GEM0_WAKE_IRQ_0 57 123#define VERSAL_GEM1_IRQ_0 58 124#define VERSAL_GEM1_WAKE_IRQ_0 59 125#define VERSAL_ADMA_IRQ_0 60 126#define VERSAL_XRAM_IRQ_0 79 127#define VERSAL_PMC_APB_IRQ 121 128#define VERSAL_OSPI_IRQ 124 129#define VERSAL_SD0_IRQ_0 126 130#define VERSAL_EFUSE_IRQ 139 131#define VERSAL_RTC_ALARM_IRQ 142 132#define VERSAL_RTC_SECONDS_IRQ 143 133 134/* Architecturally reserved IRQs suitable for virtualization. */ 135#define VERSAL_RSVD_IRQ_FIRST 111 136#define VERSAL_RSVD_IRQ_LAST 118 137 138#define MM_TOP_RSVD 0xa0000000U 139#define MM_TOP_RSVD_SIZE 0x4000000 140#define MM_GIC_APU_DIST_MAIN 0xf9000000U 141#define MM_GIC_APU_DIST_MAIN_SIZE 0x10000 142#define MM_GIC_APU_REDIST_0 0xf9080000U 143#define MM_GIC_APU_REDIST_0_SIZE 0x80000 144 145#define MM_UART0 0xff000000U 146#define MM_UART0_SIZE 0x10000 147#define MM_UART1 0xff010000U 148#define MM_UART1_SIZE 0x10000 149 150#define MM_GEM0 0xff0c0000U 151#define MM_GEM0_SIZE 0x10000 152#define MM_GEM1 0xff0d0000U 153#define MM_GEM1_SIZE 0x10000 154 155#define MM_ADMA_CH0 0xffa80000U 156#define MM_ADMA_CH0_SIZE 0x10000 157 158#define MM_OCM 0xfffc0000U 159#define MM_OCM_SIZE 0x40000 160 161#define MM_XRAM 0xfe800000 162#define MM_XRAMC 0xff8e0000 163#define MM_XRAMC_SIZE 0x10000 164 165#define MM_USB2_CTRL_REGS 0xFF9D0000 166#define MM_USB2_CTRL_REGS_SIZE 0x10000 167 168#define MM_USB_0 0xFE200000 169#define MM_USB_0_SIZE 0x10000 170 171#define MM_TOP_DDR 0x0 172#define MM_TOP_DDR_SIZE 0x80000000U 173#define MM_TOP_DDR_2 0x800000000ULL 174#define MM_TOP_DDR_2_SIZE 0x800000000ULL 175#define MM_TOP_DDR_3 0xc000000000ULL 176#define MM_TOP_DDR_3_SIZE 0x4000000000ULL 177#define MM_TOP_DDR_4 0x10000000000ULL 178#define MM_TOP_DDR_4_SIZE 0xb780000000ULL 179 180#define MM_PSM_START 0xffc80000U 181#define MM_PSM_END 0xffcf0000U 182 183#define MM_CRL 0xff5e0000U 184#define MM_CRL_SIZE 0x300000 185#define MM_IOU_SCNTR 0xff130000U 186#define MM_IOU_SCNTR_SIZE 0x10000 187#define MM_IOU_SCNTRS 0xff140000U 188#define MM_IOU_SCNTRS_SIZE 0x10000 189#define MM_FPD_CRF 0xfd1a0000U 190#define MM_FPD_CRF_SIZE 0x140000 191#define MM_FPD_FPD_APU 0xfd5c0000 192#define MM_FPD_FPD_APU_SIZE 0x100 193 194#define MM_PMC_PMC_IOU_SLCR 0xf1060000 195#define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000 196 197#define MM_PMC_OSPI 0xf1010000 198#define MM_PMC_OSPI_SIZE 0x10000 199 200#define MM_PMC_OSPI_DAC 0xc0000000 201#define MM_PMC_OSPI_DAC_SIZE 0x20000000 202 203#define MM_PMC_OSPI_DMA_DST 0xf1011800 204#define MM_PMC_OSPI_DMA_SRC 0xf1011000 205 206#define MM_PMC_SD0 0xf1040000U 207#define MM_PMC_SD0_SIZE 0x10000 208#define MM_PMC_BBRAM_CTRL 0xf11f0000 209#define MM_PMC_BBRAM_CTRL_SIZE 0x00050 210#define MM_PMC_EFUSE_CTRL 0xf1240000 211#define MM_PMC_EFUSE_CTRL_SIZE 0x00104 212#define MM_PMC_EFUSE_CACHE 0xf1250000 213#define MM_PMC_EFUSE_CACHE_SIZE 0x00C00 214 215#define MM_PMC_CRP 0xf1260000U 216#define MM_PMC_CRP_SIZE 0x10000 217#define MM_PMC_RTC 0xf12a0000 218#define MM_PMC_RTC_SIZE 0x10000 219#endif 220