LXR qemu/include/hw/i2c/npcm7xx

   1/*
   2 * Nuvoton NPCM7xx SMBus Module.
   3 *
   4 * Copyright 2020 Google LLC
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms of the GNU General Public License as published by the
   8 * Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful, but WITHOUT
  12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  14 * for more details.
  15 */
  16#ifndef NPCM7XX_SMBUS_H
  17#define NPCM7XX_SMBUS_H
  18
  19#include "exec/memory.h"
  20#include "hw/i2c/i2c.h"
  21#include "hw/irq.h"
  22#include "hw/sysbus.h"
  23
  24/*
  25 * Number of addresses this module contains. Do not change this without
  26 * incrementing the version_id in the vmstate.
  27 */
  28#define NPCM7XX_SMBUS_NR_ADDRS 10
  29
  30/* Size of the FIFO buffer. */
  31#define NPCM7XX_SMBUS_FIFO_SIZE 16
  32
  33typedef enum NPCM7xxSMBusStatus {
  34    NPCM7XX_SMBUS_STATUS_IDLE,
  35    NPCM7XX_SMBUS_STATUS_SENDING,
  36    NPCM7XX_SMBUS_STATUS_RECEIVING,
  37    NPCM7XX_SMBUS_STATUS_NEGACK,
  38    NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE,
  39    NPCM7XX_SMBUS_STATUS_STOPPING_NEGACK,
  40} NPCM7xxSMBusStatus;
  41
  42/*
  43 * struct NPCM7xxSMBusState - System Management Bus device state.
  44 * @bus: The underlying I2C Bus.
  45 * @irq: GIC interrupt line to fire on events (if enabled).
  46 * @sda: The serial data register.
  47 * @st: The status register.
  48 * @cst: The control status register.
  49 * @cst2: The control status register 2.
  50 * @cst3: The control status register 3.
  51 * @ctl1: The control register 1.
  52 * @ctl2: The control register 2.
  53 * @ctl3: The control register 3.
  54 * @ctl4: The control register 4.
  55 * @ctl5: The control register 5.
  56 * @addr: The SMBus module's own addresses on the I2C bus.
  57 * @scllt: The SCL low time register.
  58 * @sclht: The SCL high time register.
  59 * @fif_ctl: The FIFO control register.
  60 * @fif_cts: The FIFO control status register.
  61 * @fair_per: The fair preriod register.
  62 * @txf_ctl: The transmit FIFO control register.
  63 * @t_out: The SMBus timeout register.
  64 * @txf_sts: The transmit FIFO status register.
  65 * @rxf_sts: The receive FIFO status register.
  66 * @rxf_ctl: The receive FIFO control register.
  67 * @rx_fifo: The FIFO buffer for receiving in FIFO mode.
  68 * @rx_cur: The current position of rx_fifo.
  69 * @status: The current status of the SMBus.
  70 */
  71typedef struct NPCM7xxSMBusState {
  72    SysBusDevice parent;
  73
  74    MemoryRegion iomem;
  75
  76    I2CBus      *bus;
  77    qemu_irq     irq;
  78
  79    uint8_t      sda;
  80    uint8_t      st;
  81    uint8_t      cst;
  82    uint8_t      cst2;
  83    uint8_t      cst3;
  84    uint8_t      ctl1;
  85    uint8_t      ctl2;
  86    uint8_t      ctl3;
  87    uint8_t      ctl4;
  88    uint8_t      ctl5;
  89    uint8_t      addr[NPCM7XX_SMBUS_NR_ADDRS];
  90
  91    uint8_t      scllt;
  92    uint8_t      sclht;
  93
  94    uint8_t      fif_ctl;
  95    uint8_t      fif_cts;
  96    uint8_t      fair_per;
  97    uint8_t      txf_ctl;
  98    uint8_t      t_out;
  99    uint8_t      txf_sts;
 100    uint8_t      rxf_sts;
 101    uint8_t      rxf_ctl;
 102
 103    uint8_t      rx_fifo[NPCM7XX_SMBUS_FIFO_SIZE];
 104    uint8_t      rx_cur;
 105
 106    NPCM7xxSMBusStatus status;
 107} NPCM7xxSMBusState;
 108
 109#define TYPE_NPCM7XX_SMBUS "npcm7xx-smbus"
 110#define NPCM7XX_SMBUS(obj) OBJECT_CHECK(NPCM7xxSMBusState, (obj), \
 111                                        TYPE_NPCM7XX_SMBUS)
 112
 113#endif /* NPCM7XX_SMBUS_H */
 114