LXR qemu/include/hw/intc/ppc-uic.h

   1/*
   2 * "Universal" Interrupt Controller for PowerPPC 4xx embedded processors
   3 *
   4 * Copyright (c) 2007 Jocelyn Mayer
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#ifndef HW_INTC_PPC_UIC_H
  26#define HW_INTC_PPC_UIC_H
  27
  28#include "hw/sysbus.h"
  29#include "qom/object.h"
  30
  31#define TYPE_PPC_UIC "ppc-uic"
  32OBJECT_DECLARE_SIMPLE_TYPE(PPCUIC, PPC_UIC)
  33
  34/*
  35 * QEMU interface:
  36 * QOM property "cpu": link to the PPC CPU
  37 *    (no default, must be set)
  38 * QOM property "dcr-base": base of the bank of DCR registers for the UIC
  39 *    (default 0x30)
  40 * QOM property "use-vectors": true if the UIC has vector registers
  41 *    (default true)
  42 * unnamed GPIO inputs 0..UIC_MAX_IRQ: input IRQ lines
  43 * sysbus IRQs:
  44 *  0 (PPCUIC_OUTPUT_INT): output INT line to the CPU
  45 *  1 (PPCUIC_OUTPUT_CINT): output CINT line to the CPU
  46 */
  47
  48#define UIC_MAX_IRQ 32
  49
  50/* Symbolic constants for the sysbus IRQ outputs */
  51enum {
  52    PPCUIC_OUTPUT_INT = 0,
  53    PPCUIC_OUTPUT_CINT = 1,
  54    PPCUIC_OUTPUT_NB,
  55};
  56
  57struct PPCUIC {
  58    /*< private >*/
  59    SysBusDevice parent_obj;
  60
  61    /*< public >*/
  62    qemu_irq output_int;
  63    qemu_irq output_cint;
  64
  65    /* properties */
  66    CPUState *cpu;
  67    uint32_t dcr_base;
  68    bool use_vectors;
  69
  70    uint32_t level;  /* Remembers the state of level-triggered interrupts. */
  71    uint32_t uicsr;  /* Status register */
  72    uint32_t uicer;  /* Enable register */
  73    uint32_t uiccr;  /* Critical register */
  74    uint32_t uicpr;  /* Polarity register */
  75    uint32_t uictr;  /* Triggering register */
  76    uint32_t uicvcr; /* Vector configuration register */
  77    uint32_t uicvr;
  78};
  79
  80#endif
  81