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19#ifndef HW_SIFIVE_E_PRCI_H
20#define HW_SIFIVE_E_PRCI_H
21#include "qom/object.h"
22
23enum {
24 SIFIVE_E_PRCI_HFROSCCFG = 0x0,
25 SIFIVE_E_PRCI_HFXOSCCFG = 0x4,
26 SIFIVE_E_PRCI_PLLCFG = 0x8,
27 SIFIVE_E_PRCI_PLLOUTDIV = 0xC
28};
29
30enum {
31 SIFIVE_E_PRCI_HFROSCCFG_RDY = (1 << 31),
32 SIFIVE_E_PRCI_HFROSCCFG_EN = (1 << 30)
33};
34
35enum {
36 SIFIVE_E_PRCI_HFXOSCCFG_RDY = (1 << 31),
37 SIFIVE_E_PRCI_HFXOSCCFG_EN = (1 << 30)
38};
39
40enum {
41 SIFIVE_E_PRCI_PLLCFG_PLLSEL = (1 << 16),
42 SIFIVE_E_PRCI_PLLCFG_REFSEL = (1 << 17),
43 SIFIVE_E_PRCI_PLLCFG_BYPASS = (1 << 18),
44 SIFIVE_E_PRCI_PLLCFG_LOCK = (1 << 31)
45};
46
47enum {
48 SIFIVE_E_PRCI_PLLOUTDIV_DIV1 = (1 << 8)
49};
50
51#define SIFIVE_E_PRCI_REG_SIZE 0x1000
52
53#define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci"
54
55typedef struct SiFiveEPRCIState SiFiveEPRCIState;
56DECLARE_INSTANCE_CHECKER(SiFiveEPRCIState, SIFIVE_E_PRCI,
57 TYPE_SIFIVE_E_PRCI)
58
59struct SiFiveEPRCIState {
60
61 SysBusDevice parent_obj;
62
63
64 MemoryRegion mmio;
65 uint32_t hfrosccfg;
66 uint32_t hfxosccfg;
67 uint32_t pllcfg;
68 uint32_t plloutdiv;
69};
70
71DeviceState *sifive_e_prci_create(hwaddr addr);
72
73#endif
74