1#ifndef HW_SPAPR_H
2#define HW_SPAPR_H
3
4#include "qemu/units.h"
5#include "sysemu/dma.h"
6#include "hw/boards.h"
7#include "hw/ppc/spapr_drc.h"
8#include "hw/mem/pc-dimm.h"
9#include "hw/ppc/spapr_ovec.h"
10#include "hw/ppc/spapr_irq.h"
11#include "qom/object.h"
12#include "hw/ppc/spapr_xive.h"
13#include "hw/ppc/xics.h"
14#include "hw/ppc/spapr_tpm_proxy.h"
15#include "hw/ppc/vof.h"
16
17struct SpaprVioBus;
18struct SpaprPhbState;
19struct SpaprNvram;
20
21typedef struct SpaprEventLogEntry SpaprEventLogEntry;
22typedef struct SpaprEventSource SpaprEventSource;
23typedef struct SpaprPendingHpt SpaprPendingHpt;
24
25#define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL
26#define SPAPR_ENTRY_POINT 0x100
27
28#define SPAPR_TIMEBASE_FREQ 512000000ULL
29
30#define TYPE_SPAPR_RTC "spapr-rtc"
31
32OBJECT_DECLARE_SIMPLE_TYPE(SpaprRtcState, SPAPR_RTC)
33
34struct SpaprRtcState {
35
36 DeviceState parent_obj;
37 int64_t ns_offset;
38};
39
40typedef struct SpaprDimmState SpaprDimmState;
41
42#define TYPE_SPAPR_MACHINE "spapr-machine"
43OBJECT_DECLARE_TYPE(SpaprMachineState, SpaprMachineClass, SPAPR_MACHINE)
44
45typedef enum {
46 SPAPR_RESIZE_HPT_DEFAULT = 0,
47 SPAPR_RESIZE_HPT_DISABLED,
48 SPAPR_RESIZE_HPT_ENABLED,
49 SPAPR_RESIZE_HPT_REQUIRED,
50} SpaprResizeHpt;
51
52
53
54
55
56
57#define SPAPR_CAP_HTM 0x00
58
59#define SPAPR_CAP_VSX 0x01
60
61#define SPAPR_CAP_DFP 0x02
62
63#define SPAPR_CAP_CFPC 0x03
64
65#define SPAPR_CAP_SBBC 0x04
66
67#define SPAPR_CAP_IBS 0x05
68
69#define SPAPR_CAP_HPT_MAXPAGESIZE 0x06
70
71#define SPAPR_CAP_NESTED_KVM_HV 0x07
72
73#define SPAPR_CAP_LARGE_DECREMENTER 0x08
74
75#define SPAPR_CAP_CCF_ASSIST 0x09
76
77#define SPAPR_CAP_FWNMI 0x0A
78
79#define SPAPR_CAP_RPT_INVALIDATE 0x0B
80
81#define SPAPR_CAP_NUM (SPAPR_CAP_RPT_INVALIDATE + 1)
82
83
84
85
86
87#define SPAPR_CAP_OFF 0x00
88#define SPAPR_CAP_ON 0x01
89
90
91
92
93#define SPAPR_CAP_BROKEN 0x00
94#define SPAPR_CAP_WORKAROUND 0x01
95#define SPAPR_CAP_FIXED 0x02
96
97#define SPAPR_CAP_FIXED_IBS 0x02
98#define SPAPR_CAP_FIXED_CCD 0x03
99#define SPAPR_CAP_FIXED_NA 0x10
100
101#define FDT_MAX_SIZE 0x200000
102
103
104#define NVGPU_MAX_NUM 6
105
106
107#define NUMA_NODES_MAX_NUM (MAX_NODES + NVGPU_MAX_NUM)
108
109
110
111
112
113
114
115
116
117
118#define FORM1_DIST_REF_POINTS 4
119#define FORM1_NUMA_ASSOC_SIZE (FORM1_DIST_REF_POINTS + 1)
120
121
122
123
124
125#define FORM2_DIST_REF_POINTS 1
126#define FORM2_NUMA_ASSOC_SIZE (FORM2_DIST_REF_POINTS + 1)
127
128typedef struct SpaprCapabilities SpaprCapabilities;
129struct SpaprCapabilities {
130 uint8_t caps[SPAPR_CAP_NUM];
131};
132
133
134
135
136struct SpaprMachineClass {
137
138 MachineClass parent_class;
139
140
141 bool dr_lmb_enabled;
142 bool dr_phb_enabled;
143 bool update_dt_enabled;
144 bool use_ohci_by_default;
145 bool pre_2_10_has_unused_icps;
146 bool legacy_irq_allocation;
147 uint32_t nr_xirqs;
148 bool broken_host_serial_model;
149 bool pre_4_1_migration;
150 bool linux_pci_probe;
151 bool smp_threads_vsmt;
152 hwaddr rma_limit;
153 bool pre_5_1_assoc_refpoints;
154 bool pre_5_2_numa_associativity;
155 bool pre_6_2_numa_affinity;
156
157 bool (*phb_placement)(SpaprMachineState *spapr, uint32_t index,
158 uint64_t *buid, hwaddr *pio,
159 hwaddr *mmio32, hwaddr *mmio64,
160 unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa,
161 hwaddr *nv2atsd, Error **errp);
162 SpaprResizeHpt resize_hpt_default;
163 SpaprCapabilities default_caps;
164 SpaprIrq *irq;
165};
166
167
168
169
170struct SpaprMachineState {
171
172 MachineState parent_obj;
173
174 struct SpaprVioBus *vio_bus;
175 QLIST_HEAD(, SpaprPhbState) phbs;
176 struct SpaprNvram *nvram;
177 SpaprRtcState rtc;
178
179 SpaprResizeHpt resize_hpt;
180 void *htab;
181 uint32_t htab_shift;
182 uint64_t patb_entry;
183 SpaprPendingHpt *pending_hpt;
184
185 hwaddr rma_size;
186 uint32_t fdt_size;
187 uint32_t fdt_initial_size;
188 void *fdt_blob;
189 long kernel_size;
190 bool kernel_le;
191 uint64_t kernel_addr;
192 uint32_t initrd_base;
193 long initrd_size;
194 Vof *vof;
195 uint64_t rtc_offset;
196 struct PPCTimebase tb;
197 bool has_graphics;
198 uint32_t vsmt;
199
200
201 uint64_t nested_ptcr;
202
203 Notifier epow_notifier;
204 QTAILQ_HEAD(, SpaprEventLogEntry) pending_events;
205 bool use_hotplug_event_source;
206 SpaprEventSource *event_sources;
207
208
209 bool cas_pre_isa3_guest;
210 SpaprOptionVector *ov5;
211 SpaprOptionVector *ov5_cas;
212 uint32_t max_compat_pvr;
213
214
215 int htab_save_index;
216 bool htab_first_pass;
217 int htab_fd;
218
219
220
221
222 QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs;
223
224
225
226
227
228
229 target_ulong fwnmi_system_reset_addr;
230 target_ulong fwnmi_machine_check_addr;
231
232
233
234
235
236
237
238 int fwnmi_machine_check_interlock;
239 QemuCond fwnmi_machine_check_interlock_cond;
240
241
242 char *boot_device;
243
244
245 char *kvm_type;
246 char *host_model;
247 char *host_serial;
248
249 int32_t irq_map_nr;
250 unsigned long *irq_map;
251 SpaprIrq *irq;
252 qemu_irq *qirqs;
253 SpaprInterruptController *active_intc;
254 ICSState *ics;
255 SpaprXive *xive;
256
257 bool cmd_line_caps[SPAPR_CAP_NUM];
258 SpaprCapabilities def, eff, mig;
259
260 unsigned gpu_numa_id;
261 SpaprTpmProxy *tpm_proxy;
262
263 uint32_t FORM1_assoc_array[NUMA_NODES_MAX_NUM][FORM1_NUMA_ASSOC_SIZE];
264 uint32_t FORM2_assoc_array[NUMA_NODES_MAX_NUM][FORM2_NUMA_ASSOC_SIZE];
265
266 Error *fwnmi_migration_blocker;
267};
268
269#define H_SUCCESS 0
270#define H_BUSY 1
271#define H_CLOSED 2
272#define H_NOT_AVAILABLE 3
273#define H_CONSTRAINED 4
274#define H_PARTIAL 5
275#define H_IN_PROGRESS 14
276#define H_PAGE_REGISTERED 15
277#define H_PARTIAL_STORE 16
278#define H_PENDING 17
279#define H_CONTINUE 18
280#define H_LONG_BUSY_START_RANGE 9900
281#define H_LONG_BUSY_ORDER_1_MSEC 9900
282
283#define H_LONG_BUSY_ORDER_10_MSEC 9901
284
285#define H_LONG_BUSY_ORDER_100_MSEC 9902
286
287#define H_LONG_BUSY_ORDER_1_SEC 9903
288
289#define H_LONG_BUSY_ORDER_10_SEC 9904
290
291#define H_LONG_BUSY_ORDER_100_SEC 9905
292
293#define H_LONG_BUSY_END_RANGE 9905
294#define H_HARDWARE -1
295#define H_FUNCTION -2
296#define H_PRIVILEGE -3
297#define H_PARAMETER -4
298#define H_BAD_MODE -5
299#define H_PTEG_FULL -6
300#define H_NOT_FOUND -7
301#define H_RESERVED_DABR -8
302#define H_NO_MEM -9
303#define H_AUTHORITY -10
304#define H_PERMISSION -11
305#define H_DROPPED -12
306#define H_SOURCE_PARM -13
307#define H_DEST_PARM -14
308#define H_REMOTE_PARM -15
309#define H_RESOURCE -16
310#define H_ADAPTER_PARM -17
311#define H_RH_PARM -18
312#define H_RCQ_PARM -19
313#define H_SCQ_PARM -20
314#define H_EQ_PARM -21
315#define H_RT_PARM -22
316#define H_ST_PARM -23
317#define H_SIGT_PARM -24
318#define H_TOKEN_PARM -25
319#define H_MLENGTH_PARM -27
320#define H_MEM_PARM -28
321#define H_MEM_ACCESS_PARM -29
322#define H_ATTR_PARM -30
323#define H_PORT_PARM -31
324#define H_MCG_PARM -32
325#define H_VL_PARM -33
326#define H_TSIZE_PARM -34
327#define H_TRACE_PARM -35
328
329#define H_MASK_PARM -37
330#define H_MCG_FULL -38
331#define H_ALIAS_EXIST -39
332#define H_P_COUNTER -40
333#define H_TABLE_FULL -41
334#define H_ALT_TABLE -42
335#define H_MR_CONDITION -43
336#define H_NOT_ENOUGH_RESOURCES -44
337#define H_R_STATE -45
338#define H_RESCINDEND -46
339#define H_P2 -55
340#define H_P3 -56
341#define H_P4 -57
342#define H_P5 -58
343#define H_P6 -59
344#define H_P7 -60
345#define H_P8 -61
346#define H_P9 -62
347#define H_UNSUPPORTED -67
348#define H_OVERLAP -68
349#define H_UNSUPPORTED_FLAG -256
350#define H_MULTI_THREADS_ACTIVE -9005
351
352
353
354
355
356
357
358
359
360
361#define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \
362 && (x <= H_LONG_BUSY_END_RANGE))
363
364
365#define H_LARGE_PAGE (1ULL<<(63-16))
366#define H_EXACT (1ULL<<(63-24))
367#define H_R_XLATE (1ULL<<(63-25))
368#define H_READ_4 (1ULL<<(63-26))
369#define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
370#define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30)))
371#define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
372#define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
373#define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
374#define H_AVPN (1ULL<<(63-32))
375#define H_ANDCOND (1ULL<<(63-33))
376#define H_ICACHE_INVALIDATE (1ULL<<(63-40))
377#define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41))
378#define H_ZERO_PAGE (1ULL<<(63-48))
379#define H_COPY_PAGE (1ULL<<(63-49))
380#define H_N (1ULL<<(63-61))
381#define H_PP1 (1ULL<<(63-62))
382#define H_PP2 (1ULL<<(63-63))
383
384
385#define H_SET_MODE_RESOURCE_SET_CIABR 1
386#define H_SET_MODE_RESOURCE_SET_DAWR0 2
387#define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3
388#define H_SET_MODE_RESOURCE_LE 4
389
390
391#define H_SET_MODE_ENDIAN_BIG 0
392#define H_SET_MODE_ENDIAN_LITTLE 1
393
394
395#define H_VASI_INVALID 0
396#define H_VASI_ENABLED 1
397#define H_VASI_ABORTED 2
398#define H_VASI_SUSPENDING 3
399#define H_VASI_SUSPENDED 4
400#define H_VASI_RESUMED 5
401#define H_VASI_COMPLETED 6
402
403
404#define H_DABRX_HYPERVISOR (1ULL<<(63-61))
405#define H_DABRX_KERNEL (1ULL<<(63-62))
406#define H_DABRX_USER (1ULL<<(63-63))
407
408
409#define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0)
410#define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1)
411#define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2)
412#define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3)
413#define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4)
414#define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5)
415#define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6)
416#define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7)
417#define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9)
418
419#define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0)
420#define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1)
421#define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2)
422#define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5)
423#define H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY PPC_BIT(7)
424#define H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS PPC_BIT(8)
425
426
427#define H_CB_ALIGNMENT 4096
428
429
430#define H_REMOVE 0x04
431#define H_ENTER 0x08
432#define H_READ 0x0c
433#define H_CLEAR_MOD 0x10
434#define H_CLEAR_REF 0x14
435#define H_PROTECT 0x18
436#define H_GET_TCE 0x1c
437#define H_PUT_TCE 0x20
438#define H_SET_SPRG0 0x24
439#define H_SET_DABR 0x28
440#define H_PAGE_INIT 0x2c
441#define H_SET_ASR 0x30
442#define H_ASR_ON 0x34
443#define H_ASR_OFF 0x38
444#define H_LOGICAL_CI_LOAD 0x3c
445#define H_LOGICAL_CI_STORE 0x40
446#define H_LOGICAL_CACHE_LOAD 0x44
447#define H_LOGICAL_CACHE_STORE 0x48
448#define H_LOGICAL_ICBI 0x4c
449#define H_LOGICAL_DCBF 0x50
450#define H_GET_TERM_CHAR 0x54
451#define H_PUT_TERM_CHAR 0x58
452#define H_REAL_TO_LOGICAL 0x5c
453#define H_HYPERVISOR_DATA 0x60
454#define H_EOI 0x64
455#define H_CPPR 0x68
456#define H_IPI 0x6c
457#define H_IPOLL 0x70
458#define H_XIRR 0x74
459#define H_PERFMON 0x7c
460#define H_MIGRATE_DMA 0x78
461#define H_REGISTER_VPA 0xDC
462#define H_CEDE 0xE0
463#define H_CONFER 0xE4
464#define H_PROD 0xE8
465#define H_GET_PPP 0xEC
466#define H_SET_PPP 0xF0
467#define H_PURR 0xF4
468#define H_PIC 0xF8
469#define H_REG_CRQ 0xFC
470#define H_FREE_CRQ 0x100
471#define H_VIO_SIGNAL 0x104
472#define H_SEND_CRQ 0x108
473#define H_COPY_RDMA 0x110
474#define H_REGISTER_LOGICAL_LAN 0x114
475#define H_FREE_LOGICAL_LAN 0x118
476#define H_ADD_LOGICAL_LAN_BUFFER 0x11C
477#define H_SEND_LOGICAL_LAN 0x120
478#define H_BULK_REMOVE 0x124
479#define H_MULTICAST_CTRL 0x130
480#define H_SET_XDABR 0x134
481#define H_STUFF_TCE 0x138
482#define H_PUT_TCE_INDIRECT 0x13C
483#define H_CHANGE_LOGICAL_LAN_MAC 0x14C
484#define H_VTERM_PARTNER_INFO 0x150
485#define H_REGISTER_VTERM 0x154
486#define H_FREE_VTERM 0x158
487#define H_RESET_EVENTS 0x15C
488#define H_ALLOC_RESOURCE 0x160
489#define H_FREE_RESOURCE 0x164
490#define H_MODIFY_QP 0x168
491#define H_QUERY_QP 0x16C
492#define H_REREGISTER_PMR 0x170
493#define H_REGISTER_SMR 0x174
494#define H_QUERY_MR 0x178
495#define H_QUERY_MW 0x17C
496#define H_QUERY_HCA 0x180
497#define H_QUERY_PORT 0x184
498#define H_MODIFY_PORT 0x188
499#define H_DEFINE_AQP1 0x18C
500#define H_GET_TRACE_BUFFER 0x190
501#define H_DEFINE_AQP0 0x194
502#define H_RESIZE_MR 0x198
503#define H_ATTACH_MCQP 0x19C
504#define H_DETACH_MCQP 0x1A0
505#define H_CREATE_RPT 0x1A4
506#define H_REMOVE_RPT 0x1A8
507#define H_REGISTER_RPAGES 0x1AC
508#define H_DISABLE_AND_GETC 0x1B0
509#define H_ERROR_DATA 0x1B4
510#define H_GET_HCA_INFO 0x1B8
511#define H_GET_PERF_COUNT 0x1BC
512#define H_MANAGE_TRACE 0x1C0
513#define H_GET_CPU_CHARACTERISTICS 0x1C8
514#define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
515#define H_QUERY_INT_STATE 0x1E4
516#define H_POLL_PENDING 0x1D8
517#define H_ILLAN_ATTRIBUTES 0x244
518#define H_MODIFY_HEA_QP 0x250
519#define H_QUERY_HEA_QP 0x254
520#define H_QUERY_HEA 0x258
521#define H_QUERY_HEA_PORT 0x25C
522#define H_MODIFY_HEA_PORT 0x260
523#define H_REG_BCMC 0x264
524#define H_DEREG_BCMC 0x268
525#define H_REGISTER_HEA_RPAGES 0x26C
526#define H_DISABLE_AND_GET_HEA 0x270
527#define H_GET_HEA_INFO 0x274
528#define H_ALLOC_HEA_RESOURCE 0x278
529#define H_ADD_CONN 0x284
530#define H_DEL_CONN 0x288
531#define H_JOIN 0x298
532#define H_VASI_STATE 0x2A4
533#define H_ENABLE_CRQ 0x2B0
534#define H_GET_EM_PARMS 0x2B8
535#define H_SET_MPP 0x2D0
536#define H_GET_MPP 0x2D4
537#define H_HOME_NODE_ASSOCIATIVITY 0x2EC
538#define H_XIRR_X 0x2FC
539#define H_RANDOM 0x300
540#define H_SET_MODE 0x31C
541#define H_RESIZE_HPT_PREPARE 0x36C
542#define H_RESIZE_HPT_COMMIT 0x370
543#define H_CLEAN_SLB 0x374
544#define H_INVALIDATE_PID 0x378
545#define H_REGISTER_PROC_TBL 0x37C
546#define H_SIGNAL_SYS_RESET 0x380
547
548#define H_INT_GET_SOURCE_INFO 0x3A8
549#define H_INT_SET_SOURCE_CONFIG 0x3AC
550#define H_INT_GET_SOURCE_CONFIG 0x3B0
551#define H_INT_GET_QUEUE_INFO 0x3B4
552#define H_INT_SET_QUEUE_CONFIG 0x3B8
553#define H_INT_GET_QUEUE_CONFIG 0x3BC
554#define H_INT_SET_OS_REPORTING_LINE 0x3C0
555#define H_INT_GET_OS_REPORTING_LINE 0x3C4
556#define H_INT_ESB 0x3C8
557#define H_INT_SYNC 0x3CC
558#define H_INT_RESET 0x3D0
559#define H_SCM_READ_METADATA 0x3E4
560#define H_SCM_WRITE_METADATA 0x3E8
561#define H_SCM_BIND_MEM 0x3EC
562#define H_SCM_UNBIND_MEM 0x3F0
563#define H_SCM_UNBIND_ALL 0x3FC
564#define H_SCM_HEALTH 0x400
565#define H_RPT_INVALIDATE 0x448
566#define H_SCM_FLUSH 0x44C
567
568#define MAX_HCALL_OPCODE H_SCM_FLUSH
569
570
571
572
573
574
575
576
577#define KVMPPC_HCALL_BASE 0xf000
578#define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
579#define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1)
580
581#define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2)
582#define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3)
583
584#define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5)
585
586
587#define KVMPPC_H_SET_PARTITION_TABLE (KVMPPC_HCALL_BASE + 0x800)
588#define KVMPPC_H_ENTER_NESTED (KVMPPC_HCALL_BASE + 0x804)
589#define KVMPPC_H_TLB_INVALIDATE (KVMPPC_HCALL_BASE + 0x808)
590#define KVMPPC_H_COPY_TOFROM_GUEST (KVMPPC_HCALL_BASE + 0x80C)
591
592#define KVMPPC_HCALL_MAX KVMPPC_H_COPY_TOFROM_GUEST
593
594
595
596
597
598#define SVM_HCALL_BASE 0xEF00
599#define SVM_H_TPM_COMM 0xEF10
600#define SVM_HCALL_MAX SVM_H_TPM_COMM
601
602
603
604
605
606struct kvmppc_hv_guest_state {
607 uint64_t version;
608 uint32_t lpid;
609 uint32_t vcpu_token;
610
611 uint64_t lpcr;
612 uint64_t pcr;
613 uint64_t amor;
614 uint64_t dpdes;
615 uint64_t hfscr;
616 int64_t tb_offset;
617 uint64_t dawr0;
618 uint64_t dawrx0;
619 uint64_t ciabr;
620 uint64_t hdec_expiry;
621 uint64_t purr;
622 uint64_t spurr;
623 uint64_t ic;
624 uint64_t vtb;
625 uint64_t hdar;
626 uint64_t hdsisr;
627 uint64_t heir;
628 uint64_t asdr;
629
630 uint64_t srr0;
631 uint64_t srr1;
632 uint64_t sprg[4];
633 uint64_t pidr;
634 uint64_t cfar;
635 uint64_t ppr;
636
637 uint64_t dawr1;
638 uint64_t dawrx1;
639
640};
641
642
643#define HV_GUEST_STATE_VERSION 2
644
645
646struct kvmppc_pt_regs {
647 uint64_t gpr[32];
648 uint64_t nip;
649 uint64_t msr;
650 uint64_t orig_gpr3;
651 uint64_t ctr;
652 uint64_t link;
653 uint64_t xer;
654 uint64_t ccr;
655 uint64_t softe;
656 uint64_t trap;
657 uint64_t dar;
658 uint64_t dsisr;
659 uint64_t result;
660};
661
662typedef struct SpaprDeviceTreeUpdateHeader {
663 uint32_t version_id;
664} SpaprDeviceTreeUpdateHeader;
665
666#define hcall_dprintf(fmt, ...) \
667 do { \
668 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
669 } while (0)
670
671typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
672 target_ulong opcode,
673 target_ulong *args);
674
675void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
676target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
677 target_ulong *args);
678
679void spapr_exit_nested(PowerPCCPU *cpu, int excp);
680
681target_ulong softmmu_resize_hpt_prepare(PowerPCCPU *cpu, SpaprMachineState *spapr,
682 target_ulong shift);
683target_ulong softmmu_resize_hpt_commit(PowerPCCPU *cpu, SpaprMachineState *spapr,
684 target_ulong flags, target_ulong shift);
685bool is_ram_address(SpaprMachineState *spapr, hwaddr addr);
686void push_sregs_to_kvm_pr(SpaprMachineState *spapr);
687
688
689#define VPA_MIN_SIZE 640
690#define VPA_SIZE_OFFSET 0x4
691#define VPA_SHARED_PROC_OFFSET 0x9
692#define VPA_SHARED_PROC_VAL 0x2
693#define VPA_DISPATCH_COUNTER 0x100
694
695
696#define RTAS_EEH_DISABLE 0
697#define RTAS_EEH_ENABLE 1
698#define RTAS_EEH_THAW_IO 2
699#define RTAS_EEH_THAW_DMA 3
700
701
702#define RTAS_GET_PE_ADDR 0
703#define RTAS_GET_PE_MODE 1
704#define RTAS_PE_MODE_NONE 0
705#define RTAS_PE_MODE_NOT_SHARED 1
706#define RTAS_PE_MODE_SHARED 2
707
708
709#define RTAS_EEH_PE_STATE_NORMAL 0
710#define RTAS_EEH_PE_STATE_RESET 1
711#define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
712#define RTAS_EEH_PE_STATE_STOPPED_DMA 4
713#define RTAS_EEH_PE_STATE_UNAVAIL 5
714#define RTAS_EEH_NOT_SUPPORT 0
715#define RTAS_EEH_SUPPORT 1
716#define RTAS_EEH_PE_UNAVAIL_INFO 1000
717#define RTAS_EEH_PE_RECOVER_INFO 0
718
719
720#define RTAS_SLOT_RESET_DEACTIVATE 0
721#define RTAS_SLOT_RESET_HOT 1
722#define RTAS_SLOT_RESET_FUNDAMENTAL 3
723
724
725#define RTAS_SLOT_TEMP_ERR_LOG 1
726#define RTAS_SLOT_PERM_ERR_LOG 2
727
728
729#define RTAS_OUT_SUCCESS 0
730#define RTAS_OUT_NO_ERRORS_FOUND 1
731#define RTAS_OUT_HW_ERROR -1
732#define RTAS_OUT_BUSY -2
733#define RTAS_OUT_PARAM_ERROR -3
734#define RTAS_OUT_NOT_SUPPORTED -3
735#define RTAS_OUT_NO_SUCH_INDICATOR -3
736#define RTAS_OUT_NOT_AUTHORIZED -9002
737#define RTAS_OUT_SYSPARM_PARAM_ERROR -9999
738
739
740#define RTAS_DDW_PGSIZE_4K 0x01
741#define RTAS_DDW_PGSIZE_64K 0x02
742#define RTAS_DDW_PGSIZE_16M 0x04
743#define RTAS_DDW_PGSIZE_32M 0x08
744#define RTAS_DDW_PGSIZE_64M 0x10
745#define RTAS_DDW_PGSIZE_128M 0x20
746#define RTAS_DDW_PGSIZE_256M 0x40
747#define RTAS_DDW_PGSIZE_16G 0x80
748
749
750#define RTAS_TOKEN_BASE 0x2000
751
752#define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00)
753#define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01)
754#define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02)
755#define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03)
756#define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04)
757#define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05)
758#define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06)
759#define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07)
760#define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08)
761#define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09)
762#define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A)
763#define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B)
764#define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C)
765#define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D)
766#define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E)
767#define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F)
768#define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10)
769#define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11)
770#define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12)
771#define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13)
772#define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14)
773#define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15)
774#define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16)
775#define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17)
776#define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18)
777#define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19)
778#define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A)
779#define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B)
780#define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C)
781#define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D)
782#define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E)
783#define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F)
784#define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20)
785#define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21)
786#define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22)
787#define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23)
788#define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24)
789#define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25)
790#define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26)
791#define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27)
792#define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28)
793#define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29)
794#define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A)
795#define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B)
796#define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C)
797
798#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D)
799
800
801#define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20
802#define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42
803#define RTAS_SYSPARM_UUID 48
804
805
806
807
808
809
810
811#define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001
812#define RTAS_SENSOR_TYPE_DR 9002
813#define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003
814#define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
815
816
817
818
819#define DIAGNOSTICS_RUN_MODE_DISABLED 0
820#define DIAGNOSTICS_RUN_MODE_STAGGERED 1
821#define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
822#define DIAGNOSTICS_RUN_MODE_PERIODIC 3
823
824static inline uint64_t ppc64_phys_to_real(uint64_t addr)
825{
826 return addr & ~0xF000000000000000ULL;
827}
828
829static inline uint32_t rtas_ld(target_ulong phys, int n)
830{
831 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
832}
833
834static inline uint64_t rtas_ldq(target_ulong phys, int n)
835{
836 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
837}
838
839static inline void rtas_st(target_ulong phys, int n, uint32_t val)
840{
841 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
842}
843
844typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
845 uint32_t token,
846 uint32_t nargs, target_ulong args,
847 uint32_t nret, target_ulong rets);
848void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
849target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm,
850 uint32_t token, uint32_t nargs, target_ulong args,
851 uint32_t nret, target_ulong rets);
852void spapr_dt_rtas_tokens(void *fdt, int rtas);
853void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr);
854
855#define SPAPR_TCE_PAGE_SHIFT 12
856#define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT)
857#define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1)
858
859#define SPAPR_VIO_BASE_LIOBN 0x00000000
860#define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg))
861#define SPAPR_PCI_LIOBN(phb_index, window_num) \
862 (0x80000000 | ((phb_index) << 8) | (window_num))
863#define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000))
864#define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
865
866#define RTAS_MIN_SIZE 20
867#define RTAS_ERROR_LOG_MAX 2048
868
869
870#define RTAS_ERROR_LOG_OFFSET 0x30
871
872#define RTAS_EVENT_SCAN_RATE 1
873
874
875
876
877
878static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi)
879{
880 intspec[0] = cpu_to_be32(irq);
881 intspec[1] = is_lsi ? cpu_to_be32(1) : 0;
882}
883
884
885#define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
886OBJECT_DECLARE_SIMPLE_TYPE(SpaprTceTable, SPAPR_TCE_TABLE)
887
888#define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region"
889DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, SPAPR_IOMMU_MEMORY_REGION,
890 TYPE_SPAPR_IOMMU_MEMORY_REGION)
891
892struct SpaprTceTable {
893 DeviceState parent;
894 uint32_t liobn;
895 uint32_t nb_table;
896 uint64_t bus_offset;
897 uint32_t page_shift;
898 uint64_t *table;
899 uint32_t mig_nb_table;
900 uint64_t *mig_table;
901 bool bypass;
902 bool need_vfio;
903 bool skipping_replay;
904 int fd;
905 MemoryRegion root;
906 IOMMUMemoryRegion iommu;
907 struct SpaprVioDevice *vdev;
908 QLIST_ENTRY(SpaprTceTable) list;
909};
910
911SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn);
912
913struct SpaprEventLogEntry {
914 uint32_t summary;
915 uint32_t extended_length;
916 void *extended_log;
917 QTAILQ_ENTRY(SpaprEventLogEntry) next;
918};
919
920void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space);
921void spapr_events_init(SpaprMachineState *sm);
922void spapr_dt_events(SpaprMachineState *sm, void *fdt);
923void close_htab_fd(SpaprMachineState *spapr);
924void spapr_setup_hpt(SpaprMachineState *spapr);
925void spapr_free_hpt(SpaprMachineState *spapr);
926void spapr_check_mmu_mode(bool guest_radix);
927SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
928void spapr_tce_table_enable(SpaprTceTable *tcet,
929 uint32_t page_shift, uint64_t bus_offset,
930 uint32_t nb_table);
931void spapr_tce_table_disable(SpaprTceTable *tcet);
932void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio);
933
934MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet);
935int spapr_dma_dt(void *fdt, int node_off, const char *propname,
936 uint32_t liobn, uint64_t window, uint32_t size);
937int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
938 SpaprTceTable *tcet);
939void spapr_pci_switch_vga(SpaprMachineState *spapr, bool big_endian);
940void spapr_hotplug_req_add_by_index(SpaprDrc *drc);
941void spapr_hotplug_req_remove_by_index(SpaprDrc *drc);
942void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type,
943 uint32_t count);
944void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type,
945 uint32_t count);
946void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type,
947 uint32_t count, uint32_t index);
948void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type,
949 uint32_t count, uint32_t index);
950int spapr_hpt_shift_for_ramsize(uint64_t ramsize);
951int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp);
952void spapr_clear_pending_events(SpaprMachineState *spapr);
953void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr);
954void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev);
955int spapr_max_server_number(SpaprMachineState *spapr);
956void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
957 uint64_t pte0, uint64_t pte1);
958void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered);
959
960
961void spapr_core_release(DeviceState *dev);
962int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
963 void *fdt, int *fdt_start_offset, Error **errp);
964void spapr_lmb_release(DeviceState *dev);
965int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
966 void *fdt, int *fdt_start_offset, Error **errp);
967void spapr_phb_release(DeviceState *dev);
968int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
969 void *fdt, int *fdt_start_offset, Error **errp);
970
971void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns);
972int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset);
973
974#define TYPE_SPAPR_RNG "spapr-rng"
975
976#define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28)
977
978
979
980
981
982
983#define SPAPR_MAX_RAM_SLOTS 32
984
985
986#define SPAPR_DEVICE_MEM_ALIGN (1 * GiB)
987
988
989
990
991
992#define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
993
994
995
996
997
998#define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
999#define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
1000#define SPAPR_LMB_FLAGS_RESERVED 0x00000080
1001#define SPAPR_LMB_FLAGS_HOTREMOVABLE 0x00000100
1002
1003void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg);
1004
1005#define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
1006
1007int spapr_get_vcpu_id(PowerPCCPU *cpu);
1008bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp);
1009PowerPCCPU *spapr_find_cpu(int vcpu_id);
1010
1011int spapr_caps_pre_load(void *opaque);
1012int spapr_caps_pre_save(void *opaque);
1013
1014
1015
1016
1017extern const VMStateDescription vmstate_spapr_cap_htm;
1018extern const VMStateDescription vmstate_spapr_cap_vsx;
1019extern const VMStateDescription vmstate_spapr_cap_dfp;
1020extern const VMStateDescription vmstate_spapr_cap_cfpc;
1021extern const VMStateDescription vmstate_spapr_cap_sbbc;
1022extern const VMStateDescription vmstate_spapr_cap_ibs;
1023extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize;
1024extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv;
1025extern const VMStateDescription vmstate_spapr_cap_large_decr;
1026extern const VMStateDescription vmstate_spapr_cap_ccf_assist;
1027extern const VMStateDescription vmstate_spapr_cap_fwnmi;
1028extern const VMStateDescription vmstate_spapr_cap_rpt_invalidate;
1029
1030static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap)
1031{
1032 return spapr->eff.caps[cap];
1033}
1034
1035void spapr_caps_init(SpaprMachineState *spapr);
1036void spapr_caps_apply(SpaprMachineState *spapr);
1037void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu);
1038void spapr_caps_add_properties(SpaprMachineClass *smc);
1039int spapr_caps_post_migration(SpaprMachineState *spapr);
1040
1041bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize,
1042 Error **errp);
1043
1044
1045
1046#define SPAPR_OV5_XIVE_LEGACY 0x0
1047#define SPAPR_OV5_XIVE_EXPLOIT 0x40
1048#define SPAPR_OV5_XIVE_BOTH 0x80
1049
1050void spapr_set_all_lpcrs(target_ulong value, target_ulong mask);
1051hwaddr spapr_get_rtas_addr(void);
1052bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr);
1053
1054void spapr_vof_reset(SpaprMachineState *spapr, void *fdt, Error **errp);
1055void spapr_vof_quiesce(MachineState *ms);
1056bool spapr_vof_setprop(MachineState *ms, const char *path, const char *propname,
1057 void *val, int vallen);
1058target_ulong spapr_h_vof_client(PowerPCCPU *cpu, SpaprMachineState *spapr,
1059 target_ulong opcode, target_ulong *args);
1060target_ulong spapr_vof_client_architecture_support(MachineState *ms,
1061 CPUState *cs,
1062 target_ulong ovec_addr);
1063void spapr_vof_client_dt_finalize(SpaprMachineState *spapr, void *fdt);
1064
1065#endif
1066