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14#ifndef HW_S390_PCI_BUS_H
15#define HW_S390_PCI_BUS_H
16
17#include "hw/pci/pci.h"
18#include "hw/pci/pci_host.h"
19#include "hw/s390x/sclp.h"
20#include "hw/s390x/s390_flic.h"
21#include "hw/s390x/css.h"
22#include "hw/s390x/s390-pci-clp.h"
23#include "qom/object.h"
24
25#define TYPE_S390_PCI_HOST_BRIDGE "s390-pcihost"
26#define TYPE_S390_PCI_BUS "s390-pcibus"
27#define TYPE_S390_PCI_DEVICE "zpci"
28#define TYPE_S390_PCI_IOMMU "s390-pci-iommu"
29#define TYPE_S390_IOMMU_MEMORY_REGION "s390-iommu-memory-region"
30#define FH_MASK_ENABLE 0x80000000
31#define FH_MASK_INSTANCE 0x7f000000
32#define FH_MASK_SHM 0x00ff0000
33#define FH_MASK_INDEX 0x0000ffff
34#define FH_SHM_VFIO 0x00010000
35#define FH_SHM_EMUL 0x00020000
36#define ZPCI_MAX_FID 0xffffffff
37#define ZPCI_MAX_UID 0xffff
38#define UID_UNDEFINED 0
39#define UID_CHECKING_ENABLED 0x01
40#define ZPCI_DTSM 0x40
41
42OBJECT_DECLARE_SIMPLE_TYPE(S390pciState, S390_PCI_HOST_BRIDGE)
43OBJECT_DECLARE_SIMPLE_TYPE(S390PCIBus, S390_PCI_BUS)
44OBJECT_DECLARE_SIMPLE_TYPE(S390PCIBusDevice, S390_PCI_DEVICE)
45OBJECT_DECLARE_SIMPLE_TYPE(S390PCIIOMMU, S390_PCI_IOMMU)
46
47#define HP_EVENT_TO_CONFIGURED 0x0301
48#define HP_EVENT_RESERVED_TO_STANDBY 0x0302
49#define HP_EVENT_DECONFIGURE_REQUEST 0x0303
50#define HP_EVENT_CONFIGURED_TO_STBRES 0x0304
51#define HP_EVENT_STANDBY_TO_RESERVED 0x0308
52
53#define ERR_EVENT_INVALAS 0x1
54#define ERR_EVENT_OORANGE 0x2
55#define ERR_EVENT_INVALTF 0x3
56#define ERR_EVENT_TPROTE 0x4
57#define ERR_EVENT_APROTE 0x5
58#define ERR_EVENT_KEYE 0x6
59#define ERR_EVENT_INVALTE 0x7
60#define ERR_EVENT_INVALTL 0x8
61#define ERR_EVENT_TT 0x9
62#define ERR_EVENT_INVALMS 0xa
63#define ERR_EVENT_SERR 0xb
64#define ERR_EVENT_NOMSI 0x10
65#define ERR_EVENT_INVALBV 0x11
66#define ERR_EVENT_AIBV 0x12
67#define ERR_EVENT_AIRERR 0x13
68#define ERR_EVENT_FMBA 0x2a
69#define ERR_EVENT_FMBUP 0x2b
70#define ERR_EVENT_FMBPRO 0x2c
71#define ERR_EVENT_CCONF 0x30
72#define ERR_EVENT_SERVAC 0x3a
73#define ERR_EVENT_PERMERR 0x3b
74
75#define ERR_EVENT_Q_BIT 0x2
76#define ERR_EVENT_MVN_OFFSET 16
77
78#define ZPCI_MSI_VEC_BITS 11
79#define ZPCI_MSI_VEC_MASK 0x7ff
80
81#define ZPCI_MSI_ADDR 0xfe00000000000000ULL
82#define ZPCI_SDMA_ADDR 0x100000000ULL
83#define ZPCI_EDMA_ADDR 0x1ffffffffffffffULL
84
85#define PAGE_DEFAULT_ACC 0
86#define PAGE_DEFAULT_KEY (PAGE_DEFAULT_ACC << 4)
87
88
89enum ZpciIoatDtype {
90 ZPCI_IOTA_STO = 0,
91 ZPCI_IOTA_RTTO = 1,
92 ZPCI_IOTA_RSTO = 2,
93 ZPCI_IOTA_RFTO = 3,
94 ZPCI_IOTA_PFAA = 4,
95 ZPCI_IOTA_IOPFAA = 5,
96 ZPCI_IOTA_IOPTO = 7
97};
98
99#define ZPCI_IOTA_IOT_ENABLED 0x800ULL
100#define ZPCI_IOTA_DT_ST (ZPCI_IOTA_STO << 2)
101#define ZPCI_IOTA_DT_RT (ZPCI_IOTA_RTTO << 2)
102#define ZPCI_IOTA_DT_RS (ZPCI_IOTA_RSTO << 2)
103#define ZPCI_IOTA_DT_RF (ZPCI_IOTA_RFTO << 2)
104#define ZPCI_IOTA_DT_PF (ZPCI_IOTA_PFAA << 2)
105#define ZPCI_IOTA_FS_4K 0
106#define ZPCI_IOTA_FS_1M 1
107#define ZPCI_IOTA_FS_2G 2
108#define ZPCI_KEY (PAGE_DEFAULT_KEY << 5)
109
110#define ZPCI_IOTA_STO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_ST)
111#define ZPCI_IOTA_RTTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RT)
112#define ZPCI_IOTA_RSTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RS)
113#define ZPCI_IOTA_RFTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RF)
114#define ZPCI_IOTA_RFAA_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY |\
115 ZPCI_IOTA_DT_PF | ZPCI_IOTA_FS_2G)
116
117
118#define ZPCI_INDEX_MASK 0x7ffULL
119
120#define ZPCI_TABLE_TYPE_MASK 0xc
121#define ZPCI_TABLE_TYPE_RFX 0xc
122#define ZPCI_TABLE_TYPE_RSX 0x8
123#define ZPCI_TABLE_TYPE_RTX 0x4
124#define ZPCI_TABLE_TYPE_SX 0x0
125
126#define ZPCI_TABLE_LEN_RFX 0x3
127#define ZPCI_TABLE_LEN_RSX 0x3
128#define ZPCI_TABLE_LEN_RTX 0x3
129
130#define ZPCI_TABLE_OFFSET_MASK 0xc0
131#define ZPCI_TABLE_SIZE 0x4000
132#define ZPCI_TABLE_ALIGN ZPCI_TABLE_SIZE
133#define ZPCI_TABLE_ENTRY_SIZE (sizeof(unsigned long))
134#define ZPCI_TABLE_ENTRIES (ZPCI_TABLE_SIZE / ZPCI_TABLE_ENTRY_SIZE)
135
136#define ZPCI_TABLE_BITS 11
137#define ZPCI_PT_BITS 8
138#define ZPCI_ST_SHIFT (ZPCI_PT_BITS + TARGET_PAGE_BITS)
139#define ZPCI_RT_SHIFT (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS)
140
141#define ZPCI_RTE_FLAG_MASK 0x3fffULL
142#define ZPCI_RTE_ADDR_MASK (~ZPCI_RTE_FLAG_MASK)
143#define ZPCI_STE_FLAG_MASK 0x7ffULL
144#define ZPCI_STE_ADDR_MASK (~ZPCI_STE_FLAG_MASK)
145
146#define ZPCI_SFAA_MASK (~((1ULL << 20) - 1))
147
148
149#define ZPCI_PTE_VALID_MASK 0x400
150#define ZPCI_PTE_INVALID 0x400
151#define ZPCI_PTE_VALID 0x000
152#define ZPCI_PT_SIZE 0x800
153#define ZPCI_PT_ALIGN ZPCI_PT_SIZE
154#define ZPCI_PT_ENTRIES (ZPCI_PT_SIZE / ZPCI_TABLE_ENTRY_SIZE)
155#define ZPCI_PT_MASK (ZPCI_PT_ENTRIES - 1)
156
157#define ZPCI_PTE_FLAG_MASK 0xfffULL
158#define ZPCI_PTE_ADDR_MASK (~ZPCI_PTE_FLAG_MASK)
159
160
161#define ZPCI_TABLE_VALID 0x00
162#define ZPCI_TABLE_INVALID 0x20
163#define ZPCI_TABLE_PROTECTED 0x200
164#define ZPCI_TABLE_UNPROTECTED 0x000
165#define ZPCI_TABLE_FC 0x400
166
167#define ZPCI_TABLE_VALID_MASK 0x20
168#define ZPCI_TABLE_PROT_MASK 0x200
169
170#define ZPCI_ETT_RT 1
171#define ZPCI_ETT_ST 0
172#define ZPCI_ETT_PT -1
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192typedef enum {
193 ZPCI_FS_RESERVED,
194 ZPCI_FS_STANDBY,
195 ZPCI_FS_DISABLED,
196 ZPCI_FS_ENABLED,
197 ZPCI_FS_BLOCKED,
198 ZPCI_FS_ERROR,
199 ZPCI_FS_PERMANENT_ERROR,
200} ZpciState;
201
202typedef struct SeiContainer {
203 QTAILQ_ENTRY(SeiContainer) link;
204 uint32_t fid;
205 uint32_t fh;
206 uint8_t cc;
207 uint16_t pec;
208 uint64_t faddr;
209 uint32_t e;
210} SeiContainer;
211
212typedef struct PciCcdfErr {
213 uint32_t reserved1;
214 uint32_t fh;
215 uint32_t fid;
216 uint32_t e;
217 uint64_t faddr;
218 uint32_t reserved3;
219 uint16_t reserved4;
220 uint16_t pec;
221} QEMU_PACKED PciCcdfErr;
222
223typedef struct PciCcdfAvail {
224 uint32_t reserved1;
225 uint32_t fh;
226 uint32_t fid;
227 uint32_t reserved2;
228 uint32_t reserved3;
229 uint32_t reserved4;
230 uint32_t reserved5;
231 uint16_t reserved6;
232 uint16_t pec;
233} QEMU_PACKED PciCcdfAvail;
234
235typedef struct ChscSeiNt2Res {
236 uint16_t length;
237 uint16_t code;
238 uint16_t reserved1;
239 uint8_t reserved2;
240 uint8_t nt;
241 uint8_t flags;
242 uint8_t reserved3;
243 uint8_t reserved4;
244 uint8_t cc;
245 uint32_t reserved5[13];
246 uint8_t ccdf[4016];
247} QEMU_PACKED ChscSeiNt2Res;
248
249typedef struct S390MsixInfo {
250 uint8_t table_bar;
251 uint8_t pba_bar;
252 uint16_t entries;
253 uint32_t table_offset;
254 uint32_t pba_offset;
255} S390MsixInfo;
256
257typedef struct S390IOTLBEntry {
258 uint64_t iova;
259 uint64_t translated_addr;
260 uint64_t len;
261 uint64_t perm;
262} S390IOTLBEntry;
263
264typedef struct S390PCIDMACount {
265 int id;
266 int users;
267 uint32_t avail;
268 QTAILQ_ENTRY(S390PCIDMACount) link;
269} S390PCIDMACount;
270
271struct S390PCIIOMMU {
272 Object parent_obj;
273 S390PCIBusDevice *pbdev;
274 AddressSpace as;
275 MemoryRegion mr;
276 IOMMUMemoryRegion iommu_mr;
277 bool enabled;
278 uint64_t g_iota;
279 uint64_t pba;
280 uint64_t pal;
281 GHashTable *iotlb;
282 S390PCIDMACount *dma_limit;
283};
284
285typedef struct S390PCIIOMMUTable {
286 uint64_t key;
287 S390PCIIOMMU *iommu[PCI_SLOT_MAX];
288} S390PCIIOMMUTable;
289
290
291#define DEFAULT_MUI 4000
292#define UPDATE_U_BIT 0x1ULL
293#define FMBK_MASK 0xfULL
294
295typedef struct ZpciFmbFmt0 {
296 uint64_t dma_rbytes;
297 uint64_t dma_wbytes;
298} ZpciFmbFmt0;
299
300#define ZPCI_FMB_CNT_LD 0
301#define ZPCI_FMB_CNT_ST 1
302#define ZPCI_FMB_CNT_STB 2
303#define ZPCI_FMB_CNT_RPCIT 3
304#define ZPCI_FMB_CNT_MAX 4
305
306#define ZPCI_FMB_FORMAT 0
307
308typedef struct ZpciFmb {
309 uint32_t format;
310 uint32_t sample;
311 uint64_t last_update;
312 uint64_t counter[ZPCI_FMB_CNT_MAX];
313 ZpciFmbFmt0 fmt0;
314} ZpciFmb;
315QEMU_BUILD_BUG_MSG(offsetof(ZpciFmb, fmt0) != 48, "padding in ZpciFmb");
316
317#define ZPCI_DEFAULT_FN_GRP 0xFF
318typedef struct S390PCIGroup {
319 ClpRspQueryPciGrp zpci_group;
320 int id;
321 QTAILQ_ENTRY(S390PCIGroup) link;
322} S390PCIGroup;
323S390PCIGroup *s390_group_create(int id);
324S390PCIGroup *s390_group_find(int id);
325
326struct S390PCIBusDevice {
327 DeviceState qdev;
328 PCIDevice *pdev;
329 ZpciState state;
330 char *target;
331 uint16_t uid;
332 uint32_t idx;
333 uint32_t fh;
334 uint32_t fid;
335 bool fid_defined;
336 uint64_t fmb_addr;
337 ZpciFmb fmb;
338 QEMUTimer *fmb_timer;
339 uint8_t isc;
340 uint16_t noi;
341 uint16_t maxstbl;
342 uint8_t sum;
343 S390PCIGroup *pci_group;
344 ClpRspQueryPci zpci_fn;
345 S390MsixInfo msix;
346 AdapterRoutes routes;
347 S390PCIIOMMU *iommu;
348 MemoryRegion msix_notify_mr;
349 IndAddr *summary_ind;
350 IndAddr *indicator;
351 bool pci_unplug_request_processed;
352 bool unplug_requested;
353 QTAILQ_ENTRY(S390PCIBusDevice) link;
354};
355
356struct S390PCIBus {
357 BusState qbus;
358};
359
360struct S390pciState {
361 PCIHostState parent_obj;
362 uint32_t next_idx;
363 int bus_no;
364 S390PCIBus *bus;
365 GHashTable *iommu_table;
366 GHashTable *zpci_table;
367 QTAILQ_HEAD(, SeiContainer) pending_sei;
368 QTAILQ_HEAD(, S390PCIBusDevice) zpci_devs;
369 QTAILQ_HEAD(, S390PCIDMACount) zpci_dma_limit;
370 QTAILQ_HEAD(, S390PCIGroup) zpci_groups;
371};
372
373S390pciState *s390_get_phb(void);
374int pci_chsc_sei_nt2_get_event(void *res);
375int pci_chsc_sei_nt2_have_event(void);
376void s390_pci_sclp_configure(SCCB *sccb);
377void s390_pci_sclp_deconfigure(SCCB *sccb);
378void s390_pci_iommu_enable(S390PCIIOMMU *iommu);
379void s390_pci_iommu_disable(S390PCIIOMMU *iommu);
380void s390_pci_generate_error_event(uint16_t pec, uint32_t fh, uint32_t fid,
381 uint64_t faddr, uint32_t e);
382uint16_t s390_guest_io_table_walk(uint64_t g_iota, hwaddr addr,
383 S390IOTLBEntry *entry);
384S390PCIBusDevice *s390_pci_find_dev_by_idx(S390pciState *s, uint32_t idx);
385S390PCIBusDevice *s390_pci_find_dev_by_fh(S390pciState *s, uint32_t fh);
386S390PCIBusDevice *s390_pci_find_dev_by_fid(S390pciState *s, uint32_t fid);
387S390PCIBusDevice *s390_pci_find_dev_by_target(S390pciState *s,
388 const char *target);
389S390PCIBusDevice *s390_pci_find_next_avail_dev(S390pciState *s,
390 S390PCIBusDevice *pbdev);
391
392#endif
393
