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24#include "qemu/osdep.h"
25#include "qapi/error.h"
26#include "qemu/qemu-print.h"
27#include "cpu.h"
28#include "mmu.h"
29
30
31static void cris_cpu_set_pc(CPUState *cs, vaddr value)
32{
33 CRISCPU *cpu = CRIS_CPU(cs);
34
35 cpu->env.pc = value;
36}
37
38static bool cris_cpu_has_work(CPUState *cs)
39{
40 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
41}
42
43static void cris_cpu_reset(DeviceState *dev)
44{
45 CPUState *s = CPU(dev);
46 CRISCPU *cpu = CRIS_CPU(s);
47 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu);
48 CPUCRISState *env = &cpu->env;
49 uint32_t vr;
50
51 ccc->parent_reset(dev);
52
53 vr = env->pregs[PR_VR];
54 memset(env, 0, offsetof(CPUCRISState, end_reset_fields));
55 env->pregs[PR_VR] = vr;
56
57#if defined(CONFIG_USER_ONLY)
58
59 env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
60#else
61 cris_mmu_init(env);
62 env->pregs[PR_CCS] = 0;
63#endif
64}
65
66static ObjectClass *cris_cpu_class_by_name(const char *cpu_model)
67{
68 ObjectClass *oc;
69 char *typename;
70
71#if defined(CONFIG_USER_ONLY)
72 if (strcasecmp(cpu_model, "any") == 0) {
73 return object_class_by_name(CRIS_CPU_TYPE_NAME("crisv32"));
74 }
75#endif
76
77 typename = g_strdup_printf(CRIS_CPU_TYPE_NAME("%s"), cpu_model);
78 oc = object_class_by_name(typename);
79 g_free(typename);
80 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) ||
81 object_class_is_abstract(oc))) {
82 oc = NULL;
83 }
84 return oc;
85}
86
87
88static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b)
89{
90 CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a);
91 CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b);
92
93
94 if (ccc_a->vr > ccc_b->vr) {
95 return 1;
96 } else if (ccc_a->vr < ccc_b->vr) {
97 return -1;
98 } else {
99 return 0;
100 }
101}
102
103static void cris_cpu_list_entry(gpointer data, gpointer user_data)
104{
105 ObjectClass *oc = data;
106 const char *typename = object_class_get_name(oc);
107 char *name;
108
109 name = g_strndup(typename, strlen(typename) - strlen(CRIS_CPU_TYPE_SUFFIX));
110 qemu_printf(" %s\n", name);
111 g_free(name);
112}
113
114void cris_cpu_list(void)
115{
116 GSList *list;
117
118 list = object_class_get_list(TYPE_CRIS_CPU, false);
119 list = g_slist_sort(list, cris_cpu_list_compare);
120 qemu_printf("Available CPUs:\n");
121 g_slist_foreach(list, cris_cpu_list_entry, NULL);
122 g_slist_free(list);
123}
124
125static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
126{
127 CPUState *cs = CPU(dev);
128 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev);
129 Error *local_err = NULL;
130
131 cpu_exec_realizefn(cs, &local_err);
132 if (local_err != NULL) {
133 error_propagate(errp, local_err);
134 return;
135 }
136
137 cpu_reset(cs);
138 qemu_init_vcpu(cs);
139
140 ccc->parent_realize(dev, errp);
141}
142
143#ifndef CONFIG_USER_ONLY
144static void cris_cpu_set_irq(void *opaque, int irq, int level)
145{
146 CRISCPU *cpu = opaque;
147 CPUState *cs = CPU(cpu);
148 int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI;
149
150 if (irq == CRIS_CPU_IRQ) {
151
152
153
154
155 cpu->env.interrupt_vector = level;
156 }
157
158 if (level) {
159 cpu_interrupt(cs, type);
160 } else {
161 cpu_reset_interrupt(cs, type);
162 }
163}
164#endif
165
166static void cris_disas_set_info(CPUState *cpu, disassemble_info *info)
167{
168 CRISCPU *cc = CRIS_CPU(cpu);
169 CPUCRISState *env = &cc->env;
170
171 if (env->pregs[PR_VR] != 32) {
172 info->mach = bfd_mach_cris_v0_v10;
173 info->print_insn = print_insn_crisv10;
174 } else {
175 info->mach = bfd_mach_cris_v32;
176 info->print_insn = print_insn_crisv32;
177 }
178}
179
180static void cris_cpu_initfn(Object *obj)
181{
182 CRISCPU *cpu = CRIS_CPU(obj);
183 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
184 CPUCRISState *env = &cpu->env;
185
186 cpu_set_cpustate_pointers(cpu);
187
188 env->pregs[PR_VR] = ccc->vr;
189
190#ifndef CONFIG_USER_ONLY
191
192 qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2);
193#endif
194}
195
196#ifndef CONFIG_USER_ONLY
197#include "hw/core/sysemu-cpu-ops.h"
198
199static const struct SysemuCPUOps cris_sysemu_ops = {
200 .get_phys_page_debug = cris_cpu_get_phys_page_debug,
201};
202#endif
203
204#include "hw/core/tcg-cpu-ops.h"
205
206static const struct TCGCPUOps crisv10_tcg_ops = {
207 .initialize = cris_initialize_crisv10_tcg,
208
209#ifndef CONFIG_USER_ONLY
210 .tlb_fill = cris_cpu_tlb_fill,
211 .cpu_exec_interrupt = cris_cpu_exec_interrupt,
212 .do_interrupt = crisv10_cpu_do_interrupt,
213#endif
214};
215
216static const struct TCGCPUOps crisv32_tcg_ops = {
217 .initialize = cris_initialize_tcg,
218
219#ifndef CONFIG_USER_ONLY
220 .tlb_fill = cris_cpu_tlb_fill,
221 .cpu_exec_interrupt = cris_cpu_exec_interrupt,
222 .do_interrupt = cris_cpu_do_interrupt,
223#endif
224};
225
226static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
227{
228 CPUClass *cc = CPU_CLASS(oc);
229 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
230
231 ccc->vr = 8;
232 cc->gdb_read_register = crisv10_cpu_gdb_read_register;
233 cc->tcg_ops = &crisv10_tcg_ops;
234}
235
236static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
237{
238 CPUClass *cc = CPU_CLASS(oc);
239 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
240
241 ccc->vr = 9;
242 cc->gdb_read_register = crisv10_cpu_gdb_read_register;
243 cc->tcg_ops = &crisv10_tcg_ops;
244}
245
246static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
247{
248 CPUClass *cc = CPU_CLASS(oc);
249 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
250
251 ccc->vr = 10;
252 cc->gdb_read_register = crisv10_cpu_gdb_read_register;
253 cc->tcg_ops = &crisv10_tcg_ops;
254}
255
256static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
257{
258 CPUClass *cc = CPU_CLASS(oc);
259 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
260
261 ccc->vr = 11;
262 cc->gdb_read_register = crisv10_cpu_gdb_read_register;
263 cc->tcg_ops = &crisv10_tcg_ops;
264}
265
266static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
267{
268 CPUClass *cc = CPU_CLASS(oc);
269 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
270
271 ccc->vr = 17;
272 cc->gdb_read_register = crisv10_cpu_gdb_read_register;
273 cc->tcg_ops = &crisv10_tcg_ops;
274}
275
276static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
277{
278 CPUClass *cc = CPU_CLASS(oc);
279 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
280
281 ccc->vr = 32;
282 cc->tcg_ops = &crisv32_tcg_ops;
283}
284
285static void cris_cpu_class_init(ObjectClass *oc, void *data)
286{
287 DeviceClass *dc = DEVICE_CLASS(oc);
288 CPUClass *cc = CPU_CLASS(oc);
289 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
290
291 device_class_set_parent_realize(dc, cris_cpu_realizefn,
292 &ccc->parent_realize);
293
294 device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset);
295
296 cc->class_by_name = cris_cpu_class_by_name;
297 cc->has_work = cris_cpu_has_work;
298 cc->dump_state = cris_cpu_dump_state;
299 cc->set_pc = cris_cpu_set_pc;
300 cc->gdb_read_register = cris_cpu_gdb_read_register;
301 cc->gdb_write_register = cris_cpu_gdb_write_register;
302#ifndef CONFIG_USER_ONLY
303 dc->vmsd = &vmstate_cris_cpu;
304 cc->sysemu_ops = &cris_sysemu_ops;
305#endif
306
307 cc->gdb_num_core_regs = 49;
308 cc->gdb_stop_before_watchpoint = true;
309
310 cc->disas_set_info = cris_disas_set_info;
311}
312
313#define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \
314 { \
315 .parent = TYPE_CRIS_CPU, \
316 .class_init = initfn, \
317 .name = CRIS_CPU_TYPE_NAME(cpu_model), \
318 }
319
320static const TypeInfo cris_cpu_model_type_infos[] = {
321 {
322 .name = TYPE_CRIS_CPU,
323 .parent = TYPE_CPU,
324 .instance_size = sizeof(CRISCPU),
325 .instance_init = cris_cpu_initfn,
326 .abstract = true,
327 .class_size = sizeof(CRISCPUClass),
328 .class_init = cris_cpu_class_init,
329 },
330 DEFINE_CRIS_CPU_TYPE("crisv8", crisv8_cpu_class_init),
331 DEFINE_CRIS_CPU_TYPE("crisv9", crisv9_cpu_class_init),
332 DEFINE_CRIS_CPU_TYPE("crisv10", crisv10_cpu_class_init),
333 DEFINE_CRIS_CPU_TYPE("crisv11", crisv11_cpu_class_init),
334 DEFINE_CRIS_CPU_TYPE("crisv17", crisv17_cpu_class_init),
335 DEFINE_CRIS_CPU_TYPE("crisv32", crisv32_cpu_class_init),
336};
337
338DEFINE_TYPES(cris_cpu_model_type_infos)
339
