LXR qemu/target/riscv/cpu-param.h

   1/*
   2 * RISC-V cpu parameters for qemu.
   3 *
   4 * Copyright (c) 2017-2018 SiFive, Inc.
   5 * SPDX-License-Identifier: GPL-2.0+
   6 */
   7
   8#ifndef RISCV_CPU_PARAM_H
   9#define RISCV_CPU_PARAM_H 1
  10
  11#if defined(TARGET_RISCV64)
  12# define TARGET_LONG_BITS 64
  13# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */
  14# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */
  15#elif defined(TARGET_RISCV32)
  16# define TARGET_LONG_BITS 32
  17# define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */
  18# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
  19#endif
  20#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
  21/*
  22 * The current MMU Modes are:
  23 *  - U mode 0b000
  24 *  - S mode 0b001
  25 *  - M mode 0b011
  26 *  - U mode HLV/HLVX/HSV 0b100
  27 *  - S mode HLV/HLVX/HSV 0b101
  28 *  - M mode HLV/HLVX/HSV 0b111
  29 */
  30#define NB_MMU_MODES 8
  31
  32#endif
  33