qemu/target/riscv/insn32.decode
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   1#
   2# RISC-V translation routines for the RVXI Base Integer Instruction Set.
   3#
   4# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
   5#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
   6#
   7# This program is free software; you can redistribute it and/or modify it
   8# under the terms and conditions of the GNU General Public License,
   9# version 2 or later, as published by the Free Software Foundation.
  10#
  11# This program is distributed in the hope it will be useful, but WITHOUT
  12# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14# more details.
  15#
  16# You should have received a copy of the GNU General Public License along with
  17# this program.  If not, see <http://www.gnu.org/licenses/>.
  18
  19# Fields:
  20%rs3       27:5
  21%rs2       20:5
  22%rs1       15:5
  23%rd        7:5
  24%sh5       20:5
  25%sh6       20:6
  26
  27%sh7    20:7
  28%csr    20:12
  29%rm     12:3
  30%nf     29:3                     !function=ex_plus_1
  31
  32# immediates:
  33%imm_i    20:s12
  34%imm_s    25:s7 7:5
  35%imm_b    31:s1 7:1 25:6 8:4     !function=ex_shift_1
  36%imm_j    31:s1 12:8 20:1 21:10  !function=ex_shift_1
  37%imm_u    12:s20                 !function=ex_shift_12
  38
  39# Argument sets:
  40&empty
  41&b    imm rs2 rs1
  42&i    imm rs1 rd
  43&j    imm rd
  44&r    rd rs1 rs2
  45&r2   rd rs1
  46&r2_s rs1 rs2
  47&s    imm rs1 rs2
  48&u    imm rd
  49&shift     shamt rs1 rd
  50&atomic    aq rl rs2 rs1 rd
  51&rmrr      vm rd rs1 rs2
  52&rmr       vm rd rs2
  53&r2nfvm    vm rd rs1 nf
  54&rnfvm     vm rd rs1 rs2 nf
  55
  56# Formats 32:
  57@r       .......   ..... ..... ... ..... ....... &r                %rs2 %rs1 %rd
  58@i       ............    ..... ... ..... ....... &i      imm=%imm_i     %rs1 %rd
  59@b       .......   ..... ..... ... ..... ....... &b      imm=%imm_b %rs2 %rs1
  60@s       .......   ..... ..... ... ..... ....... &s      imm=%imm_s %rs2 %rs1
  61@u       ....................      ..... ....... &u      imm=%imm_u          %rd
  62@j       ....................      ..... ....... &j      imm=%imm_j          %rd
  63
  64@sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh7     %rs1 %rd
  65@csr     ............   .....  ... ..... .......               %csr     %rs1 %rd
  66
  67@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0     %rs1 %rd
  68@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2      %rs1 %rd
  69
  70@r4_rm   ..... ..  ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
  71@r_rm    .......   ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
  72@r2_rm   .......   ..... ..... ... ..... ....... %rs1 %rm %rd
  73@r2      .......   ..... ..... ... ..... ....... &r2 %rs1 %rd
  74@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
  75@r2_vm   ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
  76@r1_vm   ...... vm:1 ..... ..... ... ..... ....... %rd
  77@r_nfvm  ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd
  78@r2rd    .......   ..... ..... ... ..... ....... %rs2 %rd
  79@r_vm    ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
  80@r_vm_1  ...... . ..... ..... ... ..... .......    &rmrr vm=1 %rs2 %rs1 %rd
  81@r_vm_0  ...... . ..... ..... ... ..... .......    &rmrr vm=0 %rs2 %rs1 %rd
  82@r2_zimm11 . zimm:11  ..... ... ..... ....... %rs1 %rd
  83@r2_zimm10 .. zimm:10  ..... ... ..... ....... %rs1 %rd
  84@r2_s    .......   ..... ..... ... ..... ....... %rs2 %rs1
  85
  86@hfence_gvma ....... ..... .....   ... ..... ....... %rs2 %rs1
  87@hfence_vvma ....... ..... .....   ... ..... ....... %rs2 %rs1
  88
  89@sfence_vma ....... ..... .....   ... ..... ....... %rs2 %rs1
  90@sfence_vm  ....... ..... .....   ... ..... ....... %rs1
  91
  92# Formats 64:
  93@sh5     .......  ..... .....  ... ..... ....... &shift  shamt=%sh5      %rs1 %rd
  94
  95# Formats 128:
  96@sh6       ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd
  97
  98# *** Privileged Instructions ***
  99ecall       000000000000     00000 000 00000 1110011
 100ebreak      000000000001     00000 000 00000 1110011
 101uret        0000000    00010 00000 000 00000 1110011
 102sret        0001000    00010 00000 000 00000 1110011
 103mret        0011000    00010 00000 000 00000 1110011
 104wfi         0001000    00101 00000 000 00000 1110011
 105sfence_vma  0001001    ..... ..... 000 00000 1110011 @sfence_vma
 106sfence_vm   0001000    00100 ..... 000 00000 1110011 @sfence_vm
 107
 108# *** RV32I Base Instruction Set ***
 109lui      ....................       ..... 0110111 @u
 110auipc    ....................       ..... 0010111 @u
 111jal      ....................       ..... 1101111 @j
 112jalr     ............     ..... 000 ..... 1100111 @i
 113beq      ....... .....    ..... 000 ..... 1100011 @b
 114bne      ....... .....    ..... 001 ..... 1100011 @b
 115blt      ....... .....    ..... 100 ..... 1100011 @b
 116bge      ....... .....    ..... 101 ..... 1100011 @b
 117bltu     ....... .....    ..... 110 ..... 1100011 @b
 118bgeu     ....... .....    ..... 111 ..... 1100011 @b
 119lb       ............     ..... 000 ..... 0000011 @i
 120lh       ............     ..... 001 ..... 0000011 @i
 121lw       ............     ..... 010 ..... 0000011 @i
 122lbu      ............     ..... 100 ..... 0000011 @i
 123lhu      ............     ..... 101 ..... 0000011 @i
 124sb       .......  .....   ..... 000 ..... 0100011 @s
 125sh       .......  .....   ..... 001 ..... 0100011 @s
 126sw       .......  .....   ..... 010 ..... 0100011 @s
 127addi     ............     ..... 000 ..... 0010011 @i
 128slti     ............     ..... 010 ..... 0010011 @i
 129sltiu    ............     ..... 011 ..... 0010011 @i
 130xori     ............     ..... 100 ..... 0010011 @i
 131ori      ............     ..... 110 ..... 0010011 @i
 132andi     ............     ..... 111 ..... 0010011 @i
 133slli     00000. ......    ..... 001 ..... 0010011 @sh
 134srli     00000. ......    ..... 101 ..... 0010011 @sh
 135srai     01000. ......    ..... 101 ..... 0010011 @sh
 136add      0000000 .....    ..... 000 ..... 0110011 @r
 137sub      0100000 .....    ..... 000 ..... 0110011 @r
 138sll      0000000 .....    ..... 001 ..... 0110011 @r
 139slt      0000000 .....    ..... 010 ..... 0110011 @r
 140sltu     0000000 .....    ..... 011 ..... 0110011 @r
 141xor      0000000 .....    ..... 100 ..... 0110011 @r
 142srl      0000000 .....    ..... 101 ..... 0110011 @r
 143sra      0100000 .....    ..... 101 ..... 0110011 @r
 144or       0000000 .....    ..... 110 ..... 0110011 @r
 145and      0000000 .....    ..... 111 ..... 0110011 @r
 146fence    ---- pred:4 succ:4 ----- 000 ----- 0001111
 147fence_i  ---- ----   ----   ----- 001 ----- 0001111
 148csrrw    ............     ..... 001 ..... 1110011 @csr
 149csrrs    ............     ..... 010 ..... 1110011 @csr
 150csrrc    ............     ..... 011 ..... 1110011 @csr
 151csrrwi   ............     ..... 101 ..... 1110011 @csr
 152csrrsi   ............     ..... 110 ..... 1110011 @csr
 153csrrci   ............     ..... 111 ..... 1110011 @csr
 154
 155# *** RV64I Base Instruction Set (in addition to RV32I) ***
 156lwu      ............   ..... 110 ..... 0000011 @i
 157ld       ............   ..... 011 ..... 0000011 @i
 158sd       ....... .....  ..... 011 ..... 0100011 @s
 159addiw    ............   ..... 000 ..... 0011011 @i
 160slliw    0000000 .....  ..... 001 ..... 0011011 @sh5
 161srliw    0000000 .....  ..... 101 ..... 0011011 @sh5
 162sraiw    0100000 .....  ..... 101 ..... 0011011 @sh5
 163addw     0000000 .....  ..... 000 ..... 0111011 @r
 164subw     0100000 .....  ..... 000 ..... 0111011 @r
 165sllw     0000000 .....  ..... 001 ..... 0111011 @r
 166srlw     0000000 .....  ..... 101 ..... 0111011 @r
 167sraw     0100000 .....  ..... 101 ..... 0111011 @r
 168
 169# *** RV128I Base Instruction Set (in addition to RV64I) ***
 170ldu      ............   ..... 111 ..... 0000011 @i
 171lq       ............   ..... 010 ..... 0001111 @i
 172sq       ............   ..... 100 ..... 0100011 @s
 173addid    ............  .....  000 ..... 1011011 @i
 174sllid    000000 ......  ..... 001 ..... 1011011 @sh6
 175srlid    000000 ......  ..... 101 ..... 1011011 @sh6
 176sraid    010000 ......  ..... 101 ..... 1011011 @sh6
 177addd     0000000 ..... .....  000 ..... 1111011 @r
 178subd     0100000 ..... .....  000 ..... 1111011 @r
 179slld     0000000 ..... .....  001 ..... 1111011 @r
 180srld     0000000 ..... .....  101 ..... 1111011 @r
 181srad     0100000 ..... .....  101 ..... 1111011 @r
 182
 183# *** RV32M Standard Extension ***
 184mul      0000001 .....  ..... 000 ..... 0110011 @r
 185mulh     0000001 .....  ..... 001 ..... 0110011 @r
 186mulhsu   0000001 .....  ..... 010 ..... 0110011 @r
 187mulhu    0000001 .....  ..... 011 ..... 0110011 @r
 188div      0000001 .....  ..... 100 ..... 0110011 @r
 189divu     0000001 .....  ..... 101 ..... 0110011 @r
 190rem      0000001 .....  ..... 110 ..... 0110011 @r
 191remu     0000001 .....  ..... 111 ..... 0110011 @r
 192
 193# *** RV64M Standard Extension (in addition to RV32M) ***
 194mulw     0000001 .....  ..... 000 ..... 0111011 @r
 195divw     0000001 .....  ..... 100 ..... 0111011 @r
 196divuw    0000001 .....  ..... 101 ..... 0111011 @r
 197remw     0000001 .....  ..... 110 ..... 0111011 @r
 198remuw    0000001 .....  ..... 111 ..... 0111011 @r
 199
 200# *** RV128M Standard Extension (in addition to RV64M) ***
 201muld     0000001 .....  ..... 000 ..... 1111011 @r
 202divd     0000001 .....  ..... 100 ..... 1111011 @r
 203divud    0000001 .....  ..... 101 ..... 1111011 @r
 204remd     0000001 .....  ..... 110 ..... 1111011 @r
 205remud    0000001 .....  ..... 111 ..... 1111011 @r
 206
 207# *** RV32A Standard Extension ***
 208lr_w       00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
 209sc_w       00011 . . ..... ..... 010 ..... 0101111 @atom_st
 210amoswap_w  00001 . . ..... ..... 010 ..... 0101111 @atom_st
 211amoadd_w   00000 . . ..... ..... 010 ..... 0101111 @atom_st
 212amoxor_w   00100 . . ..... ..... 010 ..... 0101111 @atom_st
 213amoand_w   01100 . . ..... ..... 010 ..... 0101111 @atom_st
 214amoor_w    01000 . . ..... ..... 010 ..... 0101111 @atom_st
 215amomin_w   10000 . . ..... ..... 010 ..... 0101111 @atom_st
 216amomax_w   10100 . . ..... ..... 010 ..... 0101111 @atom_st
 217amominu_w  11000 . . ..... ..... 010 ..... 0101111 @atom_st
 218amomaxu_w  11100 . . ..... ..... 010 ..... 0101111 @atom_st
 219
 220# *** RV64A Standard Extension (in addition to RV32A) ***
 221lr_d       00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
 222sc_d       00011 . . ..... ..... 011 ..... 0101111 @atom_st
 223amoswap_d  00001 . . ..... ..... 011 ..... 0101111 @atom_st
 224amoadd_d   00000 . . ..... ..... 011 ..... 0101111 @atom_st
 225amoxor_d   00100 . . ..... ..... 011 ..... 0101111 @atom_st
 226amoand_d   01100 . . ..... ..... 011 ..... 0101111 @atom_st
 227amoor_d    01000 . . ..... ..... 011 ..... 0101111 @atom_st
 228amomin_d   10000 . . ..... ..... 011 ..... 0101111 @atom_st
 229amomax_d   10100 . . ..... ..... 011 ..... 0101111 @atom_st
 230amominu_d  11000 . . ..... ..... 011 ..... 0101111 @atom_st
 231amomaxu_d  11100 . . ..... ..... 011 ..... 0101111 @atom_st
 232
 233# *** RV32F Standard Extension ***
 234flw        ............   ..... 010 ..... 0000111 @i
 235fsw        .......  ..... ..... 010 ..... 0100111 @s
 236fmadd_s    ..... 00 ..... ..... ... ..... 1000011 @r4_rm
 237fmsub_s    ..... 00 ..... ..... ... ..... 1000111 @r4_rm
 238fnmsub_s   ..... 00 ..... ..... ... ..... 1001011 @r4_rm
 239fnmadd_s   ..... 00 ..... ..... ... ..... 1001111 @r4_rm
 240fadd_s     0000000  ..... ..... ... ..... 1010011 @r_rm
 241fsub_s     0000100  ..... ..... ... ..... 1010011 @r_rm
 242fmul_s     0001000  ..... ..... ... ..... 1010011 @r_rm
 243fdiv_s     0001100  ..... ..... ... ..... 1010011 @r_rm
 244fsqrt_s    0101100  00000 ..... ... ..... 1010011 @r2_rm
 245fsgnj_s    0010000  ..... ..... 000 ..... 1010011 @r
 246fsgnjn_s   0010000  ..... ..... 001 ..... 1010011 @r
 247fsgnjx_s   0010000  ..... ..... 010 ..... 1010011 @r
 248fmin_s     0010100  ..... ..... 000 ..... 1010011 @r
 249fmax_s     0010100  ..... ..... 001 ..... 1010011 @r
 250fcvt_w_s   1100000  00000 ..... ... ..... 1010011 @r2_rm
 251fcvt_wu_s  1100000  00001 ..... ... ..... 1010011 @r2_rm
 252fmv_x_w    1110000  00000 ..... 000 ..... 1010011 @r2
 253feq_s      1010000  ..... ..... 010 ..... 1010011 @r
 254flt_s      1010000  ..... ..... 001 ..... 1010011 @r
 255fle_s      1010000  ..... ..... 000 ..... 1010011 @r
 256fclass_s   1110000  00000 ..... 001 ..... 1010011 @r2
 257fcvt_s_w   1101000  00000 ..... ... ..... 1010011 @r2_rm
 258fcvt_s_wu  1101000  00001 ..... ... ..... 1010011 @r2_rm
 259fmv_w_x    1111000  00000 ..... 000 ..... 1010011 @r2
 260
 261# *** RV64F Standard Extension (in addition to RV32F) ***
 262fcvt_l_s   1100000  00010 ..... ... ..... 1010011 @r2_rm
 263fcvt_lu_s  1100000  00011 ..... ... ..... 1010011 @r2_rm
 264fcvt_s_l   1101000  00010 ..... ... ..... 1010011 @r2_rm
 265fcvt_s_lu  1101000  00011 ..... ... ..... 1010011 @r2_rm
 266
 267# *** RV32D Standard Extension ***
 268fld        ............   ..... 011 ..... 0000111 @i
 269fsd        ....... .....  ..... 011 ..... 0100111 @s
 270fmadd_d    ..... 01 ..... ..... ... ..... 1000011 @r4_rm
 271fmsub_d    ..... 01 ..... ..... ... ..... 1000111 @r4_rm
 272fnmsub_d   ..... 01 ..... ..... ... ..... 1001011 @r4_rm
 273fnmadd_d   ..... 01 ..... ..... ... ..... 1001111 @r4_rm
 274fadd_d     0000001  ..... ..... ... ..... 1010011 @r_rm
 275fsub_d     0000101  ..... ..... ... ..... 1010011 @r_rm
 276fmul_d     0001001  ..... ..... ... ..... 1010011 @r_rm
 277fdiv_d     0001101  ..... ..... ... ..... 1010011 @r_rm
 278fsqrt_d    0101101  00000 ..... ... ..... 1010011 @r2_rm
 279fsgnj_d    0010001  ..... ..... 000 ..... 1010011 @r
 280fsgnjn_d   0010001  ..... ..... 001 ..... 1010011 @r
 281fsgnjx_d   0010001  ..... ..... 010 ..... 1010011 @r
 282fmin_d     0010101  ..... ..... 000 ..... 1010011 @r
 283fmax_d     0010101  ..... ..... 001 ..... 1010011 @r
 284fcvt_s_d   0100000  00001 ..... ... ..... 1010011 @r2_rm
 285fcvt_d_s   0100001  00000 ..... ... ..... 1010011 @r2_rm
 286feq_d      1010001  ..... ..... 010 ..... 1010011 @r
 287flt_d      1010001  ..... ..... 001 ..... 1010011 @r
 288fle_d      1010001  ..... ..... 000 ..... 1010011 @r
 289fclass_d   1110001  00000 ..... 001 ..... 1010011 @r2
 290fcvt_w_d   1100001  00000 ..... ... ..... 1010011 @r2_rm
 291fcvt_wu_d  1100001  00001 ..... ... ..... 1010011 @r2_rm
 292fcvt_d_w   1101001  00000 ..... ... ..... 1010011 @r2_rm
 293fcvt_d_wu  1101001  00001 ..... ... ..... 1010011 @r2_rm
 294
 295# *** RV64D Standard Extension (in addition to RV32D) ***
 296fcvt_l_d   1100001  00010 ..... ... ..... 1010011 @r2_rm
 297fcvt_lu_d  1100001  00011 ..... ... ..... 1010011 @r2_rm
 298fmv_x_d    1110001  00000 ..... 000 ..... 1010011 @r2
 299fcvt_d_l   1101001  00010 ..... ... ..... 1010011 @r2_rm
 300fcvt_d_lu  1101001  00011 ..... ... ..... 1010011 @r2_rm
 301fmv_d_x    1111001  00000 ..... 000 ..... 1010011 @r2
 302
 303# *** RV32H Base Instruction Set ***
 304hlv_b       0110000  00000  ..... 100 ..... 1110011 @r2
 305hlv_bu      0110000  00001  ..... 100 ..... 1110011 @r2
 306hlv_h       0110010  00000  ..... 100 ..... 1110011 @r2
 307hlv_hu      0110010  00001  ..... 100 ..... 1110011 @r2
 308hlvx_hu     0110010  00011  ..... 100 ..... 1110011 @r2
 309hlv_w       0110100  00000  ..... 100 ..... 1110011 @r2
 310hlvx_wu     0110100  00011  ..... 100 ..... 1110011 @r2
 311hsv_b       0110001  .....  ..... 100 00000 1110011 @r2_s
 312hsv_h       0110011  .....  ..... 100 00000 1110011 @r2_s
 313hsv_w       0110101  .....  ..... 100 00000 1110011 @r2_s
 314hfence_gvma 0110001  .....  ..... 000 00000 1110011 @hfence_gvma
 315hfence_vvma 0010001  .....  ..... 000 00000 1110011 @hfence_vvma
 316
 317# *** RV64H Base Instruction Set ***
 318hlv_wu    0110100  00001   ..... 100 ..... 1110011 @r2
 319hlv_d     0110110  00000   ..... 100 ..... 1110011 @r2
 320hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
 321
 322# *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
 323# Vector unit-stride load/store insns.
 324vle8_v     ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
 325vle16_v    ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
 326vle32_v    ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
 327vle64_v    ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
 328vse8_v     ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
 329vse16_v    ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
 330vse32_v    ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
 331vse64_v    ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
 332
 333# Vector unit-stride mask load/store insns.
 334vlm_v      000 000 1 01011 ..... 000 ..... 0000111 @r2
 335vsm_v      000 000 1 01011 ..... 000 ..... 0100111 @r2
 336
 337# Vector strided insns.
 338vlse8_v     ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
 339vlse16_v    ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
 340vlse32_v    ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
 341vlse64_v    ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
 342vsse8_v     ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
 343vsse16_v    ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
 344vsse32_v    ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
 345vsse64_v    ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
 346
 347# Vector ordered-indexed and unordered-indexed load insns.
 348vlxei8_v      ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm
 349vlxei16_v     ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm
 350vlxei32_v     ... 0-1 . ..... ..... 110 ..... 0000111 @r_nfvm
 351vlxei64_v     ... 0-1 . ..... ..... 111 ..... 0000111 @r_nfvm
 352
 353# Vector ordered-indexed and unordered-indexed store insns.
 354vsxei8_v      ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm
 355vsxei16_v     ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm
 356vsxei32_v     ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm
 357vsxei64_v     ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm
 358
 359# Vector unit-stride fault-only-first load insns.
 360vle8ff_v      ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
 361vle16ff_v     ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
 362vle32ff_v     ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
 363vle64ff_v     ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
 364
 365# Vector whole register insns
 366vl1re8_v      000 000 1 01000 ..... 000 ..... 0000111 @r2
 367vl1re16_v     000 000 1 01000 ..... 101 ..... 0000111 @r2
 368vl1re32_v     000 000 1 01000 ..... 110 ..... 0000111 @r2
 369vl1re64_v     000 000 1 01000 ..... 111 ..... 0000111 @r2
 370vl2re8_v      001 000 1 01000 ..... 000 ..... 0000111 @r2
 371vl2re16_v     001 000 1 01000 ..... 101 ..... 0000111 @r2
 372vl2re32_v     001 000 1 01000 ..... 110 ..... 0000111 @r2
 373vl2re64_v     001 000 1 01000 ..... 111 ..... 0000111 @r2
 374vl4re8_v      011 000 1 01000 ..... 000 ..... 0000111 @r2
 375vl4re16_v     011 000 1 01000 ..... 101 ..... 0000111 @r2
 376vl4re32_v     011 000 1 01000 ..... 110 ..... 0000111 @r2
 377vl4re64_v     011 000 1 01000 ..... 111 ..... 0000111 @r2
 378vl8re8_v      111 000 1 01000 ..... 000 ..... 0000111 @r2
 379vl8re16_v     111 000 1 01000 ..... 101 ..... 0000111 @r2
 380vl8re32_v     111 000 1 01000 ..... 110 ..... 0000111 @r2
 381vl8re64_v     111 000 1 01000 ..... 111 ..... 0000111 @r2
 382vs1r_v        000 000 1 01000 ..... 000 ..... 0100111 @r2
 383vs2r_v        001 000 1 01000 ..... 000 ..... 0100111 @r2
 384vs4r_v        011 000 1 01000 ..... 000 ..... 0100111 @r2
 385vs8r_v        111 000 1 01000 ..... 000 ..... 0100111 @r2
 386
 387# *** new major opcode OP-V ***
 388vadd_vv         000000 . ..... ..... 000 ..... 1010111 @r_vm
 389vadd_vx         000000 . ..... ..... 100 ..... 1010111 @r_vm
 390vadd_vi         000000 . ..... ..... 011 ..... 1010111 @r_vm
 391vsub_vv         000010 . ..... ..... 000 ..... 1010111 @r_vm
 392vsub_vx         000010 . ..... ..... 100 ..... 1010111 @r_vm
 393vrsub_vx        000011 . ..... ..... 100 ..... 1010111 @r_vm
 394vrsub_vi        000011 . ..... ..... 011 ..... 1010111 @r_vm
 395vwaddu_vv       110000 . ..... ..... 010 ..... 1010111 @r_vm
 396vwaddu_vx       110000 . ..... ..... 110 ..... 1010111 @r_vm
 397vwadd_vv        110001 . ..... ..... 010 ..... 1010111 @r_vm
 398vwadd_vx        110001 . ..... ..... 110 ..... 1010111 @r_vm
 399vwsubu_vv       110010 . ..... ..... 010 ..... 1010111 @r_vm
 400vwsubu_vx       110010 . ..... ..... 110 ..... 1010111 @r_vm
 401vwsub_vv        110011 . ..... ..... 010 ..... 1010111 @r_vm
 402vwsub_vx        110011 . ..... ..... 110 ..... 1010111 @r_vm
 403vwaddu_wv       110100 . ..... ..... 010 ..... 1010111 @r_vm
 404vwaddu_wx       110100 . ..... ..... 110 ..... 1010111 @r_vm
 405vwadd_wv        110101 . ..... ..... 010 ..... 1010111 @r_vm
 406vwadd_wx        110101 . ..... ..... 110 ..... 1010111 @r_vm
 407vwsubu_wv       110110 . ..... ..... 010 ..... 1010111 @r_vm
 408vwsubu_wx       110110 . ..... ..... 110 ..... 1010111 @r_vm
 409vwsub_wv        110111 . ..... ..... 010 ..... 1010111 @r_vm
 410vwsub_wx        110111 . ..... ..... 110 ..... 1010111 @r_vm
 411vadc_vvm        010000 0 ..... ..... 000 ..... 1010111 @r_vm_1
 412vadc_vxm        010000 0 ..... ..... 100 ..... 1010111 @r_vm_1
 413vadc_vim        010000 0 ..... ..... 011 ..... 1010111 @r_vm_1
 414vmadc_vvm       010001 . ..... ..... 000 ..... 1010111 @r_vm
 415vmadc_vxm       010001 . ..... ..... 100 ..... 1010111 @r_vm
 416vmadc_vim       010001 . ..... ..... 011 ..... 1010111 @r_vm
 417vsbc_vvm        010010 0 ..... ..... 000 ..... 1010111 @r_vm_1
 418vsbc_vxm        010010 0 ..... ..... 100 ..... 1010111 @r_vm_1
 419vmsbc_vvm       010011 . ..... ..... 000 ..... 1010111 @r_vm
 420vmsbc_vxm       010011 . ..... ..... 100 ..... 1010111 @r_vm
 421vand_vv         001001 . ..... ..... 000 ..... 1010111 @r_vm
 422vand_vx         001001 . ..... ..... 100 ..... 1010111 @r_vm
 423vand_vi         001001 . ..... ..... 011 ..... 1010111 @r_vm
 424vor_vv          001010 . ..... ..... 000 ..... 1010111 @r_vm
 425vor_vx          001010 . ..... ..... 100 ..... 1010111 @r_vm
 426vor_vi          001010 . ..... ..... 011 ..... 1010111 @r_vm
 427vxor_vv         001011 . ..... ..... 000 ..... 1010111 @r_vm
 428vxor_vx         001011 . ..... ..... 100 ..... 1010111 @r_vm
 429vxor_vi         001011 . ..... ..... 011 ..... 1010111 @r_vm
 430vsll_vv         100101 . ..... ..... 000 ..... 1010111 @r_vm
 431vsll_vx         100101 . ..... ..... 100 ..... 1010111 @r_vm
 432vsll_vi         100101 . ..... ..... 011 ..... 1010111 @r_vm
 433vsrl_vv         101000 . ..... ..... 000 ..... 1010111 @r_vm
 434vsrl_vx         101000 . ..... ..... 100 ..... 1010111 @r_vm
 435vsrl_vi         101000 . ..... ..... 011 ..... 1010111 @r_vm
 436vsra_vv         101001 . ..... ..... 000 ..... 1010111 @r_vm
 437vsra_vx         101001 . ..... ..... 100 ..... 1010111 @r_vm
 438vsra_vi         101001 . ..... ..... 011 ..... 1010111 @r_vm
 439vnsrl_wv        101100 . ..... ..... 000 ..... 1010111 @r_vm
 440vnsrl_wx        101100 . ..... ..... 100 ..... 1010111 @r_vm
 441vnsrl_wi        101100 . ..... ..... 011 ..... 1010111 @r_vm
 442vnsra_wv        101101 . ..... ..... 000 ..... 1010111 @r_vm
 443vnsra_wx        101101 . ..... ..... 100 ..... 1010111 @r_vm
 444vnsra_wi        101101 . ..... ..... 011 ..... 1010111 @r_vm
 445vmseq_vv        011000 . ..... ..... 000 ..... 1010111 @r_vm
 446vmseq_vx        011000 . ..... ..... 100 ..... 1010111 @r_vm
 447vmseq_vi        011000 . ..... ..... 011 ..... 1010111 @r_vm
 448vmsne_vv        011001 . ..... ..... 000 ..... 1010111 @r_vm
 449vmsne_vx        011001 . ..... ..... 100 ..... 1010111 @r_vm
 450vmsne_vi        011001 . ..... ..... 011 ..... 1010111 @r_vm
 451vmsltu_vv       011010 . ..... ..... 000 ..... 1010111 @r_vm
 452vmsltu_vx       011010 . ..... ..... 100 ..... 1010111 @r_vm
 453vmslt_vv        011011 . ..... ..... 000 ..... 1010111 @r_vm
 454vmslt_vx        011011 . ..... ..... 100 ..... 1010111 @r_vm
 455vmsleu_vv       011100 . ..... ..... 000 ..... 1010111 @r_vm
 456vmsleu_vx       011100 . ..... ..... 100 ..... 1010111 @r_vm
 457vmsleu_vi       011100 . ..... ..... 011 ..... 1010111 @r_vm
 458vmsle_vv        011101 . ..... ..... 000 ..... 1010111 @r_vm
 459vmsle_vx        011101 . ..... ..... 100 ..... 1010111 @r_vm
 460vmsle_vi        011101 . ..... ..... 011 ..... 1010111 @r_vm
 461vmsgtu_vx       011110 . ..... ..... 100 ..... 1010111 @r_vm
 462vmsgtu_vi       011110 . ..... ..... 011 ..... 1010111 @r_vm
 463vmsgt_vx        011111 . ..... ..... 100 ..... 1010111 @r_vm
 464vmsgt_vi        011111 . ..... ..... 011 ..... 1010111 @r_vm
 465vminu_vv        000100 . ..... ..... 000 ..... 1010111 @r_vm
 466vminu_vx        000100 . ..... ..... 100 ..... 1010111 @r_vm
 467vmin_vv         000101 . ..... ..... 000 ..... 1010111 @r_vm
 468vmin_vx         000101 . ..... ..... 100 ..... 1010111 @r_vm
 469vmaxu_vv        000110 . ..... ..... 000 ..... 1010111 @r_vm
 470vmaxu_vx        000110 . ..... ..... 100 ..... 1010111 @r_vm
 471vmax_vv         000111 . ..... ..... 000 ..... 1010111 @r_vm
 472vmax_vx         000111 . ..... ..... 100 ..... 1010111 @r_vm
 473vmul_vv         100101 . ..... ..... 010 ..... 1010111 @r_vm
 474vmul_vx         100101 . ..... ..... 110 ..... 1010111 @r_vm
 475vmulh_vv        100111 . ..... ..... 010 ..... 1010111 @r_vm
 476vmulh_vx        100111 . ..... ..... 110 ..... 1010111 @r_vm
 477vmulhu_vv       100100 . ..... ..... 010 ..... 1010111 @r_vm
 478vmulhu_vx       100100 . ..... ..... 110 ..... 1010111 @r_vm
 479vmulhsu_vv      100110 . ..... ..... 010 ..... 1010111 @r_vm
 480vmulhsu_vx      100110 . ..... ..... 110 ..... 1010111 @r_vm
 481vdivu_vv        100000 . ..... ..... 010 ..... 1010111 @r_vm
 482vdivu_vx        100000 . ..... ..... 110 ..... 1010111 @r_vm
 483vdiv_vv         100001 . ..... ..... 010 ..... 1010111 @r_vm
 484vdiv_vx         100001 . ..... ..... 110 ..... 1010111 @r_vm
 485vremu_vv        100010 . ..... ..... 010 ..... 1010111 @r_vm
 486vremu_vx        100010 . ..... ..... 110 ..... 1010111 @r_vm
 487vrem_vv         100011 . ..... ..... 010 ..... 1010111 @r_vm
 488vrem_vx         100011 . ..... ..... 110 ..... 1010111 @r_vm
 489vwmulu_vv       111000 . ..... ..... 010 ..... 1010111 @r_vm
 490vwmulu_vx       111000 . ..... ..... 110 ..... 1010111 @r_vm
 491vwmulsu_vv      111010 . ..... ..... 010 ..... 1010111 @r_vm
 492vwmulsu_vx      111010 . ..... ..... 110 ..... 1010111 @r_vm
 493vwmul_vv        111011 . ..... ..... 010 ..... 1010111 @r_vm
 494vwmul_vx        111011 . ..... ..... 110 ..... 1010111 @r_vm
 495vmacc_vv        101101 . ..... ..... 010 ..... 1010111 @r_vm
 496vmacc_vx        101101 . ..... ..... 110 ..... 1010111 @r_vm
 497vnmsac_vv       101111 . ..... ..... 010 ..... 1010111 @r_vm
 498vnmsac_vx       101111 . ..... ..... 110 ..... 1010111 @r_vm
 499vmadd_vv        101001 . ..... ..... 010 ..... 1010111 @r_vm
 500vmadd_vx        101001 . ..... ..... 110 ..... 1010111 @r_vm
 501vnmsub_vv       101011 . ..... ..... 010 ..... 1010111 @r_vm
 502vnmsub_vx       101011 . ..... ..... 110 ..... 1010111 @r_vm
 503vwmaccu_vv      111100 . ..... ..... 010 ..... 1010111 @r_vm
 504vwmaccu_vx      111100 . ..... ..... 110 ..... 1010111 @r_vm
 505vwmacc_vv       111101 . ..... ..... 010 ..... 1010111 @r_vm
 506vwmacc_vx       111101 . ..... ..... 110 ..... 1010111 @r_vm
 507vwmaccsu_vv     111111 . ..... ..... 010 ..... 1010111 @r_vm
 508vwmaccsu_vx     111111 . ..... ..... 110 ..... 1010111 @r_vm
 509vwmaccus_vx     111110 . ..... ..... 110 ..... 1010111 @r_vm
 510vmv_v_v         010111 1 00000 ..... 000 ..... 1010111 @r2
 511vmv_v_x         010111 1 00000 ..... 100 ..... 1010111 @r2
 512vmv_v_i         010111 1 00000 ..... 011 ..... 1010111 @r2
 513vmerge_vvm      010111 0 ..... ..... 000 ..... 1010111 @r_vm_0
 514vmerge_vxm      010111 0 ..... ..... 100 ..... 1010111 @r_vm_0
 515vmerge_vim      010111 0 ..... ..... 011 ..... 1010111 @r_vm_0
 516vsaddu_vv       100000 . ..... ..... 000 ..... 1010111 @r_vm
 517vsaddu_vx       100000 . ..... ..... 100 ..... 1010111 @r_vm
 518vsaddu_vi       100000 . ..... ..... 011 ..... 1010111 @r_vm
 519vsadd_vv        100001 . ..... ..... 000 ..... 1010111 @r_vm
 520vsadd_vx        100001 . ..... ..... 100 ..... 1010111 @r_vm
 521vsadd_vi        100001 . ..... ..... 011 ..... 1010111 @r_vm
 522vssubu_vv       100010 . ..... ..... 000 ..... 1010111 @r_vm
 523vssubu_vx       100010 . ..... ..... 100 ..... 1010111 @r_vm
 524vssub_vv        100011 . ..... ..... 000 ..... 1010111 @r_vm
 525vssub_vx        100011 . ..... ..... 100 ..... 1010111 @r_vm
 526vaadd_vv        001001 . ..... ..... 010 ..... 1010111 @r_vm
 527vaadd_vx        001001 . ..... ..... 110 ..... 1010111 @r_vm
 528vaaddu_vv       001000 . ..... ..... 010 ..... 1010111 @r_vm
 529vaaddu_vx       001000 . ..... ..... 110 ..... 1010111 @r_vm
 530vasub_vv        001011 . ..... ..... 010 ..... 1010111 @r_vm
 531vasub_vx        001011 . ..... ..... 110 ..... 1010111 @r_vm
 532vasubu_vv       001010 . ..... ..... 010 ..... 1010111 @r_vm
 533vasubu_vx       001010 . ..... ..... 110 ..... 1010111 @r_vm
 534vsmul_vv        100111 . ..... ..... 000 ..... 1010111 @r_vm
 535vsmul_vx        100111 . ..... ..... 100 ..... 1010111 @r_vm
 536vssrl_vv        101010 . ..... ..... 000 ..... 1010111 @r_vm
 537vssrl_vx        101010 . ..... ..... 100 ..... 1010111 @r_vm
 538vssrl_vi        101010 . ..... ..... 011 ..... 1010111 @r_vm
 539vssra_vv        101011 . ..... ..... 000 ..... 1010111 @r_vm
 540vssra_vx        101011 . ..... ..... 100 ..... 1010111 @r_vm
 541vssra_vi        101011 . ..... ..... 011 ..... 1010111 @r_vm
 542vnclipu_wv      101110 . ..... ..... 000 ..... 1010111 @r_vm
 543vnclipu_wx      101110 . ..... ..... 100 ..... 1010111 @r_vm
 544vnclipu_wi      101110 . ..... ..... 011 ..... 1010111 @r_vm
 545vnclip_wv       101111 . ..... ..... 000 ..... 1010111 @r_vm
 546vnclip_wx       101111 . ..... ..... 100 ..... 1010111 @r_vm
 547vnclip_wi       101111 . ..... ..... 011 ..... 1010111 @r_vm
 548vfadd_vv        000000 . ..... ..... 001 ..... 1010111 @r_vm
 549vfadd_vf        000000 . ..... ..... 101 ..... 1010111 @r_vm
 550vfsub_vv        000010 . ..... ..... 001 ..... 1010111 @r_vm
 551vfsub_vf        000010 . ..... ..... 101 ..... 1010111 @r_vm
 552vfrsub_vf       100111 . ..... ..... 101 ..... 1010111 @r_vm
 553vfwadd_vv       110000 . ..... ..... 001 ..... 1010111 @r_vm
 554vfwadd_vf       110000 . ..... ..... 101 ..... 1010111 @r_vm
 555vfwadd_wv       110100 . ..... ..... 001 ..... 1010111 @r_vm
 556vfwadd_wf       110100 . ..... ..... 101 ..... 1010111 @r_vm
 557vfwsub_vv       110010 . ..... ..... 001 ..... 1010111 @r_vm
 558vfwsub_vf       110010 . ..... ..... 101 ..... 1010111 @r_vm
 559vfwsub_wv       110110 . ..... ..... 001 ..... 1010111 @r_vm
 560vfwsub_wf       110110 . ..... ..... 101 ..... 1010111 @r_vm
 561vfmul_vv        100100 . ..... ..... 001 ..... 1010111 @r_vm
 562vfmul_vf        100100 . ..... ..... 101 ..... 1010111 @r_vm
 563vfdiv_vv        100000 . ..... ..... 001 ..... 1010111 @r_vm
 564vfdiv_vf        100000 . ..... ..... 101 ..... 1010111 @r_vm
 565vfrdiv_vf       100001 . ..... ..... 101 ..... 1010111 @r_vm
 566vfwmul_vv       111000 . ..... ..... 001 ..... 1010111 @r_vm
 567vfwmul_vf       111000 . ..... ..... 101 ..... 1010111 @r_vm
 568vfmacc_vv       101100 . ..... ..... 001 ..... 1010111 @r_vm
 569vfnmacc_vv      101101 . ..... ..... 001 ..... 1010111 @r_vm
 570vfnmacc_vf      101101 . ..... ..... 101 ..... 1010111 @r_vm
 571vfmacc_vf       101100 . ..... ..... 101 ..... 1010111 @r_vm
 572vfmsac_vv       101110 . ..... ..... 001 ..... 1010111 @r_vm
 573vfmsac_vf       101110 . ..... ..... 101 ..... 1010111 @r_vm
 574vfnmsac_vv      101111 . ..... ..... 001 ..... 1010111 @r_vm
 575vfnmsac_vf      101111 . ..... ..... 101 ..... 1010111 @r_vm
 576vfmadd_vv       101000 . ..... ..... 001 ..... 1010111 @r_vm
 577vfmadd_vf       101000 . ..... ..... 101 ..... 1010111 @r_vm
 578vfnmadd_vv      101001 . ..... ..... 001 ..... 1010111 @r_vm
 579vfnmadd_vf      101001 . ..... ..... 101 ..... 1010111 @r_vm
 580vfmsub_vv       101010 . ..... ..... 001 ..... 1010111 @r_vm
 581vfmsub_vf       101010 . ..... ..... 101 ..... 1010111 @r_vm
 582vfnmsub_vv      101011 . ..... ..... 001 ..... 1010111 @r_vm
 583vfnmsub_vf      101011 . ..... ..... 101 ..... 1010111 @r_vm
 584vfwmacc_vv      111100 . ..... ..... 001 ..... 1010111 @r_vm
 585vfwmacc_vf      111100 . ..... ..... 101 ..... 1010111 @r_vm
 586vfwnmacc_vv     111101 . ..... ..... 001 ..... 1010111 @r_vm
 587vfwnmacc_vf     111101 . ..... ..... 101 ..... 1010111 @r_vm
 588vfwmsac_vv      111110 . ..... ..... 001 ..... 1010111 @r_vm
 589vfwmsac_vf      111110 . ..... ..... 101 ..... 1010111 @r_vm
 590vfwnmsac_vv     111111 . ..... ..... 001 ..... 1010111 @r_vm
 591vfwnmsac_vf     111111 . ..... ..... 101 ..... 1010111 @r_vm
 592vfsqrt_v        010011 . ..... 00000 001 ..... 1010111 @r2_vm
 593vfrsqrt7_v      010011 . ..... 00100 001 ..... 1010111 @r2_vm
 594vfrec7_v        010011 . ..... 00101 001 ..... 1010111 @r2_vm
 595vfmin_vv        000100 . ..... ..... 001 ..... 1010111 @r_vm
 596vfmin_vf        000100 . ..... ..... 101 ..... 1010111 @r_vm
 597vfmax_vv        000110 . ..... ..... 001 ..... 1010111 @r_vm
 598vfmax_vf        000110 . ..... ..... 101 ..... 1010111 @r_vm
 599vfsgnj_vv       001000 . ..... ..... 001 ..... 1010111 @r_vm
 600vfsgnj_vf       001000 . ..... ..... 101 ..... 1010111 @r_vm
 601vfsgnjn_vv      001001 . ..... ..... 001 ..... 1010111 @r_vm
 602vfsgnjn_vf      001001 . ..... ..... 101 ..... 1010111 @r_vm
 603vfsgnjx_vv      001010 . ..... ..... 001 ..... 1010111 @r_vm
 604vfsgnjx_vf      001010 . ..... ..... 101 ..... 1010111 @r_vm
 605vfslide1up_vf   001110 . ..... ..... 101 ..... 1010111 @r_vm
 606vfslide1down_vf 001111 . ..... ..... 101 ..... 1010111 @r_vm
 607vmfeq_vv        011000 . ..... ..... 001 ..... 1010111 @r_vm
 608vmfeq_vf        011000 . ..... ..... 101 ..... 1010111 @r_vm
 609vmfne_vv        011100 . ..... ..... 001 ..... 1010111 @r_vm
 610vmfne_vf        011100 . ..... ..... 101 ..... 1010111 @r_vm
 611vmflt_vv        011011 . ..... ..... 001 ..... 1010111 @r_vm
 612vmflt_vf        011011 . ..... ..... 101 ..... 1010111 @r_vm
 613vmfle_vv        011001 . ..... ..... 001 ..... 1010111 @r_vm
 614vmfle_vf        011001 . ..... ..... 101 ..... 1010111 @r_vm
 615vmfgt_vf        011101 . ..... ..... 101 ..... 1010111 @r_vm
 616vmfge_vf        011111 . ..... ..... 101 ..... 1010111 @r_vm
 617vfclass_v       010011 . ..... 10000 001 ..... 1010111 @r2_vm
 618vfmerge_vfm     010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
 619vfmv_v_f        010111 1 00000 ..... 101 ..... 1010111 @r2
 620
 621vfcvt_xu_f_v       010010 . ..... 00000 001 ..... 1010111 @r2_vm
 622vfcvt_x_f_v        010010 . ..... 00001 001 ..... 1010111 @r2_vm
 623vfcvt_f_xu_v       010010 . ..... 00010 001 ..... 1010111 @r2_vm
 624vfcvt_f_x_v        010010 . ..... 00011 001 ..... 1010111 @r2_vm
 625vfcvt_rtz_xu_f_v   010010 . ..... 00110 001 ..... 1010111 @r2_vm
 626vfcvt_rtz_x_f_v    010010 . ..... 00111 001 ..... 1010111 @r2_vm
 627
 628vfwcvt_xu_f_v      010010 . ..... 01000 001 ..... 1010111 @r2_vm
 629vfwcvt_x_f_v       010010 . ..... 01001 001 ..... 1010111 @r2_vm
 630vfwcvt_f_xu_v      010010 . ..... 01010 001 ..... 1010111 @r2_vm
 631vfwcvt_f_x_v       010010 . ..... 01011 001 ..... 1010111 @r2_vm
 632vfwcvt_f_f_v       010010 . ..... 01100 001 ..... 1010111 @r2_vm
 633vfwcvt_rtz_xu_f_v  010010 . ..... 01110 001 ..... 1010111 @r2_vm
 634vfwcvt_rtz_x_f_v   010010 . ..... 01111 001 ..... 1010111 @r2_vm
 635
 636vfncvt_xu_f_w      010010 . ..... 10000 001 ..... 1010111 @r2_vm
 637vfncvt_x_f_w       010010 . ..... 10001 001 ..... 1010111 @r2_vm
 638vfncvt_f_xu_w      010010 . ..... 10010 001 ..... 1010111 @r2_vm
 639vfncvt_f_x_w       010010 . ..... 10011 001 ..... 1010111 @r2_vm
 640vfncvt_f_f_w       010010 . ..... 10100 001 ..... 1010111 @r2_vm
 641vfncvt_rod_f_f_w   010010 . ..... 10101 001 ..... 1010111 @r2_vm
 642vfncvt_rtz_xu_f_w  010010 . ..... 10110 001 ..... 1010111 @r2_vm
 643vfncvt_rtz_x_f_w   010010 . ..... 10111 001 ..... 1010111 @r2_vm
 644
 645vredsum_vs      000000 . ..... ..... 010 ..... 1010111 @r_vm
 646vredand_vs      000001 . ..... ..... 010 ..... 1010111 @r_vm
 647vredor_vs       000010 . ..... ..... 010 ..... 1010111 @r_vm
 648vredxor_vs      000011 . ..... ..... 010 ..... 1010111 @r_vm
 649vredminu_vs     000100 . ..... ..... 010 ..... 1010111 @r_vm
 650vredmin_vs      000101 . ..... ..... 010 ..... 1010111 @r_vm
 651vredmaxu_vs     000110 . ..... ..... 010 ..... 1010111 @r_vm
 652vredmax_vs      000111 . ..... ..... 010 ..... 1010111 @r_vm
 653vwredsumu_vs    110000 . ..... ..... 000 ..... 1010111 @r_vm
 654vwredsum_vs     110001 . ..... ..... 000 ..... 1010111 @r_vm
 655# Vector ordered and unordered reduction sum
 656vfredsum_vs     0000-1 . ..... ..... 001 ..... 1010111 @r_vm
 657vfredmin_vs     000101 . ..... ..... 001 ..... 1010111 @r_vm
 658vfredmax_vs     000111 . ..... ..... 001 ..... 1010111 @r_vm
 659# Vector widening ordered and unordered float reduction sum
 660vfwredsum_vs    1100-1 . ..... ..... 001 ..... 1010111 @r_vm
 661vmand_mm        011001 - ..... ..... 010 ..... 1010111 @r
 662vmnand_mm       011101 - ..... ..... 010 ..... 1010111 @r
 663vmandn_mm       011000 - ..... ..... 010 ..... 1010111 @r
 664vmxor_mm        011011 - ..... ..... 010 ..... 1010111 @r
 665vmor_mm         011010 - ..... ..... 010 ..... 1010111 @r
 666vmnor_mm        011110 - ..... ..... 010 ..... 1010111 @r
 667vmorn_mm        011100 - ..... ..... 010 ..... 1010111 @r
 668vmxnor_mm       011111 - ..... ..... 010 ..... 1010111 @r
 669vcpop_m         010000 . ..... 10000 010 ..... 1010111 @r2_vm
 670vfirst_m        010000 . ..... 10001 010 ..... 1010111 @r2_vm
 671vmsbf_m         010100 . ..... 00001 010 ..... 1010111 @r2_vm
 672vmsif_m         010100 . ..... 00011 010 ..... 1010111 @r2_vm
 673vmsof_m         010100 . ..... 00010 010 ..... 1010111 @r2_vm
 674viota_m         010100 . ..... 10000 010 ..... 1010111 @r2_vm
 675vid_v           010100 . 00000 10001 010 ..... 1010111 @r1_vm
 676vmv_x_s         010000 1 ..... 00000 010 ..... 1010111 @r2rd
 677vmv_s_x         010000 1 00000 ..... 110 ..... 1010111 @r2
 678vfmv_f_s        010000 1 ..... 00000 001 ..... 1010111 @r2rd
 679vfmv_s_f        010000 1 00000 ..... 101 ..... 1010111 @r2
 680vslideup_vx     001110 . ..... ..... 100 ..... 1010111 @r_vm
 681vslideup_vi     001110 . ..... ..... 011 ..... 1010111 @r_vm
 682vslide1up_vx    001110 . ..... ..... 110 ..... 1010111 @r_vm
 683vslidedown_vx   001111 . ..... ..... 100 ..... 1010111 @r_vm
 684vslidedown_vi   001111 . ..... ..... 011 ..... 1010111 @r_vm
 685vslide1down_vx  001111 . ..... ..... 110 ..... 1010111 @r_vm
 686vrgather_vv     001100 . ..... ..... 000 ..... 1010111 @r_vm
 687vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm
 688vrgather_vx     001100 . ..... ..... 100 ..... 1010111 @r_vm
 689vrgather_vi     001100 . ..... ..... 011 ..... 1010111 @r_vm
 690vcompress_vm    010111 - ..... ..... 010 ..... 1010111 @r
 691vmv1r_v         100111 1 ..... 00000 011 ..... 1010111 @r2rd
 692vmv2r_v         100111 1 ..... 00001 011 ..... 1010111 @r2rd
 693vmv4r_v         100111 1 ..... 00011 011 ..... 1010111 @r2rd
 694vmv8r_v         100111 1 ..... 00111 011 ..... 1010111 @r2rd
 695
 696# Vector Integer Extension
 697vzext_vf2       010010 . ..... 00110 010 ..... 1010111 @r2_vm
 698vzext_vf4       010010 . ..... 00100 010 ..... 1010111 @r2_vm
 699vzext_vf8       010010 . ..... 00010 010 ..... 1010111 @r2_vm
 700vsext_vf2       010010 . ..... 00111 010 ..... 1010111 @r2_vm
 701vsext_vf4       010010 . ..... 00101 010 ..... 1010111 @r2_vm
 702vsext_vf8       010010 . ..... 00011 010 ..... 1010111 @r2_vm
 703
 704vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm11
 705vsetivli        11 .......... ..... 111 ..... 1010111  @r2_zimm10
 706vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
 707
 708# *** RV32 Zba Standard Extension ***
 709sh1add     0010000 .......... 010 ..... 0110011 @r
 710sh2add     0010000 .......... 100 ..... 0110011 @r
 711sh3add     0010000 .......... 110 ..... 0110011 @r
 712
 713# *** RV64 Zba Standard Extension (in addition to RV32 Zba) ***
 714add_uw     0000100 .......... 000 ..... 0111011 @r
 715sh1add_uw  0010000 .......... 010 ..... 0111011 @r
 716sh2add_uw  0010000 .......... 100 ..... 0111011 @r
 717sh3add_uw  0010000 .......... 110 ..... 0111011 @r
 718slli_uw    00001 ............ 001 ..... 0011011 @sh
 719
 720# *** RV32 Zbb Standard Extension ***
 721andn       0100000 .......... 111 ..... 0110011 @r
 722clz        011000 000000 ..... 001 ..... 0010011 @r2
 723cpop       011000 000010 ..... 001 ..... 0010011 @r2
 724ctz        011000 000001 ..... 001 ..... 0010011 @r2
 725max        0000101 .......... 110 ..... 0110011 @r
 726maxu       0000101 .......... 111 ..... 0110011 @r
 727min        0000101 .......... 100 ..... 0110011 @r
 728minu       0000101 .......... 101 ..... 0110011 @r
 729orc_b      001010 000111 ..... 101 ..... 0010011 @r2
 730orn        0100000 .......... 110 ..... 0110011 @r
 731# The encoding for rev8 differs between RV32 and RV64.
 732# rev8_32 denotes the RV32 variant.
 733rev8_32    011010 011000 ..... 101 ..... 0010011 @r2
 734rol        0110000 .......... 001 ..... 0110011 @r
 735ror        0110000 .......... 101 ..... 0110011 @r
 736rori       01100 ............ 101 ..... 0010011 @sh
 737sext_b     011000 000100 ..... 001 ..... 0010011 @r2
 738sext_h     011000 000101 ..... 001 ..... 0010011 @r2
 739xnor       0100000 .......... 100 ..... 0110011 @r
 740# The encoding for zext.h differs between RV32 and RV64.
 741# zext_h_32 denotes the RV32 variant.
 742zext_h_32  0000100 00000 ..... 100 ..... 0110011 @r2
 743
 744# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
 745clzw       0110000 00000 ..... 001 ..... 0011011 @r2
 746ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
 747cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
 748# The encoding for rev8 differs between RV32 and RV64.
 749# When executing on RV64, the encoding used in RV32 is an illegal
 750# instruction, so we use different handler functions to differentiate.
 751rev8_64    011010 111000 ..... 101 ..... 0010011 @r2
 752rolw       0110000 .......... 001 ..... 0111011 @r
 753roriw      0110000 .......... 101 ..... 0011011 @sh5
 754rorw       0110000 .......... 101 ..... 0111011 @r
 755# The encoding for zext.h differs between RV32 and RV64.
 756# When executing on RV64, the encoding used in RV32 is an illegal
 757# instruction, so we use different handler functions to differentiate.
 758zext_h_64  0000100 00000 ..... 100 ..... 0111011 @r2
 759
 760# *** RV32 Zbc Standard Extension ***
 761clmul      0000101 .......... 001 ..... 0110011 @r
 762clmulh     0000101 .......... 011 ..... 0110011 @r
 763clmulr     0000101 .......... 010 ..... 0110011 @r
 764
 765# *** RV32 Zbs Standard Extension ***
 766bclr       0100100 .......... 001 ..... 0110011 @r
 767bclri      01001. ........... 001 ..... 0010011 @sh
 768bext       0100100 .......... 101 ..... 0110011 @r
 769bexti      01001. ........... 101 ..... 0010011 @sh
 770binv       0110100 .......... 001 ..... 0110011 @r
 771binvi      01101. ........... 001 ..... 0010011 @sh
 772bset       0010100 .......... 001 ..... 0110011 @r
 773bseti      00101. ........... 001 ..... 0010011 @sh
 774
 775# *** RV32 Zfh Extension ***
 776flh        ............   ..... 001 ..... 0000111 @i
 777fsh        .......  ..... ..... 001 ..... 0100111 @s
 778fmadd_h    ..... 10 ..... ..... ... ..... 1000011 @r4_rm
 779fmsub_h    ..... 10 ..... ..... ... ..... 1000111 @r4_rm
 780fnmsub_h   ..... 10 ..... ..... ... ..... 1001011 @r4_rm
 781fnmadd_h   ..... 10 ..... ..... ... ..... 1001111 @r4_rm
 782fadd_h     0000010  ..... ..... ... ..... 1010011 @r_rm
 783fsub_h     0000110  ..... ..... ... ..... 1010011 @r_rm
 784fmul_h     0001010  ..... ..... ... ..... 1010011 @r_rm
 785fdiv_h     0001110  ..... ..... ... ..... 1010011 @r_rm
 786fsqrt_h    0101110  00000 ..... ... ..... 1010011 @r2_rm
 787fsgnj_h    0010010  ..... ..... 000 ..... 1010011 @r
 788fsgnjn_h   0010010  ..... ..... 001 ..... 1010011 @r
 789fsgnjx_h   0010010  ..... ..... 010 ..... 1010011 @r
 790fmin_h     0010110  ..... ..... 000 ..... 1010011 @r
 791fmax_h     0010110  ..... ..... 001 ..... 1010011 @r
 792fcvt_h_s   0100010  00000 ..... ... ..... 1010011 @r2_rm
 793fcvt_s_h   0100000  00010 ..... ... ..... 1010011 @r2_rm
 794fcvt_h_d   0100010  00001 ..... ... ..... 1010011 @r2_rm
 795fcvt_d_h   0100001  00010 ..... ... ..... 1010011 @r2_rm
 796fcvt_w_h   1100010  00000 ..... ... ..... 1010011 @r2_rm
 797fcvt_wu_h  1100010  00001 ..... ... ..... 1010011 @r2_rm
 798fmv_x_h    1110010  00000 ..... 000 ..... 1010011 @r2
 799feq_h      1010010  ..... ..... 010 ..... 1010011 @r
 800flt_h      1010010  ..... ..... 001 ..... 1010011 @r
 801fle_h      1010010  ..... ..... 000 ..... 1010011 @r
 802fclass_h   1110010  00000 ..... 001 ..... 1010011 @r2
 803fcvt_h_w   1101010  00000 ..... ... ..... 1010011 @r2_rm
 804fcvt_h_wu  1101010  00001 ..... ... ..... 1010011 @r2_rm
 805fmv_h_x    1111010  00000 ..... 000 ..... 1010011 @r2
 806
 807# *** RV64 Zfh Extension (in addition to RV32 Zfh) ***
 808fcvt_l_h   1100010  00010 ..... ... ..... 1010011 @r2_rm
 809fcvt_lu_h  1100010  00011 ..... ... ..... 1010011 @r2_rm
 810fcvt_h_l   1101010  00010 ..... ... ..... 1010011 @r2_rm
 811fcvt_h_lu  1101010  00011 ..... ... ..... 1010011 @r2_rm
 812
 813# *** Svinval Standard Extension ***
 814sinval_vma        0001011 ..... ..... 000 00000 1110011 @sfence_vma
 815sfence_w_inval    0001100 00000 00000 000 00000 1110011
 816sfence_inval_ir   0001100 00001 00000 000 00000 1110011
 817hinval_vvma       0010011 ..... ..... 000 00000 1110011 @hfence_vvma
 818hinval_gvma       0110011 ..... ..... 000 00000 1110011 @hfence_gvma
 819