LXR qemu/target/riscv/internals.h

   1/*
   2 * QEMU RISC-V CPU -- internal functions and types
   3 *
   4 * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms and conditions of the GNU General Public License,
   8 * version 2 or later, as published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope it will be useful, but WITHOUT
  11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13 * more details.
  14 *
  15 * You should have received a copy of the GNU General Public License along with
  16 * this program.  If not, see <http://www.gnu.org/licenses/>.
  17 */
  18
  19#ifndef RISCV_CPU_INTERNALS_H
  20#define RISCV_CPU_INTERNALS_H
  21
  22#include "hw/registerfields.h"
  23
  24/* share data between vector helpers and decode code */
  25FIELD(VDATA, VM, 0, 1)
  26FIELD(VDATA, LMUL, 1, 3)
  27FIELD(VDATA, NF, 4, 4)
  28FIELD(VDATA, WD, 4, 1)
  29
  30/* float point classify helpers */
  31target_ulong fclass_h(uint64_t frs1);
  32target_ulong fclass_s(uint64_t frs1);
  33target_ulong fclass_d(uint64_t frs1);
  34
  35#ifndef CONFIG_USER_ONLY
  36extern const VMStateDescription vmstate_riscv_cpu;
  37#endif
  38
  39enum {
  40    RISCV_FRM_RNE = 0,  /* Round to Nearest, ties to Even */
  41    RISCV_FRM_RTZ = 1,  /* Round towards Zero */
  42    RISCV_FRM_RDN = 2,  /* Round Down */
  43    RISCV_FRM_RUP = 3,  /* Round Up */
  44    RISCV_FRM_RMM = 4,  /* Round to Nearest, ties to Max Magnitude */
  45    RISCV_FRM_DYN = 7,  /* Dynamic rounding mode */
  46    RISCV_FRM_ROD = 8,  /* Round to Odd */
  47};
  48
  49static inline uint64_t nanbox_s(CPURISCVState *env, float32 f)
  50{
  51    /* the value is sign-extended instead of NaN-boxing for zfinx */
  52    if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
  53        return (int32_t)f;
  54    } else {
  55        return f | MAKE_64BIT_MASK(32, 32);
  56    }
  57}
  58
  59static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f)
  60{
  61    /* Disable NaN-boxing check when enable zfinx */
  62    if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
  63        return (uint32_t)f;
  64    }
  65
  66    uint64_t mask = MAKE_64BIT_MASK(32, 32);
  67
  68    if (likely((f & mask) == mask)) {
  69        return (uint32_t)f;
  70    } else {
  71        return 0x7fc00000u; /* default qnan */
  72    }
  73}
  74
  75static inline uint64_t nanbox_h(CPURISCVState *env, float16 f)
  76{
  77    /* the value is sign-extended instead of NaN-boxing for zfinx */
  78    if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
  79        return (int16_t)f;
  80    } else {
  81        return f | MAKE_64BIT_MASK(16, 48);
  82    }
  83}
  84
  85static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f)
  86{
  87    /* Disable nanbox check when enable zfinx */
  88    if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
  89        return (uint16_t)f;
  90    }
  91
  92    uint64_t mask = MAKE_64BIT_MASK(16, 48);
  93
  94    if (likely((f & mask) == mask)) {
  95        return (uint16_t)f;
  96    } else {
  97        return 0x7E00u; /* default qnan */
  98    }
  99}
 100
 101#endif
 102