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20#ifndef SH4_CPU_H
21#define SH4_CPU_H
22
23#include "cpu-qom.h"
24#include "exec/cpu-defs.h"
25
26
27#define SH_CPU_SH7750 (1 << 0)
28#define SH_CPU_SH7750S (1 << 1)
29#define SH_CPU_SH7750R (1 << 2)
30#define SH_CPU_SH7751 (1 << 3)
31#define SH_CPU_SH7751R (1 << 4)
32#define SH_CPU_SH7785 (1 << 5)
33#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
34#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
35
36#define SR_MD 30
37#define SR_RB 29
38#define SR_BL 28
39#define SR_FD 15
40#define SR_M 9
41#define SR_Q 8
42#define SR_I3 7
43#define SR_I2 6
44#define SR_I1 5
45#define SR_I0 4
46#define SR_S 1
47#define SR_T 0
48
49#define FPSCR_MASK (0x003fffff)
50#define FPSCR_FR (1 << 21)
51#define FPSCR_SZ (1 << 20)
52#define FPSCR_PR (1 << 19)
53#define FPSCR_DN (1 << 18)
54#define FPSCR_CAUSE_MASK (0x3f << 12)
55#define FPSCR_CAUSE_SHIFT (12)
56#define FPSCR_CAUSE_E (1 << 17)
57#define FPSCR_CAUSE_V (1 << 16)
58#define FPSCR_CAUSE_Z (1 << 15)
59#define FPSCR_CAUSE_O (1 << 14)
60#define FPSCR_CAUSE_U (1 << 13)
61#define FPSCR_CAUSE_I (1 << 12)
62#define FPSCR_ENABLE_MASK (0x1f << 7)
63#define FPSCR_ENABLE_SHIFT (7)
64#define FPSCR_ENABLE_V (1 << 11)
65#define FPSCR_ENABLE_Z (1 << 10)
66#define FPSCR_ENABLE_O (1 << 9)
67#define FPSCR_ENABLE_U (1 << 8)
68#define FPSCR_ENABLE_I (1 << 7)
69#define FPSCR_FLAG_MASK (0x1f << 2)
70#define FPSCR_FLAG_SHIFT (2)
71#define FPSCR_FLAG_V (1 << 6)
72#define FPSCR_FLAG_Z (1 << 5)
73#define FPSCR_FLAG_O (1 << 4)
74#define FPSCR_FLAG_U (1 << 3)
75#define FPSCR_FLAG_I (1 << 2)
76#define FPSCR_RM_MASK (0x03 << 0)
77#define FPSCR_RM_NEAREST (0 << 0)
78#define FPSCR_RM_ZERO (1 << 0)
79
80#define DELAY_SLOT_MASK 0x7
81#define DELAY_SLOT (1 << 0)
82#define DELAY_SLOT_CONDITIONAL (1 << 1)
83#define DELAY_SLOT_RTE (1 << 2)
84
85#define TB_FLAG_PENDING_MOVCA (1 << 3)
86#define TB_FLAG_UNALIGN (1 << 4)
87
88#define GUSA_SHIFT 4
89#ifdef CONFIG_USER_ONLY
90#define GUSA_EXCLUSIVE (1 << 12)
91#define GUSA_MASK ((0xff << GUSA_SHIFT) | GUSA_EXCLUSIVE)
92#else
93
94
95#define GUSA_EXCLUSIVE 0
96#define GUSA_MASK 0
97#endif
98
99#define TB_FLAG_ENVFLAGS_MASK (DELAY_SLOT_MASK | GUSA_MASK)
100
101typedef struct tlb_t {
102 uint32_t vpn;
103 uint32_t ppn;
104 uint32_t size;
105 uint8_t asid;
106 uint8_t v:1;
107 uint8_t sz:2;
108 uint8_t sh:1;
109 uint8_t c:1;
110 uint8_t pr:2;
111 uint8_t d:1;
112 uint8_t wt:1;
113 uint8_t sa:3;
114 uint8_t tc:1;
115} tlb_t;
116
117#define UTLB_SIZE 64
118#define ITLB_SIZE 4
119
120#define TARGET_INSN_START_EXTRA_WORDS 1
121
122enum sh_features {
123 SH_FEATURE_SH4A = 1,
124 SH_FEATURE_BCR3_AND_BCR4 = 2,
125};
126
127typedef struct memory_content {
128 uint32_t address;
129 uint32_t value;
130 struct memory_content *next;
131} memory_content;
132
133typedef struct CPUArchState {
134 uint32_t flags;
135 uint32_t gregs[24];
136 float32 fregs[32];
137 uint32_t sr;
138 uint32_t sr_m;
139 uint32_t sr_q;
140 uint32_t sr_t;
141 uint32_t ssr;
142 uint32_t spc;
143 uint32_t gbr;
144 uint32_t vbr;
145 uint32_t sgr;
146 uint32_t dbr;
147 uint32_t pc;
148 uint32_t delayed_pc;
149 uint32_t delayed_cond;
150 uint32_t mach;
151 uint32_t macl;
152 uint32_t pr;
153 uint32_t fpscr;
154 uint32_t fpul;
155
156
157 float_status fp_status;
158
159
160 uint32_t mmucr;
161 uint32_t pteh;
162 uint32_t ptel;
163 uint32_t ptea;
164 uint32_t ttb;
165 uint32_t tea;
166 uint32_t tra;
167 uint32_t expevt;
168 uint32_t intevt;
169
170 tlb_t itlb[ITLB_SIZE];
171 tlb_t utlb[UTLB_SIZE];
172
173
174 uint32_t lock_addr;
175 uint32_t lock_value;
176
177
178 struct {} end_reset_fields;
179
180
181 int id;
182
183
184 uint32_t features;
185
186 void *intc_handle;
187 int in_sleep;
188 memory_content *movcal_backup;
189 memory_content **movcal_backup_tail;
190} CPUSH4State;
191
192
193
194
195
196
197
198struct ArchCPU {
199
200 CPUState parent_obj;
201
202
203 CPUNegativeOffsetState neg;
204 CPUSH4State env;
205};
206
207
208void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
209hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
210int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
211int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
212void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
213 MMUAccessType access_type, int mmu_idx,
214 uintptr_t retaddr) QEMU_NORETURN;
215
216void sh4_translate_init(void);
217void sh4_cpu_list(void);
218
219#if !defined(CONFIG_USER_ONLY)
220bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
221 MMUAccessType access_type, int mmu_idx,
222 bool probe, uintptr_t retaddr);
223void superh_cpu_do_interrupt(CPUState *cpu);
224bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
225void cpu_sh4_invalidate_tlb(CPUSH4State *s);
226uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
227 hwaddr addr);
228void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
229 uint32_t mem_value);
230uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
231 hwaddr addr);
232void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
233 uint32_t mem_value);
234uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
235 hwaddr addr);
236void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
237 uint32_t mem_value);
238uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
239 hwaddr addr);
240void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
241 uint32_t mem_value);
242#endif
243
244int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
245
246void cpu_load_tlb(CPUSH4State * env);
247
248#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU
249#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX
250#define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU
251
252#define cpu_list sh4_cpu_list
253
254
255#define MMU_USER_IDX 1
256static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
257{
258
259
260 if (ifetch && (env->flags & DELAY_SLOT_RTE)) {
261 return 0;
262 } else {
263 return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
264 }
265}
266
267#include "exec/cpu-all.h"
268
269
270#define MMUCR 0x1F000010
271#define MMUCR_AT (1<<0)
272#define MMUCR_TI (1<<2)
273#define MMUCR_SV (1<<8)
274#define MMUCR_URC_BITS (6)
275#define MMUCR_URC_OFFSET (10)
276#define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
277#define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
278static inline int cpu_mmucr_urc (uint32_t mmucr)
279{
280 return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
281}
282
283
284#define PTEH_ASID_BITS (8)
285#define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
286#define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
287#define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
288#define PTEH_VPN_BITS (22)
289#define PTEH_VPN_OFFSET (10)
290#define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
291#define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
292static inline int cpu_pteh_vpn (uint32_t pteh)
293{
294 return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
295}
296
297
298#define PTEL_V (1 << 8)
299#define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
300#define PTEL_C (1 << 3)
301#define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
302#define PTEL_D (1 << 2)
303#define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
304#define PTEL_SH (1 << 1)
305#define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
306#define PTEL_WT (1 << 0)
307#define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
308
309#define PTEL_SZ_HIGH_OFFSET (7)
310#define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET)
311#define PTEL_SZ_LOW_OFFSET (4)
312#define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET)
313static inline int cpu_ptel_sz (uint32_t ptel)
314{
315 int sz;
316 sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
317 sz <<= 1;
318 sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
319 return sz;
320}
321
322#define PTEL_PPN_BITS (19)
323#define PTEL_PPN_OFFSET (10)
324#define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
325#define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
326static inline int cpu_ptel_ppn (uint32_t ptel)
327{
328 return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
329}
330
331#define PTEL_PR_BITS (2)
332#define PTEL_PR_OFFSET (5)
333#define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
334#define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
335static inline int cpu_ptel_pr (uint32_t ptel)
336{
337 return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
338}
339
340
341#define PTEA_SA_BITS (3)
342#define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
343#define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
344#define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
345#define PTEA_TC (1 << 3)
346#define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
347
348static inline target_ulong cpu_read_sr(CPUSH4State *env)
349{
350 return env->sr | (env->sr_m << SR_M) |
351 (env->sr_q << SR_Q) |
352 (env->sr_t << SR_T);
353}
354
355static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
356{
357 env->sr_m = (sr >> SR_M) & 1;
358 env->sr_q = (sr >> SR_Q) & 1;
359 env->sr_t = (sr >> SR_T) & 1;
360 env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
361}
362
363static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
364 target_ulong *cs_base, uint32_t *flags)
365{
366 *pc = env->pc;
367
368 *cs_base = env->flags & GUSA_MASK ? env->gregs[0] : 0;
369 *flags = env->flags
370 | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR))
371 | (env->sr & ((1u << SR_MD) | (1u << SR_RB)))
372 | (env->sr & (1u << SR_FD))
373 | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0);
374#ifdef CONFIG_USER_ONLY
375 *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
376#endif
377}
378
379#endif
380