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29#include "qemu/osdep.h"
30#include "qapi/error.h"
31#include "qemu/bitmap.h"
32#include "trace.h"
33#include "hw/core/cpu.h"
34#include "target/arm/cpu.h"
35#include "hw/acpi/acpi-defs.h"
36#include "hw/acpi/acpi.h"
37#include "hw/nvram/fw_cfg.h"
38#include "hw/acpi/bios-linker-loader.h"
39#include "hw/acpi/aml-build.h"
40#include "hw/acpi/utils.h"
41#include "hw/acpi/pci.h"
42#include "hw/acpi/memory_hotplug.h"
43#include "hw/acpi/generic_event_device.h"
44#include "hw/acpi/tpm.h"
45#include "hw/pci/pcie_host.h"
46#include "hw/pci/pci.h"
47#include "hw/pci/pci_bus.h"
48#include "hw/pci-host/gpex.h"
49#include "hw/arm/virt.h"
50#include "hw/mem/nvdimm.h"
51#include "hw/platform-bus.h"
52#include "sysemu/numa.h"
53#include "sysemu/reset.h"
54#include "sysemu/tpm.h"
55#include "kvm_arm.h"
56#include "migration/vmstate.h"
57#include "hw/acpi/ghes.h"
58#include "hw/acpi/viot.h"
59
60#define ARM_SPI_BASE 32
61
62#define ACPI_BUILD_TABLE_SIZE 0x20000
63
64static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms)
65{
66 MachineState *ms = MACHINE(vms);
67 uint16_t i;
68
69 for (i = 0; i < ms->smp.cpus; i++) {
70 Aml *dev = aml_device("C%.03X", i);
71 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
72 aml_append(dev, aml_name_decl("_UID", aml_int(i)));
73 aml_append(scope, dev);
74 }
75}
76
77static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
78 uint32_t uart_irq)
79{
80 Aml *dev = aml_device("COM0");
81 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
82 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
83
84 Aml *crs = aml_resource_template();
85 aml_append(crs, aml_memory32_fixed(uart_memmap->base,
86 uart_memmap->size, AML_READ_WRITE));
87 aml_append(crs,
88 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
89 AML_EXCLUSIVE, &uart_irq, 1));
90 aml_append(dev, aml_name_decl("_CRS", crs));
91
92 aml_append(scope, dev);
93}
94
95static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
96{
97 Aml *dev = aml_device("FWCF");
98 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
99
100 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
101 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
102
103 Aml *crs = aml_resource_template();
104 aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
105 fw_cfg_memmap->size, AML_READ_WRITE));
106 aml_append(dev, aml_name_decl("_CRS", crs));
107 aml_append(scope, dev);
108}
109
110static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
111{
112 Aml *dev, *crs;
113 hwaddr base = flash_memmap->base;
114 hwaddr size = flash_memmap->size / 2;
115
116 dev = aml_device("FLS0");
117 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
118 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
119
120 crs = aml_resource_template();
121 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
122 aml_append(dev, aml_name_decl("_CRS", crs));
123 aml_append(scope, dev);
124
125 dev = aml_device("FLS1");
126 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
127 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
128 crs = aml_resource_template();
129 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE));
130 aml_append(dev, aml_name_decl("_CRS", crs));
131 aml_append(scope, dev);
132}
133
134static void acpi_dsdt_add_virtio(Aml *scope,
135 const MemMapEntry *virtio_mmio_memmap,
136 uint32_t mmio_irq, int num)
137{
138 hwaddr base = virtio_mmio_memmap->base;
139 hwaddr size = virtio_mmio_memmap->size;
140 int i;
141
142 for (i = 0; i < num; i++) {
143 uint32_t irq = mmio_irq + i;
144 Aml *dev = aml_device("VR%02u", i);
145 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
146 aml_append(dev, aml_name_decl("_UID", aml_int(i)));
147 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
148
149 Aml *crs = aml_resource_template();
150 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
151 aml_append(crs,
152 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
153 AML_EXCLUSIVE, &irq, 1));
154 aml_append(dev, aml_name_decl("_CRS", crs));
155 aml_append(scope, dev);
156 base += size;
157 }
158}
159
160static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
161 uint32_t irq, VirtMachineState *vms)
162{
163 int ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
164 struct GPEXConfig cfg = {
165 .mmio32 = memmap[VIRT_PCIE_MMIO],
166 .pio = memmap[VIRT_PCIE_PIO],
167 .ecam = memmap[ecam_id],
168 .irq = irq,
169 .bus = vms->bus,
170 };
171
172 if (vms->highmem_mmio) {
173 cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO];
174 }
175
176 acpi_dsdt_add_gpex(scope, &cfg);
177}
178
179static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
180 uint32_t gpio_irq)
181{
182 Aml *dev = aml_device("GPO0");
183 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061")));
184 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
185
186 Aml *crs = aml_resource_template();
187 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size,
188 AML_READ_WRITE));
189 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
190 AML_EXCLUSIVE, &gpio_irq, 1));
191 aml_append(dev, aml_name_decl("_CRS", crs));
192
193 Aml *aei = aml_resource_template();
194
195 const uint32_t pin_list[1] = {3};
196 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH,
197 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1,
198 "GPO0", NULL, 0));
199 aml_append(dev, aml_name_decl("_AEI", aei));
200
201
202 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED);
203 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE),
204 aml_int(0x80)));
205 aml_append(dev, method);
206 aml_append(scope, dev);
207}
208
209#ifdef CONFIG_TPM
210static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms)
211{
212 PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
213 hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base;
214 SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find());
215 MemoryRegion *sbdev_mr;
216 hwaddr tpm_base;
217
218 if (!sbdev) {
219 return;
220 }
221
222 tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
223 assert(tpm_base != -1);
224
225 tpm_base += pbus_base;
226
227 sbdev_mr = sysbus_mmio_get_region(sbdev, 0);
228
229 Aml *dev = aml_device("TPM0");
230 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
231 aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device")));
232 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
233
234 Aml *crs = aml_resource_template();
235 aml_append(crs,
236 aml_memory32_fixed(tpm_base,
237 (uint32_t)memory_region_size(sbdev_mr),
238 AML_READ_WRITE));
239 aml_append(dev, aml_name_decl("_CRS", crs));
240 aml_append(scope, dev);
241}
242#endif
243
244#define ID_MAPPING_ENTRY_SIZE 20
245#define SMMU_V3_ENTRY_SIZE 68
246#define ROOT_COMPLEX_ENTRY_SIZE 36
247#define IORT_NODE_OFFSET 48
248
249static void build_iort_id_mapping(GArray *table_data, uint32_t input_base,
250 uint32_t id_count, uint32_t out_ref)
251{
252
253 build_append_int_noprefix(table_data, input_base, 4);
254 build_append_int_noprefix(table_data, id_count, 4);
255 build_append_int_noprefix(table_data, input_base, 4);
256 build_append_int_noprefix(table_data, out_ref, 4);
257
258 build_append_int_noprefix(table_data, 0 , 4);
259}
260
261struct AcpiIortIdMapping {
262 uint32_t input_base;
263 uint32_t id_count;
264};
265typedef struct AcpiIortIdMapping AcpiIortIdMapping;
266
267
268static int
269iort_host_bridges(Object *obj, void *opaque)
270{
271 GArray *idmap_blob = opaque;
272
273 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
274 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
275
276 if (bus && !pci_bus_bypass_iommu(bus)) {
277 int min_bus, max_bus;
278
279 pci_bus_range(bus, &min_bus, &max_bus);
280
281 AcpiIortIdMapping idmap = {
282 .input_base = min_bus << 8,
283 .id_count = (max_bus - min_bus + 1) << 8,
284 };
285 g_array_append_val(idmap_blob, idmap);
286 }
287 }
288
289 return 0;
290}
291
292static int iort_idmap_compare(gconstpointer a, gconstpointer b)
293{
294 AcpiIortIdMapping *idmap_a = (AcpiIortIdMapping *)a;
295 AcpiIortIdMapping *idmap_b = (AcpiIortIdMapping *)b;
296
297 return idmap_a->input_base - idmap_b->input_base;
298}
299
300
301
302
303
304
305static void
306build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
307{
308 int i, nb_nodes, rc_mapping_count;
309 const uint32_t iort_node_offset = IORT_NODE_OFFSET;
310 size_t node_size, smmu_offset = 0;
311 AcpiIortIdMapping *idmap;
312 uint32_t id = 0;
313 GArray *smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
314 GArray *its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
315
316 AcpiTable table = { .sig = "IORT", .rev = 3, .oem_id = vms->oem_id,
317 .oem_table_id = vms->oem_table_id };
318
319 acpi_table_begin(&table, table_data);
320
321 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
322 AcpiIortIdMapping next_range = {0};
323
324 object_child_foreach_recursive(object_get_root(),
325 iort_host_bridges, smmu_idmaps);
326
327
328 g_array_sort(smmu_idmaps, iort_idmap_compare);
329
330
331
332
333
334 for (i = 0; i < smmu_idmaps->len; i++) {
335 idmap = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i);
336
337 if (next_range.input_base < idmap->input_base) {
338 next_range.id_count = idmap->input_base - next_range.input_base;
339 g_array_append_val(its_idmaps, next_range);
340 }
341
342 next_range.input_base = idmap->input_base + idmap->id_count;
343 }
344
345
346 if (next_range.input_base < 0xFFFF) {
347 next_range.id_count = 0xFFFF - next_range.input_base;
348 g_array_append_val(its_idmaps, next_range);
349 }
350
351 nb_nodes = 3;
352 rc_mapping_count = smmu_idmaps->len + its_idmaps->len;
353 } else {
354 nb_nodes = 2;
355 rc_mapping_count = 1;
356 }
357
358 build_append_int_noprefix(table_data, nb_nodes, 4);
359
360
361 build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4);
362 build_append_int_noprefix(table_data, 0, 4);
363
364
365 build_append_int_noprefix(table_data, 0 , 1);
366 node_size = 20 + 4 ;
367 build_append_int_noprefix(table_data, node_size, 2);
368 build_append_int_noprefix(table_data, 1, 1);
369 build_append_int_noprefix(table_data, id++, 4);
370 build_append_int_noprefix(table_data, 0, 4);
371 build_append_int_noprefix(table_data, 0, 4);
372 build_append_int_noprefix(table_data, 1, 4);
373
374 build_append_int_noprefix(table_data, 0 , 4);
375
376 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
377 int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE;
378
379 smmu_offset = table_data->len - table.table_offset;
380
381 build_append_int_noprefix(table_data, 4 , 1);
382 node_size = SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE;
383 build_append_int_noprefix(table_data, node_size, 2);
384 build_append_int_noprefix(table_data, 4, 1);
385 build_append_int_noprefix(table_data, id++, 4);
386 build_append_int_noprefix(table_data, 1, 4);
387
388 build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4);
389
390 build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base, 8);
391
392 build_append_int_noprefix(table_data, 1 , 4);
393 build_append_int_noprefix(table_data, 0, 4);
394 build_append_int_noprefix(table_data, 0, 8);
395
396 build_append_int_noprefix(table_data, 0 , 4);
397 build_append_int_noprefix(table_data, irq, 4);
398 build_append_int_noprefix(table_data, irq + 1, 4);
399 build_append_int_noprefix(table_data, irq + 3, 4);
400 build_append_int_noprefix(table_data, irq + 2, 4);
401 build_append_int_noprefix(table_data, 0, 4);
402
403 build_append_int_noprefix(table_data, 0, 4);
404
405
406 build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET);
407 }
408
409
410 build_append_int_noprefix(table_data, 2 , 1);
411 node_size = ROOT_COMPLEX_ENTRY_SIZE +
412 ID_MAPPING_ENTRY_SIZE * rc_mapping_count;
413 build_append_int_noprefix(table_data, node_size, 2);
414 build_append_int_noprefix(table_data, 3, 1);
415 build_append_int_noprefix(table_data, id++, 4);
416
417 build_append_int_noprefix(table_data, rc_mapping_count, 4);
418
419 build_append_int_noprefix(table_data, ROOT_COMPLEX_ENTRY_SIZE, 4);
420
421
422
423 build_append_int_noprefix(table_data, 1 , 4);
424 build_append_int_noprefix(table_data, 0, 1);
425 build_append_int_noprefix(table_data, 0, 2);
426
427 build_append_int_noprefix(table_data, 0x3 , 1);
428
429 build_append_int_noprefix(table_data, 0, 4);
430
431 build_append_int_noprefix(table_data, 0, 4);
432
433
434 build_append_int_noprefix(table_data, 64, 1);
435
436 build_append_int_noprefix(table_data, 0, 3);
437
438
439 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
440 AcpiIortIdMapping *range;
441
442
443 for (i = 0; i < smmu_idmaps->len; i++) {
444 range = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i);
445
446 build_iort_id_mapping(table_data, range->input_base,
447 range->id_count, smmu_offset);
448 }
449
450
451 for (i = 0; i < its_idmaps->len; i++) {
452 range = &g_array_index(its_idmaps, AcpiIortIdMapping, i);
453
454 build_iort_id_mapping(table_data, range->input_base,
455 range->id_count, iort_node_offset);
456 }
457 } else {
458
459 build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET);
460 }
461
462 acpi_table_end(linker, &table);
463 g_array_free(smmu_idmaps, true);
464 g_array_free(its_idmaps, true);
465}
466
467
468
469
470
471static void
472build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
473{
474 AcpiTable table = { .sig = "SPCR", .rev = 2, .oem_id = vms->oem_id,
475 .oem_table_id = vms->oem_table_id };
476
477 acpi_table_begin(&table, table_data);
478
479
480 build_append_int_noprefix(table_data, 3, 1);
481 build_append_int_noprefix(table_data, 0, 3);
482
483 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 8, 0, 1,
484 vms->memmap[VIRT_UART].base);
485
486 build_append_int_noprefix(table_data,
487 (1 << 3) , 1);
488 build_append_int_noprefix(table_data, 0, 1);
489
490 build_append_int_noprefix(table_data,
491 vms->irqmap[VIRT_UART] + ARM_SPI_BASE, 4);
492 build_append_int_noprefix(table_data, 3 , 1);
493 build_append_int_noprefix(table_data, 0 , 1);
494
495 build_append_int_noprefix(table_data, 1 , 1);
496
497 build_append_int_noprefix(table_data,
498 (1 << 1) , 1);
499
500 build_append_int_noprefix(table_data, 0 , 1);
501 build_append_int_noprefix(table_data, 0, 1);
502
503 build_append_int_noprefix(table_data, 0xffff , 2);
504
505 build_append_int_noprefix(table_data, 0xffff , 2);
506 build_append_int_noprefix(table_data, 0, 1);
507 build_append_int_noprefix(table_data, 0, 1);
508 build_append_int_noprefix(table_data, 0, 1);
509 build_append_int_noprefix(table_data, 0, 4);
510 build_append_int_noprefix(table_data, 0, 1);
511 build_append_int_noprefix(table_data, 0, 4);
512
513 acpi_table_end(linker, &table);
514}
515
516
517
518
519
520static void
521build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
522{
523 int i;
524 uint64_t mem_base;
525 MachineClass *mc = MACHINE_GET_CLASS(vms);
526 MachineState *ms = MACHINE(vms);
527 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms);
528 AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id,
529 .oem_table_id = vms->oem_table_id };
530
531 acpi_table_begin(&table, table_data);
532 build_append_int_noprefix(table_data, 1, 4);
533 build_append_int_noprefix(table_data, 0, 8);
534
535 for (i = 0; i < cpu_list->len; ++i) {
536 uint32_t nodeid = cpu_list->cpus[i].props.node_id;
537
538
539
540 build_append_int_noprefix(table_data, 3, 1);
541 build_append_int_noprefix(table_data, 18, 1);
542 build_append_int_noprefix(table_data, nodeid, 4);
543 build_append_int_noprefix(table_data, i, 4);
544
545 build_append_int_noprefix(table_data, 1 , 4);
546 build_append_int_noprefix(table_data, 0, 4);
547 }
548
549 mem_base = vms->memmap[VIRT_MEM].base;
550 for (i = 0; i < ms->numa_state->num_nodes; ++i) {
551 if (ms->numa_state->nodes[i].node_mem > 0) {
552 build_srat_memory(table_data, mem_base,
553 ms->numa_state->nodes[i].node_mem, i,
554 MEM_AFFINITY_ENABLED);
555 mem_base += ms->numa_state->nodes[i].node_mem;
556 }
557 }
558
559 if (ms->nvdimms_state->is_enabled) {
560 nvdimm_build_srat(table_data);
561 }
562
563 if (ms->device_memory) {
564 build_srat_memory(table_data, ms->device_memory->base,
565 memory_region_size(&ms->device_memory->mr),
566 ms->numa_state->num_nodes - 1,
567 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
568 }
569
570 acpi_table_end(linker, &table);
571}
572
573
574
575
576
577static void
578build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
579{
580 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
581
582
583
584
585
586 uint32_t irqflags = vmc->claim_edge_triggered_timers ?
587 1 :
588 0;
589 AcpiTable table = { .sig = "GTDT", .rev = 2, .oem_id = vms->oem_id,
590 .oem_table_id = vms->oem_table_id };
591
592 acpi_table_begin(&table, table_data);
593
594
595
596 build_append_int_noprefix(table_data, 0, 8);
597 build_append_int_noprefix(table_data, 0, 4);
598
599
600
601
602
603 build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ + 16, 4);
604
605 build_append_int_noprefix(table_data, irqflags, 4);
606
607 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ + 16, 4);
608
609 build_append_int_noprefix(table_data, irqflags |
610 1UL << 2,
611 4);
612
613 build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ + 16, 4);
614
615 build_append_int_noprefix(table_data, irqflags, 4);
616
617 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ + 16, 4);
618
619 build_append_int_noprefix(table_data, irqflags, 4);
620
621 build_append_int_noprefix(table_data, 0, 8);
622
623 build_append_int_noprefix(table_data, 0, 4);
624
625 build_append_int_noprefix(table_data, 0, 4);
626
627 acpi_table_end(linker, &table);
628}
629
630
631static void
632build_dbg2(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
633{
634 AcpiTable table = { .sig = "DBG2", .rev = 0, .oem_id = vms->oem_id,
635 .oem_table_id = vms->oem_table_id };
636 int dbg2devicelength;
637 const char name[] = "COM0";
638 const int namespace_length = sizeof(name);
639
640 acpi_table_begin(&table, table_data);
641
642 dbg2devicelength = 22 +
643 12 +
644 4 +
645 namespace_length ;
646
647
648 build_append_int_noprefix(table_data, 44, 4);
649
650 build_append_int_noprefix(table_data, 1, 4);
651
652
653 build_append_int_noprefix(table_data, 0, 1);
654 build_append_int_noprefix(table_data, dbg2devicelength, 2);
655
656 build_append_int_noprefix(table_data, 1, 1);
657
658 build_append_int_noprefix(table_data, namespace_length, 2);
659 build_append_int_noprefix(table_data, 38, 2);
660 build_append_int_noprefix(table_data, 0, 2);
661
662 build_append_int_noprefix(table_data, 0, 2);
663
664
665 build_append_int_noprefix(table_data, 0x8000 , 2);
666
667 build_append_int_noprefix(table_data, 0x3 , 2);
668 build_append_int_noprefix(table_data, 0, 2);
669
670 build_append_int_noprefix(table_data, 22, 2);
671
672 build_append_int_noprefix(table_data, 34, 2);
673
674
675 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 8, 0, 1,
676 vms->memmap[VIRT_UART].base);
677
678
679 build_append_int_noprefix(table_data,
680 vms->memmap[VIRT_UART].size, 4);
681
682
683 g_array_append_vals(table_data, name, namespace_length);
684
685 acpi_table_end(linker, &table);
686};
687
688
689
690
691
692static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size)
693{
694 build_append_int_noprefix(table_data, 0xE, 1);
695 build_append_int_noprefix(table_data, 16, 1);
696 build_append_int_noprefix(table_data, 0, 2);
697
698 build_append_int_noprefix(table_data, base, 8);
699 build_append_int_noprefix(table_data, size, 4);
700}
701
702static void
703build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
704{
705 int i;
706 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
707 const MemMapEntry *memmap = vms->memmap;
708 AcpiTable table = { .sig = "APIC", .rev = 3, .oem_id = vms->oem_id,
709 .oem_table_id = vms->oem_table_id };
710
711 acpi_table_begin(&table, table_data);
712
713 build_append_int_noprefix(table_data, 0, 4);
714 build_append_int_noprefix(table_data, 0, 4);
715
716
717 build_append_int_noprefix(table_data, 0xC, 1);
718 build_append_int_noprefix(table_data, 24, 1);
719 build_append_int_noprefix(table_data, 0, 2);
720 build_append_int_noprefix(table_data, 0, 4);
721
722 build_append_int_noprefix(table_data, memmap[VIRT_GIC_DIST].base, 8);
723 build_append_int_noprefix(table_data, 0, 4);
724
725 build_append_int_noprefix(table_data, vms->gic_version, 1);
726 build_append_int_noprefix(table_data, 0, 3);
727
728 for (i = 0; i < MACHINE(vms)->smp.cpus; i++) {
729 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
730 uint64_t physical_base_address = 0, gich = 0, gicv = 0;
731 uint32_t vgic_interrupt = vms->virt ? PPI(ARCH_GIC_MAINT_IRQ) : 0;
732 uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
733 PPI(VIRTUAL_PMU_IRQ) : 0;
734
735 if (vms->gic_version == VIRT_GIC_VERSION_2) {
736 physical_base_address = memmap[VIRT_GIC_CPU].base;
737 gicv = memmap[VIRT_GIC_VCPU].base;
738 gich = memmap[VIRT_GIC_HYP].base;
739 }
740
741
742 build_append_int_noprefix(table_data, 0xB, 1);
743 build_append_int_noprefix(table_data, 76, 1);
744 build_append_int_noprefix(table_data, 0, 2);
745 build_append_int_noprefix(table_data, i, 4);
746 build_append_int_noprefix(table_data, i, 4);
747
748 build_append_int_noprefix(table_data, 1, 4);
749
750 build_append_int_noprefix(table_data, 0, 4);
751
752 build_append_int_noprefix(table_data, pmu_interrupt, 4);
753 build_append_int_noprefix(table_data, 0, 8);
754
755 build_append_int_noprefix(table_data, physical_base_address, 8);
756 build_append_int_noprefix(table_data, gicv, 8);
757 build_append_int_noprefix(table_data, gich, 8);
758
759 build_append_int_noprefix(table_data, vgic_interrupt, 4);
760 build_append_int_noprefix(table_data, 0, 8);
761
762 build_append_int_noprefix(table_data, armcpu->mp_affinity, 8);
763 }
764
765 if (vms->gic_version != VIRT_GIC_VERSION_2) {
766 build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base,
767 memmap[VIRT_GIC_REDIST].size);
768 if (virt_gicv3_redist_region_count(vms) == 2) {
769 build_append_gicr(table_data, memmap[VIRT_HIGH_GIC_REDIST2].base,
770 memmap[VIRT_HIGH_GIC_REDIST2].size);
771 }
772
773 if (its_class_name() && !vmc->no_its) {
774
775
776
777
778
779
780
781
782
783
784
785 build_append_int_noprefix(table_data, 0xF, 1);
786 build_append_int_noprefix(table_data, 20, 1);
787 build_append_int_noprefix(table_data, 0, 2);
788 build_append_int_noprefix(table_data, 0, 4);
789
790 build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].base, 8);
791 build_append_int_noprefix(table_data, 0, 4);
792 }
793 } else {
794 const uint16_t spi_base = vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE;
795
796
797 build_append_int_noprefix(table_data, 0xD, 1);
798 build_append_int_noprefix(table_data, 24, 1);
799 build_append_int_noprefix(table_data, 0, 2);
800 build_append_int_noprefix(table_data, 0, 4);
801
802 build_append_int_noprefix(table_data, memmap[VIRT_GIC_V2M].base, 8);
803 build_append_int_noprefix(table_data, 1, 4);
804
805 build_append_int_noprefix(table_data, NUM_GICV2M_SPIS, 2);
806 build_append_int_noprefix(table_data, spi_base, 2);
807 }
808 acpi_table_end(linker, &table);
809}
810
811
812static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker,
813 VirtMachineState *vms, unsigned dsdt_tbl_offset)
814{
815
816 AcpiFadtData fadt = {
817 .rev = 5,
818 .minor_ver = 1,
819 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
820 .xdsdt_tbl_offset = &dsdt_tbl_offset,
821 };
822
823 switch (vms->psci_conduit) {
824 case QEMU_PSCI_CONDUIT_DISABLED:
825 fadt.arm_boot_arch = 0;
826 break;
827 case QEMU_PSCI_CONDUIT_HVC:
828 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT |
829 ACPI_FADT_ARM_PSCI_USE_HVC;
830 break;
831 case QEMU_PSCI_CONDUIT_SMC:
832 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT;
833 break;
834 default:
835 g_assert_not_reached();
836 }
837
838 build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id);
839}
840
841
842static void
843build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
844{
845 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
846 Aml *scope, *dsdt;
847 MachineState *ms = MACHINE(vms);
848 const MemMapEntry *memmap = vms->memmap;
849 const int *irqmap = vms->irqmap;
850 AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = vms->oem_id,
851 .oem_table_id = vms->oem_table_id };
852
853 acpi_table_begin(&table, table_data);
854 dsdt = init_aml_allocator();
855
856
857
858
859
860
861 scope = aml_scope("\\_SB");
862 acpi_dsdt_add_cpus(scope, vms);
863 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
864 (irqmap[VIRT_UART] + ARM_SPI_BASE));
865 if (vmc->acpi_expose_flash) {
866 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
867 }
868 acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
869 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
870 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
871 acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms);
872 if (vms->acpi_dev) {
873 build_ged_aml(scope, "\\_SB."GED_DEVICE,
874 HOTPLUG_HANDLER(vms->acpi_dev),
875 irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY,
876 memmap[VIRT_ACPI_GED].base);
877 } else {
878 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO],
879 (irqmap[VIRT_GPIO] + ARM_SPI_BASE));
880 }
881
882 if (vms->acpi_dev) {
883 uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev),
884 "ged-event", &error_abort);
885
886 if (event & ACPI_GED_MEM_HOTPLUG_EVT) {
887 build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL,
888 AML_SYSTEM_MEMORY,
889 memmap[VIRT_PCDIMM_ACPI].base);
890 }
891 }
892
893 acpi_dsdt_add_power_button(scope);
894#ifdef CONFIG_TPM
895 acpi_dsdt_add_tpm(scope, vms);
896#endif
897
898 aml_append(dsdt, scope);
899
900
901 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
902
903 acpi_table_end(linker, &table);
904 free_aml_allocator();
905}
906
907typedef
908struct AcpiBuildState {
909
910 MemoryRegion *table_mr;
911 MemoryRegion *rsdp_mr;
912 MemoryRegion *linker_mr;
913
914 bool patched;
915} AcpiBuildState;
916
917static void acpi_align_size(GArray *blob, unsigned align)
918{
919
920
921
922
923 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
924}
925
926static
927void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
928{
929 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
930 GArray *table_offsets;
931 unsigned dsdt, xsdt;
932 GArray *tables_blob = tables->table_data;
933 MachineState *ms = MACHINE(vms);
934
935 table_offsets = g_array_new(false, true ,
936 sizeof(uint32_t));
937
938 bios_linker_loader_alloc(tables->linker,
939 ACPI_BUILD_TABLE_FILE, tables_blob,
940 64, false );
941
942
943 dsdt = tables_blob->len;
944 build_dsdt(tables_blob, tables->linker, vms);
945
946
947 acpi_add_table(table_offsets, tables_blob);
948 build_fadt_rev5(tables_blob, tables->linker, vms, dsdt);
949
950 acpi_add_table(table_offsets, tables_blob);
951 build_madt(tables_blob, tables->linker, vms);
952
953 if (!vmc->no_cpu_topology) {
954 acpi_add_table(table_offsets, tables_blob);
955 build_pptt(tables_blob, tables->linker, ms,
956 vms->oem_id, vms->oem_table_id);
957 }
958
959 acpi_add_table(table_offsets, tables_blob);
960 build_gtdt(tables_blob, tables->linker, vms);
961
962 acpi_add_table(table_offsets, tables_blob);
963 {
964 AcpiMcfgInfo mcfg = {
965 .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base,
966 .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size,
967 };
968 build_mcfg(tables_blob, tables->linker, &mcfg, vms->oem_id,
969 vms->oem_table_id);
970 }
971
972 acpi_add_table(table_offsets, tables_blob);
973 build_spcr(tables_blob, tables->linker, vms);
974
975 acpi_add_table(table_offsets, tables_blob);
976 build_dbg2(tables_blob, tables->linker, vms);
977
978 if (vms->ras) {
979 build_ghes_error_table(tables->hardware_errors, tables->linker);
980 acpi_add_table(table_offsets, tables_blob);
981 acpi_build_hest(tables_blob, tables->linker, vms->oem_id,
982 vms->oem_table_id);
983 }
984
985 if (ms->numa_state->num_nodes > 0) {
986 acpi_add_table(table_offsets, tables_blob);
987 build_srat(tables_blob, tables->linker, vms);
988 if (ms->numa_state->have_numa_distance) {
989 acpi_add_table(table_offsets, tables_blob);
990 build_slit(tables_blob, tables->linker, ms, vms->oem_id,
991 vms->oem_table_id);
992 }
993 }
994
995 if (ms->nvdimms_state->is_enabled) {
996 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
997 ms->nvdimms_state, ms->ram_slots, vms->oem_id,
998 vms->oem_table_id);
999 }
1000
1001 if (its_class_name() && !vmc->no_its) {
1002 acpi_add_table(table_offsets, tables_blob);
1003 build_iort(tables_blob, tables->linker, vms);
1004 }
1005
1006#ifdef CONFIG_TPM
1007 if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {
1008 acpi_add_table(table_offsets, tables_blob);
1009 build_tpm2(tables_blob, tables->linker, tables->tcpalog, vms->oem_id,
1010 vms->oem_table_id);
1011 }
1012#endif
1013
1014 if (vms->iommu == VIRT_IOMMU_VIRTIO) {
1015 acpi_add_table(table_offsets, tables_blob);
1016 build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf,
1017 vms->oem_id, vms->oem_table_id);
1018 }
1019
1020
1021 xsdt = tables_blob->len;
1022 build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id,
1023 vms->oem_table_id);
1024
1025
1026 {
1027 AcpiRsdpData rsdp_data = {
1028 .revision = 2,
1029 .oem_id = vms->oem_id,
1030 .xsdt_tbl_offset = &xsdt,
1031 .rsdt_tbl_offset = NULL,
1032 };
1033 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
1034 }
1035
1036
1037
1038
1039
1040 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
1041 warn_report("ACPI table size %u exceeds %d bytes,"
1042 " migration may not work",
1043 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
1044 error_printf("Try removing CPUs, NUMA nodes, memory slots"
1045 " or PCI bridges.");
1046 }
1047 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
1048
1049
1050
1051 g_array_free(table_offsets, true);
1052}
1053
1054static void acpi_ram_update(MemoryRegion *mr, GArray *data)
1055{
1056 uint32_t size = acpi_data_len(data);
1057
1058
1059
1060 memory_region_ram_resize(mr, size, &error_abort);
1061
1062 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
1063 memory_region_set_dirty(mr, 0, size);
1064}
1065
1066static void virt_acpi_build_update(void *build_opaque)
1067{
1068 AcpiBuildState *build_state = build_opaque;
1069 AcpiBuildTables tables;
1070
1071
1072 if (!build_state || build_state->patched) {
1073 return;
1074 }
1075 build_state->patched = true;
1076
1077 acpi_build_tables_init(&tables);
1078
1079 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables);
1080
1081 acpi_ram_update(build_state->table_mr, tables.table_data);
1082 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
1083 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
1084
1085 acpi_build_tables_cleanup(&tables, true);
1086}
1087
1088static void virt_acpi_build_reset(void *build_opaque)
1089{
1090 AcpiBuildState *build_state = build_opaque;
1091 build_state->patched = false;
1092}
1093
1094static const VMStateDescription vmstate_virt_acpi_build = {
1095 .name = "virt_acpi_build",
1096 .version_id = 1,
1097 .minimum_version_id = 1,
1098 .fields = (VMStateField[]) {
1099 VMSTATE_BOOL(patched, AcpiBuildState),
1100 VMSTATE_END_OF_LIST()
1101 },
1102};
1103
1104void virt_acpi_setup(VirtMachineState *vms)
1105{
1106 AcpiBuildTables tables;
1107 AcpiBuildState *build_state;
1108 AcpiGedState *acpi_ged_state;
1109
1110 if (!vms->fw_cfg) {
1111 trace_virt_acpi_setup();
1112 return;
1113 }
1114
1115 if (!virt_is_acpi_enabled(vms)) {
1116 trace_virt_acpi_setup();
1117 return;
1118 }
1119
1120 build_state = g_malloc0(sizeof *build_state);
1121
1122 acpi_build_tables_init(&tables);
1123 virt_acpi_build(vms, &tables);
1124
1125
1126 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update,
1127 build_state, tables.table_data,
1128 ACPI_BUILD_TABLE_FILE);
1129 assert(build_state->table_mr != NULL);
1130
1131 build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update,
1132 build_state,
1133 tables.linker->cmd_blob,
1134 ACPI_BUILD_LOADER_FILE);
1135
1136 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
1137 acpi_data_len(tables.tcpalog));
1138
1139 if (vms->ras) {
1140 assert(vms->acpi_dev);
1141 acpi_ged_state = ACPI_GED(vms->acpi_dev);
1142 acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state,
1143 vms->fw_cfg, tables.hardware_errors);
1144 }
1145
1146 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update,
1147 build_state, tables.rsdp,
1148 ACPI_BUILD_RSDP_FILE);
1149
1150 qemu_register_reset(virt_acpi_build_reset, build_state);
1151 virt_acpi_build_reset(build_state);
1152 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
1153
1154
1155
1156
1157 acpi_build_tables_cleanup(&tables, false);
1158}
1159