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26#include "qemu/osdep.h"
27#include "hw/ppc/mac.h"
28#include "hw/ppc/mac_dbdma.h"
29#include "hw/qdev-properties.h"
30#include "migration/vmstate.h"
31#include "qemu/module.h"
32#include "hw/misc/macio/macio.h"
33#include "sysemu/block-backend.h"
34#include "sysemu/dma.h"
35
36#include "hw/ide/internal.h"
37
38
39
40
41#ifdef DEBUG_MACIO
42static const int debug_macio = 1;
43#else
44static const int debug_macio = 0;
45#endif
46
47#define MACIO_DPRINTF(fmt, ...) do { \
48 if (debug_macio) { \
49 printf(fmt , ## __VA_ARGS__); \
50 } \
51 } while (0)
52
53
54
55
56
57#define MACIO_PAGE_SIZE 4096
58
59static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
60{
61 DBDMA_io *io = opaque;
62 MACIOIDEState *m = io->opaque;
63 IDEState *s = idebus_active_if(&m->bus);
64 int64_t offset;
65
66 MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
67
68 if (ret < 0) {
69 MACIO_DPRINTF("DMA error: %d\n", ret);
70 qemu_sglist_destroy(&s->sg);
71 ide_atapi_io_error(s, ret);
72 goto done;
73 }
74
75 if (!m->dma_active) {
76 MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
77 s->nsector, io->len, s->status);
78
79 io->processing = false;
80 return;
81 }
82
83 if (s->io_buffer_size <= 0) {
84 MACIO_DPRINTF("End of IDE transfer\n");
85 qemu_sglist_destroy(&s->sg);
86 ide_atapi_cmd_ok(s);
87 m->dma_active = false;
88 goto done;
89 }
90
91 if (io->len == 0) {
92 MACIO_DPRINTF("End of DMA transfer\n");
93 goto done;
94 }
95
96 if (s->lba == -1) {
97
98 s->io_buffer_size = MIN(s->io_buffer_size, io->len);
99 dma_memory_write(&address_space_memory, io->addr, s->io_buffer,
100 s->io_buffer_size, MEMTXATTRS_UNSPECIFIED);
101 io->len = 0;
102 ide_atapi_cmd_ok(s);
103 m->dma_active = false;
104 goto done;
105 }
106
107
108 offset = ((int64_t)s->lba << 11) + s->io_buffer_index;
109
110 qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
111 &address_space_memory);
112 qemu_sglist_add(&s->sg, io->addr, io->len);
113 s->io_buffer_size -= io->len;
114 s->io_buffer_index += io->len;
115 io->len = 0;
116
117 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset, 0x1,
118 pmac_ide_atapi_transfer_cb, io);
119 return;
120
121done:
122 dma_memory_unmap(&address_space_memory, io->dma_mem, io->dma_len,
123 io->dir, io->dma_len);
124
125 if (ret < 0) {
126 block_acct_failed(blk_get_stats(s->blk), &s->acct);
127 } else {
128 block_acct_done(blk_get_stats(s->blk), &s->acct);
129 }
130
131 ide_set_inactive(s, false);
132 io->dma_end(opaque);
133}
134
135static void pmac_ide_transfer_cb(void *opaque, int ret)
136{
137 DBDMA_io *io = opaque;
138 MACIOIDEState *m = io->opaque;
139 IDEState *s = idebus_active_if(&m->bus);
140 int64_t offset;
141
142 MACIO_DPRINTF("pmac_ide_transfer_cb\n");
143
144 if (ret < 0) {
145 MACIO_DPRINTF("DMA error: %d\n", ret);
146 qemu_sglist_destroy(&s->sg);
147 ide_dma_error(s);
148 goto done;
149 }
150
151 if (!m->dma_active) {
152 MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
153 s->nsector, io->len, s->status);
154
155 io->processing = false;
156 return;
157 }
158
159 if (s->io_buffer_size <= 0) {
160 MACIO_DPRINTF("End of IDE transfer\n");
161 qemu_sglist_destroy(&s->sg);
162 s->status = READY_STAT | SEEK_STAT;
163 ide_set_irq(s->bus);
164 m->dma_active = false;
165 goto done;
166 }
167
168 if (io->len == 0) {
169 MACIO_DPRINTF("End of DMA transfer\n");
170 goto done;
171 }
172
173
174 offset = (ide_get_sector(s) << 9) + s->io_buffer_index;
175
176 qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
177 &address_space_memory);
178 qemu_sglist_add(&s->sg, io->addr, io->len);
179 s->io_buffer_size -= io->len;
180 s->io_buffer_index += io->len;
181 io->len = 0;
182
183 switch (s->dma_cmd) {
184 case IDE_DMA_READ:
185 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset, 0x1,
186 pmac_ide_atapi_transfer_cb, io);
187 break;
188 case IDE_DMA_WRITE:
189 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, offset, 0x1,
190 pmac_ide_transfer_cb, io);
191 break;
192 case IDE_DMA_TRIM:
193 s->bus->dma->aiocb = dma_blk_io(blk_get_aio_context(s->blk), &s->sg,
194 offset, 0x1, ide_issue_trim, s,
195 pmac_ide_transfer_cb, io,
196 DMA_DIRECTION_TO_DEVICE);
197 break;
198 default:
199 abort();
200 }
201
202 return;
203
204done:
205 dma_memory_unmap(&address_space_memory, io->dma_mem, io->dma_len,
206 io->dir, io->dma_len);
207
208 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
209 if (ret < 0) {
210 block_acct_failed(blk_get_stats(s->blk), &s->acct);
211 } else {
212 block_acct_done(blk_get_stats(s->blk), &s->acct);
213 }
214 }
215
216 ide_set_inactive(s, false);
217 io->dma_end(opaque);
218}
219
220static void pmac_ide_transfer(DBDMA_io *io)
221{
222 MACIOIDEState *m = io->opaque;
223 IDEState *s = idebus_active_if(&m->bus);
224
225 MACIO_DPRINTF("\n");
226
227 if (s->drive_kind == IDE_CD) {
228 block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
229 BLOCK_ACCT_READ);
230
231 pmac_ide_atapi_transfer_cb(io, 0);
232 return;
233 }
234
235 switch (s->dma_cmd) {
236 case IDE_DMA_READ:
237 block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
238 BLOCK_ACCT_READ);
239 break;
240 case IDE_DMA_WRITE:
241 block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
242 BLOCK_ACCT_WRITE);
243 break;
244 default:
245 break;
246 }
247
248 pmac_ide_transfer_cb(io, 0);
249}
250
251static void pmac_ide_flush(DBDMA_io *io)
252{
253 MACIOIDEState *m = io->opaque;
254 IDEState *s = idebus_active_if(&m->bus);
255
256 if (s->bus->dma->aiocb) {
257 blk_drain(s->blk);
258 }
259}
260
261
262static uint64_t pmac_ide_read(void *opaque, hwaddr addr, unsigned size)
263{
264 MACIOIDEState *d = opaque;
265 uint64_t retval = 0xffffffff;
266 int reg = addr >> 4;
267
268 switch (reg) {
269 case 0x0:
270 if (size == 1) {
271 retval = ide_data_readw(&d->bus, 0) & 0xFF;
272 } else if (size == 2) {
273 retval = ide_data_readw(&d->bus, 0);
274 } else if (size == 4) {
275 retval = ide_data_readl(&d->bus, 0);
276 }
277 break;
278 case 0x1 ... 0x7:
279 if (size == 1) {
280 retval = ide_ioport_read(&d->bus, reg);
281 }
282 break;
283 case 0x8:
284 case 0x16:
285 if (size == 1) {
286 retval = ide_status_read(&d->bus, 0);
287 }
288 break;
289 case 0x20:
290 if (size == 4) {
291 retval = d->timing_reg;
292 }
293 break;
294 case 0x30:
295
296
297
298
299
300
301
302 if (size == 4) {
303 retval = d->irq_reg;
304 }
305 break;
306 }
307
308 return retval;
309}
310
311
312static void pmac_ide_write(void *opaque, hwaddr addr, uint64_t val,
313 unsigned size)
314{
315 MACIOIDEState *d = opaque;
316 int reg = addr >> 4;
317
318 switch (reg) {
319 case 0x0:
320 if (size == 2) {
321 ide_data_writew(&d->bus, 0, val);
322 } else if (size == 4) {
323 ide_data_writel(&d->bus, 0, val);
324 }
325 break;
326 case 0x1 ... 0x7:
327 if (size == 1) {
328 ide_ioport_write(&d->bus, reg, val);
329 }
330 break;
331 case 0x8:
332 case 0x16:
333 if (size == 1) {
334 ide_ctrl_write(&d->bus, 0, val);
335 }
336 break;
337 case 0x20:
338 if (size == 4) {
339 d->timing_reg = val;
340 }
341 break;
342 case 0x30:
343 if (size == 4) {
344 if (val & 0x80000000u) {
345 d->irq_reg &= 0x7fffffff;
346 }
347 }
348 break;
349 }
350}
351
352static const MemoryRegionOps pmac_ide_ops = {
353 .read = pmac_ide_read,
354 .write = pmac_ide_write,
355 .valid.min_access_size = 1,
356 .valid.max_access_size = 4,
357 .endianness = DEVICE_LITTLE_ENDIAN,
358};
359
360static const VMStateDescription vmstate_pmac = {
361 .name = "ide",
362 .version_id = 5,
363 .minimum_version_id = 0,
364 .fields = (VMStateField[]) {
365 VMSTATE_IDE_BUS(bus, MACIOIDEState),
366 VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
367 VMSTATE_BOOL(dma_active, MACIOIDEState),
368 VMSTATE_UINT32(timing_reg, MACIOIDEState),
369 VMSTATE_UINT32(irq_reg, MACIOIDEState),
370 VMSTATE_END_OF_LIST()
371 }
372};
373
374static void macio_ide_reset(DeviceState *dev)
375{
376 MACIOIDEState *d = MACIO_IDE(dev);
377
378 ide_bus_reset(&d->bus);
379}
380
381static int ide_nop_int(const IDEDMA *dma, bool is_write)
382{
383 return 0;
384}
385
386static int32_t ide_nop_int32(const IDEDMA *dma, int32_t l)
387{
388 return 0;
389}
390
391static void ide_dbdma_start(const IDEDMA *dma, IDEState *s,
392 BlockCompletionFunc *cb)
393{
394 MACIOIDEState *m = container_of(dma, MACIOIDEState, dma);
395
396 s->io_buffer_index = 0;
397 if (s->drive_kind == IDE_CD) {
398 s->io_buffer_size = s->packet_transfer_size;
399 } else {
400 s->io_buffer_size = s->nsector * BDRV_SECTOR_SIZE;
401 }
402
403 MACIO_DPRINTF("\n\n------------ IDE transfer\n");
404 MACIO_DPRINTF("buffer_size: %x buffer_index: %x\n",
405 s->io_buffer_size, s->io_buffer_index);
406 MACIO_DPRINTF("lba: %x size: %x\n", s->lba, s->io_buffer_size);
407 MACIO_DPRINTF("-------------------------\n");
408
409 m->dma_active = true;
410 DBDMA_kick(m->dbdma);
411}
412
413static const IDEDMAOps dbdma_ops = {
414 .start_dma = ide_dbdma_start,
415 .prepare_buf = ide_nop_int32,
416 .rw_buf = ide_nop_int,
417};
418
419static void macio_ide_realizefn(DeviceState *dev, Error **errp)
420{
421 MACIOIDEState *s = MACIO_IDE(dev);
422
423 ide_init2(&s->bus, s->ide_irq);
424
425
426 s->dma.ops = &dbdma_ops;
427 s->bus.dma = &s->dma;
428}
429
430static void pmac_ide_irq(void *opaque, int n, int level)
431{
432 MACIOIDEState *s = opaque;
433 uint32_t mask = 0x80000000u >> n;
434
435
436 if (level) {
437 s->irq_reg |= mask;
438 } else {
439 s->irq_reg &= ~mask;
440 }
441
442 if (n) {
443 qemu_set_irq(s->real_ide_irq, level);
444 } else {
445 qemu_set_irq(s->real_dma_irq, level);
446 }
447}
448
449static void macio_ide_initfn(Object *obj)
450{
451 SysBusDevice *d = SYS_BUS_DEVICE(obj);
452 MACIOIDEState *s = MACIO_IDE(obj);
453
454 ide_bus_init(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
455 memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
456 sysbus_init_mmio(d, &s->mem);
457 sysbus_init_irq(d, &s->real_ide_irq);
458 sysbus_init_irq(d, &s->real_dma_irq);
459 s->dma_irq = qemu_allocate_irq(pmac_ide_irq, s, 0);
460 s->ide_irq = qemu_allocate_irq(pmac_ide_irq, s, 1);
461
462 object_property_add_link(obj, "dbdma", TYPE_MAC_DBDMA,
463 (Object **) &s->dbdma,
464 qdev_prop_allow_set_link_before_realize, 0);
465}
466
467static Property macio_ide_properties[] = {
468 DEFINE_PROP_UINT32("channel", MACIOIDEState, channel, 0),
469 DEFINE_PROP_UINT32("addr", MACIOIDEState, addr, -1),
470 DEFINE_PROP_END_OF_LIST(),
471};
472
473static void macio_ide_class_init(ObjectClass *oc, void *data)
474{
475 DeviceClass *dc = DEVICE_CLASS(oc);
476
477 dc->realize = macio_ide_realizefn;
478 dc->reset = macio_ide_reset;
479 device_class_set_props(dc, macio_ide_properties);
480 dc->vmsd = &vmstate_pmac;
481 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
482}
483
484static const TypeInfo macio_ide_type_info = {
485 .name = TYPE_MACIO_IDE,
486 .parent = TYPE_SYS_BUS_DEVICE,
487 .instance_size = sizeof(MACIOIDEState),
488 .instance_init = macio_ide_initfn,
489 .class_init = macio_ide_class_init,
490};
491
492static void macio_ide_register_types(void)
493{
494 type_register_static(&macio_ide_type_info);
495}
496
497
498void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
499{
500 int i;
501
502 for (i = 0; i < 2; i++) {
503 if (hd_table[i]) {
504 ide_create_drive(&s->bus, i, hd_table[i]);
505 }
506 }
507}
508
509void macio_ide_register_dma(MACIOIDEState *s)
510{
511 DBDMA_register_channel(s->dbdma, s->channel, s->dma_irq,
512 pmac_ide_transfer, pmac_ide_flush, s);
513}
514
515type_init(macio_ide_register_types)
516
