LXR qemu/hw/intc/gicv3

   1/*
   2 * ARM GICv3 support - internal interfaces
   3 *
   4 * Copyright (c) 2012 Linaro Limited
   5 * Copyright (c) 2015 Huawei.
   6 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
   7 * Written by Peter Maydell
   8 * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
   9 *
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License as published by
  12 * the Free Software Foundation, either version 2 of the License, or
  13 * (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU General Public License along
  21 * with this program; if not, see <http://www.gnu.org/licenses/>.
  22 */
  23
  24#ifndef QEMU_ARM_GICV3_INTERNAL_H
  25#define QEMU_ARM_GICV3_INTERNAL_H
  26
  27#include "hw/registerfields.h"
  28#include "hw/intc/arm_gicv3_common.h"
  29
  30/* Distributor registers, as offsets from the distributor base address */
  31#define GICD_CTLR            0x0000
  32#define GICD_TYPER           0x0004
  33#define GICD_IIDR            0x0008
  34#define GICD_STATUSR         0x0010
  35#define GICD_SETSPI_NSR      0x0040
  36#define GICD_CLRSPI_NSR      0x0048
  37#define GICD_SETSPI_SR       0x0050
  38#define GICD_CLRSPI_SR       0x0058
  39#define GICD_SEIR            0x0068
  40#define GICD_IGROUPR         0x0080
  41#define GICD_ISENABLER       0x0100
  42#define GICD_ICENABLER       0x0180
  43#define GICD_ISPENDR         0x0200
  44#define GICD_ICPENDR         0x0280
  45#define GICD_ISACTIVER       0x0300
  46#define GICD_ICACTIVER       0x0380
  47#define GICD_IPRIORITYR      0x0400
  48#define GICD_ITARGETSR       0x0800
  49#define GICD_ICFGR           0x0C00
  50#define GICD_IGRPMODR        0x0D00
  51#define GICD_NSACR           0x0E00
  52#define GICD_SGIR            0x0F00
  53#define GICD_CPENDSGIR       0x0F10
  54#define GICD_SPENDSGIR       0x0F20
  55#define GICD_IROUTER         0x6000
  56#define GICD_IDREGS          0xFFD0
  57
  58/* GICD_CTLR fields  */
  59#define GICD_CTLR_EN_GRP0           (1U << 0)
  60#define GICD_CTLR_EN_GRP1NS         (1U << 1) /* GICv3 5.3.20 */
  61#define GICD_CTLR_EN_GRP1S          (1U << 2)
  62#define GICD_CTLR_EN_GRP1_ALL       (GICD_CTLR_EN_GRP1NS | GICD_CTLR_EN_GRP1S)
  63/* Bit 4 is ARE if the system doesn't support TrustZone, ARE_S otherwise */
  64#define GICD_CTLR_ARE               (1U << 4)
  65#define GICD_CTLR_ARE_S             (1U << 4)
  66#define GICD_CTLR_ARE_NS            (1U << 5)
  67#define GICD_CTLR_DS                (1U << 6)
  68#define GICD_CTLR_E1NWF             (1U << 7)
  69#define GICD_CTLR_RWP               (1U << 31)
  70
  71#define GICD_TYPER_LPIS_SHIFT          17
  72
  73/* 16 bits EventId */
  74#define GICD_TYPER_IDBITS            0xf
  75
  76/*
  77 * Redistributor frame offsets from RD_base
  78 */
  79#define GICR_SGI_OFFSET 0x10000
  80#define GICR_VLPI_OFFSET 0x20000
  81
  82/*
  83 * Redistributor registers, offsets from RD_base
  84 */
  85#define GICR_CTLR             0x0000
  86#define GICR_IIDR             0x0004
  87#define GICR_TYPER            0x0008
  88#define GICR_STATUSR          0x0010
  89#define GICR_WAKER            0x0014
  90#define GICR_SETLPIR          0x0040
  91#define GICR_CLRLPIR          0x0048
  92#define GICR_PROPBASER        0x0070
  93#define GICR_PENDBASER        0x0078
  94#define GICR_INVLPIR          0x00A0
  95#define GICR_INVALLR          0x00B0
  96#define GICR_SYNCR            0x00C0
  97#define GICR_IDREGS           0xFFD0
  98
  99/* SGI and PPI Redistributor registers, offsets from RD_base */
 100#define GICR_IGROUPR0         (GICR_SGI_OFFSET + 0x0080)
 101#define GICR_ISENABLER0       (GICR_SGI_OFFSET + 0x0100)
 102#define GICR_ICENABLER0       (GICR_SGI_OFFSET + 0x0180)
 103#define GICR_ISPENDR0         (GICR_SGI_OFFSET + 0x0200)
 104#define GICR_ICPENDR0         (GICR_SGI_OFFSET + 0x0280)
 105#define GICR_ISACTIVER0       (GICR_SGI_OFFSET + 0x0300)
 106#define GICR_ICACTIVER0       (GICR_SGI_OFFSET + 0x0380)
 107#define GICR_IPRIORITYR       (GICR_SGI_OFFSET + 0x0400)
 108#define GICR_ICFGR0           (GICR_SGI_OFFSET + 0x0C00)
 109#define GICR_ICFGR1           (GICR_SGI_OFFSET + 0x0C04)
 110#define GICR_IGRPMODR0        (GICR_SGI_OFFSET + 0x0D00)
 111#define GICR_NSACR            (GICR_SGI_OFFSET + 0x0E00)
 112
 113/* VLPI redistributor registers, offsets from VLPI_base */
 114#define GICR_VPROPBASER       (GICR_VLPI_OFFSET + 0x70)
 115#define GICR_VPENDBASER       (GICR_VLPI_OFFSET + 0x78)
 116
 117#define GICR_CTLR_ENABLE_LPIS        (1U << 0)
 118#define GICR_CTLR_CES                (1U << 1)
 119#define GICR_CTLR_RWP                (1U << 3)
 120#define GICR_CTLR_DPG0               (1U << 24)
 121#define GICR_CTLR_DPG1NS             (1U << 25)
 122#define GICR_CTLR_DPG1S              (1U << 26)
 123#define GICR_CTLR_UWP                (1U << 31)
 124
 125#define GICR_TYPER_PLPIS             (1U << 0)
 126#define GICR_TYPER_VLPIS             (1U << 1)
 127#define GICR_TYPER_DIRECTLPI         (1U << 3)
 128#define GICR_TYPER_LAST              (1U << 4)
 129#define GICR_TYPER_DPGS              (1U << 5)
 130#define GICR_TYPER_PROCNUM           (0xFFFFU << 8)
 131#define GICR_TYPER_COMMONLPIAFF      (0x3 << 24)
 132#define GICR_TYPER_AFFINITYVALUE     (0xFFFFFFFFULL << 32)
 133
 134#define GICR_WAKER_ProcessorSleep    (1U << 1)
 135#define GICR_WAKER_ChildrenAsleep    (1U << 2)
 136
 137FIELD(GICR_PROPBASER, IDBITS, 0, 5)
 138FIELD(GICR_PROPBASER, INNERCACHE, 7, 3)
 139FIELD(GICR_PROPBASER, SHAREABILITY, 10, 2)
 140FIELD(GICR_PROPBASER, PHYADDR, 12, 40)
 141FIELD(GICR_PROPBASER, OUTERCACHE, 56, 3)
 142
 143FIELD(GICR_PENDBASER, INNERCACHE, 7, 3)
 144FIELD(GICR_PENDBASER, SHAREABILITY, 10, 2)
 145FIELD(GICR_PENDBASER, PHYADDR, 16, 36)
 146FIELD(GICR_PENDBASER, OUTERCACHE, 56, 3)
 147FIELD(GICR_PENDBASER, PTZ, 62, 1)
 148
 149#define GICR_PROPBASER_IDBITS_THRESHOLD          0xd
 150
 151/* These are the GICv4 VPROPBASER and VPENDBASER layouts; v4.1 is different */
 152FIELD(GICR_VPROPBASER, IDBITS, 0, 5)
 153FIELD(GICR_VPROPBASER, INNERCACHE, 7, 3)
 154FIELD(GICR_VPROPBASER, SHAREABILITY, 10, 2)
 155FIELD(GICR_VPROPBASER, PHYADDR, 12, 40)
 156FIELD(GICR_VPROPBASER, OUTERCACHE, 56, 3)
 157
 158FIELD(GICR_VPENDBASER, INNERCACHE, 7, 3)
 159FIELD(GICR_VPENDBASER, SHAREABILITY, 10, 2)
 160FIELD(GICR_VPENDBASER, PHYADDR, 16, 36)
 161FIELD(GICR_VPENDBASER, OUTERCACHE, 56, 3)
 162FIELD(GICR_VPENDBASER, DIRTY, 60, 1)
 163FIELD(GICR_VPENDBASER, PENDINGLAST, 61, 1)
 164FIELD(GICR_VPENDBASER, IDAI, 62, 1)
 165FIELD(GICR_VPENDBASER, VALID, 63, 1)
 166
 167#define ICC_CTLR_EL1_CBPR           (1U << 0)
 168#define ICC_CTLR_EL1_EOIMODE        (1U << 1)
 169#define ICC_CTLR_EL1_PMHE           (1U << 6)
 170#define ICC_CTLR_EL1_PRIBITS_SHIFT 8
 171#define ICC_CTLR_EL1_PRIBITS_MASK   (7U << ICC_CTLR_EL1_PRIBITS_SHIFT)
 172#define ICC_CTLR_EL1_IDBITS_SHIFT 11
 173#define ICC_CTLR_EL1_SEIS           (1U << 14)
 174#define ICC_CTLR_EL1_A3V            (1U << 15)
 175
 176#define ICC_PMR_PRIORITY_MASK    0xff
 177#define ICC_BPR_BINARYPOINT_MASK 0x07
 178#define ICC_IGRPEN_ENABLE        0x01
 179
 180#define ICC_CTLR_EL3_CBPR_EL1S (1U << 0)
 181#define ICC_CTLR_EL3_CBPR_EL1NS (1U << 1)
 182#define ICC_CTLR_EL3_EOIMODE_EL3 (1U << 2)
 183#define ICC_CTLR_EL3_EOIMODE_EL1S (1U << 3)
 184#define ICC_CTLR_EL3_EOIMODE_EL1NS (1U << 4)
 185#define ICC_CTLR_EL3_RM (1U << 5)
 186#define ICC_CTLR_EL3_PMHE (1U << 6)
 187#define ICC_CTLR_EL3_PRIBITS_SHIFT 8
 188#define ICC_CTLR_EL3_IDBITS_SHIFT 11
 189#define ICC_CTLR_EL3_SEIS (1U << 14)
 190#define ICC_CTLR_EL3_A3V (1U << 15)
 191#define ICC_CTLR_EL3_NDS (1U << 17)
 192
 193#define ICH_VMCR_EL2_VENG0_SHIFT 0
 194#define ICH_VMCR_EL2_VENG0 (1U << ICH_VMCR_EL2_VENG0_SHIFT)
 195#define ICH_VMCR_EL2_VENG1_SHIFT 1
 196#define ICH_VMCR_EL2_VENG1 (1U << ICH_VMCR_EL2_VENG1_SHIFT)
 197#define ICH_VMCR_EL2_VACKCTL (1U << 2)
 198#define ICH_VMCR_EL2_VFIQEN (1U << 3)
 199#define ICH_VMCR_EL2_VCBPR_SHIFT 4
 200#define ICH_VMCR_EL2_VCBPR (1U << ICH_VMCR_EL2_VCBPR_SHIFT)
 201#define ICH_VMCR_EL2_VEOIM_SHIFT 9
 202#define ICH_VMCR_EL2_VEOIM (1U << ICH_VMCR_EL2_VEOIM_SHIFT)
 203#define ICH_VMCR_EL2_VBPR1_SHIFT 18
 204#define ICH_VMCR_EL2_VBPR1_LENGTH 3
 205#define ICH_VMCR_EL2_VBPR1_MASK (0x7U << ICH_VMCR_EL2_VBPR1_SHIFT)
 206#define ICH_VMCR_EL2_VBPR0_SHIFT 21
 207#define ICH_VMCR_EL2_VBPR0_LENGTH 3
 208#define ICH_VMCR_EL2_VBPR0_MASK (0x7U << ICH_VMCR_EL2_VBPR0_SHIFT)
 209#define ICH_VMCR_EL2_VPMR_SHIFT 24
 210#define ICH_VMCR_EL2_VPMR_LENGTH 8
 211#define ICH_VMCR_EL2_VPMR_MASK (0xffU << ICH_VMCR_EL2_VPMR_SHIFT)
 212
 213#define ICH_HCR_EL2_EN (1U << 0)
 214#define ICH_HCR_EL2_UIE (1U << 1)
 215#define ICH_HCR_EL2_LRENPIE (1U << 2)
 216#define ICH_HCR_EL2_NPIE (1U << 3)
 217#define ICH_HCR_EL2_VGRP0EIE (1U << 4)
 218#define ICH_HCR_EL2_VGRP0DIE (1U << 5)
 219#define ICH_HCR_EL2_VGRP1EIE (1U << 6)
 220#define ICH_HCR_EL2_VGRP1DIE (1U << 7)
 221#define ICH_HCR_EL2_TC (1U << 10)
 222#define ICH_HCR_EL2_TALL0 (1U << 11)
 223#define ICH_HCR_EL2_TALL1 (1U << 12)
 224#define ICH_HCR_EL2_TSEI (1U << 13)
 225#define ICH_HCR_EL2_TDIR (1U << 14)
 226#define ICH_HCR_EL2_EOICOUNT_SHIFT 27
 227#define ICH_HCR_EL2_EOICOUNT_LENGTH 5
 228#define ICH_HCR_EL2_EOICOUNT_MASK (0x1fU << ICH_HCR_EL2_EOICOUNT_SHIFT)
 229
 230#define ICH_LR_EL2_VINTID_SHIFT 0
 231#define ICH_LR_EL2_VINTID_LENGTH 32
 232#define ICH_LR_EL2_VINTID_MASK (0xffffffffULL << ICH_LR_EL2_VINTID_SHIFT)
 233#define ICH_LR_EL2_PINTID_SHIFT 32
 234#define ICH_LR_EL2_PINTID_LENGTH 10
 235#define ICH_LR_EL2_PINTID_MASK (0x3ffULL << ICH_LR_EL2_PINTID_SHIFT)
 236/* Note that EOI shares with the top bit of the pINTID field */
 237#define ICH_LR_EL2_EOI (1ULL << 41)
 238#define ICH_LR_EL2_PRIORITY_SHIFT 48
 239#define ICH_LR_EL2_PRIORITY_LENGTH 8
 240#define ICH_LR_EL2_PRIORITY_MASK (0xffULL << ICH_LR_EL2_PRIORITY_SHIFT)
 241#define ICH_LR_EL2_GROUP (1ULL << 60)
 242#define ICH_LR_EL2_HW (1ULL << 61)
 243#define ICH_LR_EL2_STATE_SHIFT 62
 244#define ICH_LR_EL2_STATE_LENGTH 2
 245#define ICH_LR_EL2_STATE_MASK (3ULL << ICH_LR_EL2_STATE_SHIFT)
 246/* values for the state field: */
 247#define ICH_LR_EL2_STATE_INVALID 0
 248#define ICH_LR_EL2_STATE_PENDING 1
 249#define ICH_LR_EL2_STATE_ACTIVE 2
 250#define ICH_LR_EL2_STATE_ACTIVE_PENDING 3
 251#define ICH_LR_EL2_STATE_PENDING_BIT (1ULL << ICH_LR_EL2_STATE_SHIFT)
 252#define ICH_LR_EL2_STATE_ACTIVE_BIT (2ULL << ICH_LR_EL2_STATE_SHIFT)
 253
 254#define ICH_MISR_EL2_EOI (1U << 0)
 255#define ICH_MISR_EL2_U (1U << 1)
 256#define ICH_MISR_EL2_LRENP (1U << 2)
 257#define ICH_MISR_EL2_NP (1U << 3)
 258#define ICH_MISR_EL2_VGRP0E (1U << 4)
 259#define ICH_MISR_EL2_VGRP0D (1U << 5)
 260#define ICH_MISR_EL2_VGRP1E (1U << 6)
 261#define ICH_MISR_EL2_VGRP1D (1U << 7)
 262
 263#define ICH_VTR_EL2_LISTREGS_SHIFT 0
 264#define ICH_VTR_EL2_TDS (1U << 19)
 265#define ICH_VTR_EL2_NV4 (1U << 20)
 266#define ICH_VTR_EL2_A3V (1U << 21)
 267#define ICH_VTR_EL2_SEIS (1U << 22)
 268#define ICH_VTR_EL2_IDBITS_SHIFT 23
 269#define ICH_VTR_EL2_PREBITS_SHIFT 26
 270#define ICH_VTR_EL2_PRIBITS_SHIFT 29
 271
 272/* ITS Registers */
 273
 274FIELD(GITS_BASER, SIZE, 0, 8)
 275FIELD(GITS_BASER, PAGESIZE, 8, 2)
 276FIELD(GITS_BASER, SHAREABILITY, 10, 2)
 277FIELD(GITS_BASER, PHYADDR, 12, 36)
 278FIELD(GITS_BASER, PHYADDRL_64K, 16, 32)
 279FIELD(GITS_BASER, PHYADDRH_64K, 12, 4)
 280FIELD(GITS_BASER, ENTRYSIZE, 48, 5)
 281FIELD(GITS_BASER, OUTERCACHE, 53, 3)
 282FIELD(GITS_BASER, TYPE, 56, 3)
 283FIELD(GITS_BASER, INNERCACHE, 59, 3)
 284FIELD(GITS_BASER, INDIRECT, 62, 1)
 285FIELD(GITS_BASER, VALID, 63, 1)
 286
 287FIELD(GITS_CBASER, SIZE, 0, 8)
 288FIELD(GITS_CBASER, SHAREABILITY, 10, 2)
 289FIELD(GITS_CBASER, PHYADDR, 12, 40)
 290FIELD(GITS_CBASER, OUTERCACHE, 53, 3)
 291FIELD(GITS_CBASER, INNERCACHE, 59, 3)
 292FIELD(GITS_CBASER, VALID, 63, 1)
 293
 294FIELD(GITS_CREADR, STALLED, 0, 1)
 295FIELD(GITS_CREADR, OFFSET, 5, 15)
 296
 297FIELD(GITS_CWRITER, RETRY, 0, 1)
 298FIELD(GITS_CWRITER, OFFSET, 5, 15)
 299
 300FIELD(GITS_CTLR, ENABLED, 0, 1)
 301FIELD(GITS_CTLR, QUIESCENT, 31, 1)
 302
 303FIELD(GITS_TYPER, PHYSICAL, 0, 1)
 304FIELD(GITS_TYPER, VIRTUAL, 1, 1)
 305FIELD(GITS_TYPER, ITT_ENTRY_SIZE, 4, 4)
 306FIELD(GITS_TYPER, IDBITS, 8, 5)
 307FIELD(GITS_TYPER, DEVBITS, 13, 5)
 308FIELD(GITS_TYPER, SEIS, 18, 1)
 309FIELD(GITS_TYPER, PTA, 19, 1)
 310FIELD(GITS_TYPER, CIDBITS, 32, 4)
 311FIELD(GITS_TYPER, CIL, 36, 1)
 312FIELD(GITS_TYPER, VMOVP, 37, 1)
 313
 314#define GITS_IDREGS           0xFFD0
 315
 316#define GITS_BASER_RO_MASK                  (R_GITS_BASER_ENTRYSIZE_MASK | \
 317                                              R_GITS_BASER_TYPE_MASK)
 318
 319#define GITS_BASER_PAGESIZE_4K                0
 320#define GITS_BASER_PAGESIZE_16K               1
 321#define GITS_BASER_PAGESIZE_64K               2
 322
 323#define GITS_BASER_TYPE_DEVICE               1ULL
 324#define GITS_BASER_TYPE_VPE                  2ULL
 325#define GITS_BASER_TYPE_COLLECTION           4ULL
 326
 327#define GITS_PAGE_SIZE_4K       0x1000
 328#define GITS_PAGE_SIZE_16K      0x4000
 329#define GITS_PAGE_SIZE_64K      0x10000
 330
 331#define L1TABLE_ENTRY_SIZE         8
 332
 333#define LPI_CTE_ENABLED          TABLE_ENTRY_VALID_MASK
 334#define LPI_PRIORITY_MASK         0xfc
 335
 336#define GITS_CMDQ_ENTRY_WORDS 4
 337#define GITS_CMDQ_ENTRY_SIZE  (GITS_CMDQ_ENTRY_WORDS * sizeof(uint64_t))
 338
 339#define CMD_MASK                  0xff
 340
 341/* ITS Commands */
 342#define GITS_CMD_MOVI             0x01
 343#define GITS_CMD_INT              0x03
 344#define GITS_CMD_CLEAR            0x04
 345#define GITS_CMD_SYNC             0x05
 346#define GITS_CMD_MAPD             0x08
 347#define GITS_CMD_MAPC             0x09
 348#define GITS_CMD_MAPTI            0x0A
 349#define GITS_CMD_MAPI             0x0B
 350#define GITS_CMD_INV              0x0C
 351#define GITS_CMD_INVALL           0x0D
 352#define GITS_CMD_MOVALL           0x0E
 353#define GITS_CMD_DISCARD          0x0F
 354#define GITS_CMD_VMOVI            0x21
 355#define GITS_CMD_VMOVP            0x22
 356#define GITS_CMD_VSYNC            0x25
 357#define GITS_CMD_VMAPP            0x29
 358#define GITS_CMD_VMAPTI           0x2A
 359#define GITS_CMD_VMAPI            0x2B
 360#define GITS_CMD_VINVALL          0x2D
 361
 362/* MAPC command fields */
 363#define ICID_LENGTH                  16
 364#define ICID_MASK                 ((1U << ICID_LENGTH) - 1)
 365FIELD(MAPC, RDBASE, 16, 32)
 366
 367#define RDBASE_PROCNUM_LENGTH        16
 368#define RDBASE_PROCNUM_MASK       ((1ULL << RDBASE_PROCNUM_LENGTH) - 1)
 369
 370/* MAPD command fields */
 371#define ITTADDR_LENGTH               44
 372#define ITTADDR_SHIFT                 8
 373#define ITTADDR_MASK             MAKE_64BIT_MASK(ITTADDR_SHIFT, ITTADDR_LENGTH)
 374#define SIZE_MASK                 0x1f
 375
 376/* MAPI command fields */
 377#define EVENTID_MASK              ((1ULL << 32) - 1)
 378
 379/* MAPTI command fields */
 380#define pINTID_SHIFT                 32
 381#define pINTID_MASK               MAKE_64BIT_MASK(32, 32)
 382
 383#define DEVID_SHIFT                  32
 384#define DEVID_MASK                MAKE_64BIT_MASK(32, 32)
 385
 386#define VALID_SHIFT               63
 387#define CMD_FIELD_VALID_MASK      (1ULL << VALID_SHIFT)
 388#define L2_TABLE_VALID_MASK       CMD_FIELD_VALID_MASK
 389#define TABLE_ENTRY_VALID_MASK    (1ULL << 0)
 390
 391/* MOVALL command fields */
 392FIELD(MOVALL_2, RDBASE1, 16, 36)
 393FIELD(MOVALL_3, RDBASE2, 16, 36)
 394
 395/* MOVI command fields */
 396FIELD(MOVI_0, DEVICEID, 32, 32)
 397FIELD(MOVI_1, EVENTID, 0, 32)
 398FIELD(MOVI_2, ICID, 0, 16)
 399
 400/* INV command fields */
 401FIELD(INV_0, DEVICEID, 32, 32)
 402FIELD(INV_1, EVENTID, 0, 32)
 403
 404/* VMAPI, VMAPTI command fields */
 405FIELD(VMAPTI_0, DEVICEID, 32, 32)
 406FIELD(VMAPTI_1, EVENTID, 0, 32)
 407FIELD(VMAPTI_1, VPEID, 32, 16)
 408FIELD(VMAPTI_2, VINTID, 0, 32) /* VMAPTI only */
 409FIELD(VMAPTI_2, DOORBELL, 32, 32)
 410
 411/* VMAPP command fields */
 412FIELD(VMAPP_0, ALLOC, 8, 1) /* GICv4.1 only */
 413FIELD(VMAPP_0, PTZ, 9, 1) /* GICv4.1 only */
 414FIELD(VMAPP_0, VCONFADDR, 16, 36) /* GICv4.1 only */
 415FIELD(VMAPP_1, DEFAULT_DOORBELL, 0, 32) /* GICv4.1 only */
 416FIELD(VMAPP_1, VPEID, 32, 16)
 417FIELD(VMAPP_2, RDBASE, 16, 36)
 418FIELD(VMAPP_2, V, 63, 1)
 419FIELD(VMAPP_3, VPTSIZE, 0, 8) /* For GICv4.0, bits [7:6] are RES0 */
 420FIELD(VMAPP_3, VPTADDR, 16, 36)
 421
 422/* VMOVP command fields */
 423FIELD(VMOVP_0, SEQNUM, 32, 16) /* not used for GITS_TYPER.VMOVP == 1 */
 424FIELD(VMOVP_1, ITSLIST, 0, 16) /* not used for GITS_TYPER.VMOVP == 1 */
 425FIELD(VMOVP_1, VPEID, 32, 16)
 426FIELD(VMOVP_2, RDBASE, 16, 36)
 427FIELD(VMOVP_2, DB, 63, 1) /* GICv4.1 only */
 428FIELD(VMOVP_3, DEFAULT_DOORBELL, 0, 32) /* GICv4.1 only */
 429
 430/* VMOVI command fields */
 431FIELD(VMOVI_0, DEVICEID, 32, 32)
 432FIELD(VMOVI_1, EVENTID, 0, 32)
 433FIELD(VMOVI_1, VPEID, 32, 16)
 434FIELD(VMOVI_2, D, 0, 1)
 435FIELD(VMOVI_2, DOORBELL, 32, 32)
 436
 437/* VINVALL command fields */
 438FIELD(VINVALL_1, VPEID, 32, 16)
 439
 440/*
 441 * 12 bytes Interrupt translation Table Entry size
 442 * as per Table 5.3 in GICv3 spec
 443 * ITE Lower 8 Bytes
 444 *   Bits:    | 63 ... 48 | 47 ... 32 | 31 ... 26 | 25 ... 2 |   1     |  0    |
 445 *   Values:  | vPEID     | ICID      | unused    |  IntNum  | IntType | Valid |
 446 * ITE Higher 4 Bytes
 447 *   Bits:    | 31 ... 25 | 24 ... 0 |
 448 *   Values:  | unused    | Doorbell |
 449 * (When Doorbell is unused, as it always is for INTYPE_PHYSICAL,
 450 * the value of that field in memory cannot be relied upon -- older
 451 * versions of QEMU did not correctly write to that memory.)
 452 */
 453#define ITS_ITT_ENTRY_SIZE            0xC
 454
 455FIELD(ITE_L, VALID, 0, 1)
 456FIELD(ITE_L, INTTYPE, 1, 1)
 457FIELD(ITE_L, INTID, 2, 24)
 458FIELD(ITE_L, ICID, 32, 16)
 459FIELD(ITE_L, VPEID, 48, 16)
 460FIELD(ITE_H, DOORBELL, 0, 24)
 461
 462/* Possible values for ITE_L INTTYPE */
 463#define ITE_INTTYPE_VIRTUAL 0
 464#define ITE_INTTYPE_PHYSICAL 1
 465
 466/* 16 bits EventId */
 467#define ITS_IDBITS                   GICD_TYPER_IDBITS
 468
 469/* 16 bits DeviceId */
 470#define ITS_DEVBITS                   0xF
 471
 472/* 16 bits CollectionId */
 473#define ITS_CIDBITS                  0xF
 474
 475/*
 476 * 8 bytes Device Table Entry size
 477 * Valid = 1 bit,ITTAddr = 44 bits,Size = 5 bits
 478 */
 479#define GITS_DTE_SIZE                 (0x8ULL)
 480
 481FIELD(DTE, VALID, 0, 1)
 482FIELD(DTE, SIZE, 1, 5)
 483FIELD(DTE, ITTADDR, 6, 44)
 484
 485/*
 486 * 8 bytes Collection Table Entry size
 487 * Valid = 1 bit, RDBase = 16 bits
 488 */
 489#define GITS_CTE_SIZE                 (0x8ULL)
 490FIELD(CTE, VALID, 0, 1)
 491FIELD(CTE, RDBASE, 1, RDBASE_PROCNUM_LENGTH)
 492
 493/*
 494 * 8 bytes VPE table entry size:
 495 * Valid = 1 bit, VPTsize = 5 bits, VPTaddr = 36 bits, RDbase = 16 bits
 496 *
 497 * Field sizes for Valid and size are mandated; field sizes for RDbase
 498 * and VPT_addr are IMPDEF.
 499 */
 500#define GITS_VPE_SIZE 0x8ULL
 501
 502FIELD(VTE, VALID, 0, 1)
 503FIELD(VTE, VPTSIZE, 1, 5)
 504FIELD(VTE, VPTADDR, 6, 36)
 505FIELD(VTE, RDBASE, 42, RDBASE_PROCNUM_LENGTH)
 506
 507/* Special interrupt IDs */
 508#define INTID_SECURE 1020
 509#define INTID_NONSECURE 1021
 510#define INTID_SPURIOUS 1023
 511
 512/* Functions internal to the emulated GICv3 */
 513
 514/**
 515 * gicv3_redist_size:
 516 * @s: GICv3State
 517 *
 518 * Return the size of the redistributor register frame in bytes
 519 * (which depends on what GIC version this is)
 520 */
 521static inline int gicv3_redist_size(GICv3State *s)
 522{
 523    /*
 524     * Redistributor size is controlled by the redistributor GICR_TYPER.VLPIS.
 525     * It's the same for every redistributor in the GIC, so arbitrarily
 526     * use the register field in the first one.
 527     */
 528    if (s->cpu[0].gicr_typer & GICR_TYPER_VLPIS) {
 529        return GICV4_REDIST_SIZE;
 530    } else {
 531        return GICV3_REDIST_SIZE;
 532    }
 533}
 534
 535/**
 536 * gicv3_intid_is_special:
 537 * @intid: interrupt ID
 538 *
 539 * Return true if @intid is a special interrupt ID (1020 to
 540 * 1023 inclusive). This corresponds to the GIC spec pseudocode
 541 * IsSpecial() function.
 542 */
 543static inline bool gicv3_intid_is_special(int intid)
 544{
 545    return intid >= INTID_SECURE && intid <= INTID_SPURIOUS;
 546}
 547
 548/**
 549 * gicv3_redist_update:
 550 * @cs: GICv3CPUState for this redistributor
 551 *
 552 * Recalculate the highest priority pending interrupt after a
 553 * change to redistributor state, and inform the CPU accordingly.
 554 */
 555void gicv3_redist_update(GICv3CPUState *cs);
 556
 557/**
 558 * gicv3_update:
 559 * @s: GICv3State
 560 * @start: first interrupt whose state changed
 561 * @len: length of the range of interrupts whose state changed
 562 *
 563 * Recalculate the highest priority pending interrupts after a
 564 * change to the distributor state affecting @len interrupts
 565 * starting at @start, and inform the CPUs accordingly.
 566 */
 567void gicv3_update(GICv3State *s, int start, int len);
 568
 569/**
 570 * gicv3_full_update_noirqset:
 571 * @s: GICv3State
 572 *
 573 * Recalculate the cached information about highest priority
 574 * pending interrupts, but don't inform the CPUs. This should be
 575 * called after an incoming migration has loaded new state.
 576 */
 577void gicv3_full_update_noirqset(GICv3State *s);
 578
 579/**
 580 * gicv3_full_update:
 581 * @s: GICv3State
 582 *
 583 * Recalculate the highest priority pending interrupts after
 584 * a change that could affect the status of all interrupts,
 585 * and inform the CPUs accordingly.
 586 */
 587void gicv3_full_update(GICv3State *s);
 588MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data,
 589                            unsigned size, MemTxAttrs attrs);
 590MemTxResult gicv3_dist_write(void *opaque, hwaddr addr, uint64_t data,
 591                             unsigned size, MemTxAttrs attrs);
 592MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,
 593                              unsigned size, MemTxAttrs attrs);
 594MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data,
 595                               unsigned size, MemTxAttrs attrs);
 596void gicv3_dist_set_irq(GICv3State *s, int irq, int level);
 597void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level);
 598void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level);
 599/**
 600 * gicv3_redist_process_vlpi:
 601 * @cs: GICv3CPUState
 602 * @irq: (virtual) interrupt number
 603 * @vptaddr: (guest) address of VLPI table
 604 * @doorbell: doorbell (physical) interrupt number (1023 for "no doorbell")
 605 * @level: level to set @irq to
 606 *
 607 * Process a virtual LPI being directly injected by the ITS. This function
 608 * will update the VLPI table specified by @vptaddr and @vptsize. If the
 609 * vCPU corresponding to that VLPI table is currently running on
 610 * the CPU associated with this redistributor, directly inject the VLPI
 611 * @irq. If the vCPU is not running on this CPU, raise the doorbell
 612 * interrupt instead.
 613 */
 614void gicv3_redist_process_vlpi(GICv3CPUState *cs, int irq, uint64_t vptaddr,
 615                               int doorbell, int level);
 616/**
 617 * gicv3_redist_vlpi_pending:
 618 * @cs: GICv3CPUState
 619 * @irq: (virtual) interrupt number
 620 * @level: level to set @irq to
 621 *
 622 * Set/clear the pending status of a virtual LPI in the vLPI table
 623 * that this redistributor is currently using. (The difference between
 624 * this and gicv3_redist_process_vlpi() is that this is called from
 625 * the cpuif and does not need to do the not-running-on-this-vcpu checks.)
 626 */
 627void gicv3_redist_vlpi_pending(GICv3CPUState *cs, int irq, int level);
 628
 629void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level);
 630/**
 631 * gicv3_redist_update_lpi:
 632 * @cs: GICv3CPUState
 633 *
 634 * Scan the LPI pending table and recalculate the highest priority
 635 * pending LPI and also the overall highest priority pending interrupt.
 636 */
 637void gicv3_redist_update_lpi(GICv3CPUState *cs);
 638/**
 639 * gicv3_redist_update_lpi_only:
 640 * @cs: GICv3CPUState
 641 *
 642 * Scan the LPI pending table and recalculate cs->hpplpi only,
 643 * without calling gicv3_redist_update() to recalculate the overall
 644 * highest priority pending interrupt. This should be called after
 645 * an incoming migration has loaded new state.
 646 */
 647void gicv3_redist_update_lpi_only(GICv3CPUState *cs);
 648/**
 649 * gicv3_redist_inv_lpi:
 650 * @cs: GICv3CPUState
 651 * @irq: LPI to invalidate cached information for
 652 *
 653 * Forget or update any cached information associated with this LPI.
 654 */
 655void gicv3_redist_inv_lpi(GICv3CPUState *cs, int irq);
 656/**
 657 * gicv3_redist_inv_vlpi:
 658 * @cs: GICv3CPUState
 659 * @irq: vLPI to invalidate cached information for
 660 * @vptaddr: (guest) address of vLPI table
 661 *
 662 * Forget or update any cached information associated with this vLPI.
 663 */
 664void gicv3_redist_inv_vlpi(GICv3CPUState *cs, int irq, uint64_t vptaddr);
 665/**
 666 * gicv3_redist_mov_lpi:
 667 * @src: source redistributor
 668 * @dest: destination redistributor
 669 * @irq: LPI to update
 670 *
 671 * Move the pending state of the specified LPI from @src to @dest,
 672 * as required by the ITS MOVI command.
 673 */
 674void gicv3_redist_mov_lpi(GICv3CPUState *src, GICv3CPUState *dest, int irq);
 675/**
 676 * gicv3_redist_movall_lpis:
 677 * @src: source redistributor
 678 * @dest: destination redistributor
 679 *
 680 * Scan the LPI pending table for @src, and for each pending LPI there
 681 * mark it as not-pending for @src and pending for @dest, as required
 682 * by the ITS MOVALL command.
 683 */
 684void gicv3_redist_movall_lpis(GICv3CPUState *src, GICv3CPUState *dest);
 685/**
 686 * gicv3_redist_mov_vlpi:
 687 * @src: source redistributor
 688 * @src_vptaddr: (guest) address of source VLPI table
 689 * @dest: destination redistributor
 690 * @dest_vptaddr: (guest) address of destination VLPI table
 691 * @irq: VLPI to update
 692 * @doorbell: doorbell for destination (1023 for "no doorbell")
 693 *
 694 * Move the pending state of the specified VLPI from @src to @dest,
 695 * as required by the ITS VMOVI command.
 696 */
 697void gicv3_redist_mov_vlpi(GICv3CPUState *src, uint64_t src_vptaddr,
 698                           GICv3CPUState *dest, uint64_t dest_vptaddr,
 699                           int irq, int doorbell);
 700/**
 701 * gicv3_redist_vinvall:
 702 * @cs: GICv3CPUState
 703 * @vptaddr: address of VLPI pending table
 704 *
 705 * On redistributor @cs, invalidate all cached information associated
 706 * with the vCPU defined by @vptaddr.
 707 */
 708void gicv3_redist_vinvall(GICv3CPUState *cs, uint64_t vptaddr);
 709
 710void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns);
 711void gicv3_init_cpuif(GICv3State *s);
 712
 713/**
 714 * gicv3_cpuif_update:
 715 * @cs: GICv3CPUState for the CPU to update
 716 *
 717 * Recalculate whether to assert the IRQ or FIQ lines after a change
 718 * to the current highest priority pending interrupt, the CPU's
 719 * current running priority or the CPU's current exception level or
 720 * security state.
 721 */
 722void gicv3_cpuif_update(GICv3CPUState *cs);
 723
 724/*
 725 * gicv3_cpuif_virt_irq_fiq_update:
 726 * @cs: GICv3CPUState for the CPU to update
 727 *
 728 * Recalculate whether to assert the virtual IRQ or FIQ lines after
 729 * a change to the current highest priority pending virtual interrupt.
 730 * Note that this does not recalculate and change the maintenance
 731 * interrupt status (for that, see gicv3_cpuif_virt_update()).
 732 */
 733void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs);
 734
 735static inline uint32_t gicv3_iidr(void)
 736{
 737    /* Return the Implementer Identification Register value
 738     * for the emulated GICv3, as reported in GICD_IIDR and GICR_IIDR.
 739     *
 740     * We claim to be an ARM r0p0 with a zero ProductID.
 741     * This is the same as an r0p0 GIC-500.
 742     */
 743    return 0x43b;
 744}
 745
 746/* CoreSight PIDR0 values for ARM GICv3 implementations */
 747#define GICV3_PIDR0_DIST 0x92
 748#define GICV3_PIDR0_REDIST 0x93
 749#define GICV3_PIDR0_ITS 0x94
 750
 751static inline uint32_t gicv3_idreg(GICv3State *s, int regoffset, uint8_t pidr0)
 752{
 753    /* Return the value of the CoreSight ID register at the specified
 754     * offset from the first ID register (as found in the distributor
 755     * and redistributor register banks).
 756     * These values indicate an ARM implementation of a GICv3 or v4.
 757     */
 758    static const uint8_t gicd_ids[] = {
 759        0x44, 0x00, 0x00, 0x00, 0x92, 0xB4, 0x0B, 0x00, 0x0D, 0xF0, 0x05, 0xB1
 760    };
 761    uint32_t id;
 762
 763    regoffset /= 4;
 764
 765    if (regoffset == 4) {
 766        return pidr0;
 767    }
 768    id = gicd_ids[regoffset];
 769    if (regoffset == 6) {
 770        /* PIDR2 bits [7:4] are the GIC architecture revision */
 771        id |= s->revision << 4;
 772    }
 773    return id;
 774}
 775
 776/**
 777 * gicv3_irq_group:
 778 *
 779 * Return the group which this interrupt is configured as (GICV3_G0,
 780 * GICV3_G1 or GICV3_G1NS).
 781 */
 782static inline int gicv3_irq_group(GICv3State *s, GICv3CPUState *cs, int irq)
 783{
 784    bool grpbit, grpmodbit;
 785
 786    if (irq < GIC_INTERNAL) {
 787        grpbit = extract32(cs->gicr_igroupr0, irq, 1);
 788        grpmodbit = extract32(cs->gicr_igrpmodr0, irq, 1);
 789    } else {
 790        grpbit = gicv3_gicd_group_test(s, irq);
 791        grpmodbit = gicv3_gicd_grpmod_test(s, irq);
 792    }
 793    if (grpbit) {
 794        return GICV3_G1NS;
 795    }
 796    if (s->gicd_ctlr & GICD_CTLR_DS) {
 797        return GICV3_G0;
 798    }
 799    return grpmodbit ? GICV3_G1 : GICV3_G0;
 800}
 801
 802/**
 803 * gicv3_redist_affid:
 804 *
 805 * Return the 32-bit affinity ID of the CPU connected to this redistributor
 806 */
 807static inline uint32_t gicv3_redist_affid(GICv3CPUState *cs)
 808{
 809    return cs->gicr_typer >> 32;
 810}
 811
 812/**
 813 * gicv3_cache_target_cpustate:
 814 *
 815 * Update the cached CPU state corresponding to the target for this interrupt
 816 * (which is kept in s->gicd_irouter_target[]).
 817 */
 818static inline void gicv3_cache_target_cpustate(GICv3State *s, int irq)
 819{
 820    GICv3CPUState *cs = NULL;
 821    int i;
 822    uint32_t tgtaff = extract64(s->gicd_irouter[irq], 0, 24) |
 823        extract64(s->gicd_irouter[irq], 32, 8) << 24;
 824
 825    for (i = 0; i < s->num_cpu; i++) {
 826        if (s->cpu[i].gicr_typer >> 32 == tgtaff) {
 827            cs = &s->cpu[i];
 828            break;
 829        }
 830    }
 831
 832    s->gicd_irouter_target[irq] = cs;
 833}
 834
 835/**
 836 * gicv3_cache_all_target_cpustates:
 837 *
 838 * Populate the entire cache of CPU state pointers for interrupt targets
 839 * (eg after inbound migration or CPU reset)
 840 */
 841static inline void gicv3_cache_all_target_cpustates(GICv3State *s)
 842{
 843    int irq;
 844
 845    for (irq = GIC_INTERNAL; irq < GICV3_MAXIRQ; irq++) {
 846        gicv3_cache_target_cpustate(s, irq);
 847    }
 848}
 849
 850void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s);
 851
 852#endif /* QEMU_ARM_GICV3_INTERNAL_H */
 853