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10#ifndef PPC_PNV_XIVE2_REGS_H
11#define PPC_PNV_XIVE2_REGS_H
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16
17
18#define X_CQ_XIVE_CAP 0x02
19#define CQ_XIVE_CAP 0x010
20#define CQ_XIVE_CAP_VERSION PPC_BITMASK(0, 3)
21
22#define CQ_XIVE_CAP_USER_INT_PRIO PPC_BITMASK(8, 9)
23#define CQ_XIVE_CAP_USER_INT_PRIO_1 0
24#define CQ_XIVE_CAP_USER_INT_PRIO_1_2 1
25#define CQ_XIVE_CAP_USER_INT_PRIO_1_4 2
26#define CQ_XIVE_CAP_USER_INT_PRIO_1_8 3
27#define CQ_XIVE_CAP_VP_INT_PRIO PPC_BITMASK(10, 11)
28#define CQ_XIVE_CAP_VP_INT_PRIO_1_8 0
29#define CQ_XIVE_CAP_VP_INT_PRIO_2_8 1
30#define CQ_XIVE_CAP_VP_INT_PRIO_4_8 2
31#define CQ_XIVE_CAP_VP_INT_PRIO_8 3
32#define CQ_XIVE_CAP_BLOCK_ID_WIDTH PPC_BITMASK(12, 13)
33#define CQ_XIVE_CAP_VP_SAVE_RESTORE PPC_BIT(38)
34
35#define CQ_XIVE_CAP_PHB_PQ_DISABLE PPC_BIT(56)
36#define CQ_XIVE_CAP_PHB_ABT PPC_BIT(57)
37#define CQ_XIVE_CAP_EXPLOITATION_MODE PPC_BIT(58)
38#define CQ_XIVE_CAP_STORE_EOI PPC_BIT(59)
39
40
41#define X_CQ_XIVE_CFG 0x03
42#define CQ_XIVE_CFG 0x018
43
44
45#define CQ_XIVE_CFG_USER_INT_PRIO PPC_BITMASK(8, 9)
46#define CQ_XIVE_CFG_VP_INT_PRIO PPC_BITMASK(10, 11)
47#define CQ_XIVE_CFG_INT_PRIO_1 0
48#define CQ_XIVE_CFG_INT_PRIO_2 1
49#define CQ_XIVE_CFG_INT_PRIO_4 2
50#define CQ_XIVE_CFG_INT_PRIO_8 3
51#define CQ_XIVE_CFG_BLOCK_ID_WIDTH PPC_BITMASK(12, 13)
52#define CQ_XIVE_CFG_BLOCK_ID_4BITS 0
53#define CQ_XIVE_CFG_BLOCK_ID_5BITS 1
54#define CQ_XIVE_CFG_BLOCK_ID_6BITS 2
55#define CQ_XIVE_CFG_BLOCK_ID_7BITS 3
56#define CQ_XIVE_CFG_HYP_HARD_RANGE PPC_BITMASK(14, 15)
57#define CQ_XIVE_CFG_THREADID_7BITS 0
58#define CQ_XIVE_CFG_THREADID_8BITS 1
59#define CQ_XIVE_CFG_THREADID_9BITS 2
60#define CQ_XIVE_CFG_THREADID_10BITs 3
61#define CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE PPC_BIT(16)
62#define CQ_XIVE_CFG_HYP_HARD_BLOCK_ID PPC_BITMASK(17, 23)
63
64#define CQ_XIVE_CFG_GEN1_TIMA_OS PPC_BIT(24)
65#define CQ_XIVE_CFG_GEN1_TIMA_HYP PPC_BIT(25)
66#define CQ_XIVE_CFG_GEN1_TIMA_HYP_BLK0 PPC_BIT(26)
67#define CQ_XIVE_CFG_GEN1_TIMA_CROWD_DIS PPC_BIT(27)
68#define CQ_XIVE_CFG_GEN1_END_ESX PPC_BIT(28)
69#define CQ_XIVE_CFG_EN_VP_SAVE_RESTORE PPC_BIT(38)
70#define CQ_XIVE_CFG_EN_VP_SAVE_REST_STRICT PPC_BIT(39)
71
72
73#define X_CQ_IC_BAR 0x08
74#define CQ_IC_BAR 0x040
75#define CQ_IC_BAR_VALID PPC_BIT(0)
76#define CQ_IC_BAR_64K PPC_BIT(1)
77
78#define CQ_IC_BAR_ADDR PPC_BITMASK(8, 42)
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81
82#define X_CQ_TM_BAR 0x09
83#define CQ_TM_BAR 0x048
84#define CQ_TM_BAR_VALID PPC_BIT(0)
85#define CQ_TM_BAR_64K PPC_BIT(1)
86#define CQ_TM_BAR_ADDR PPC_BITMASK(8, 49)
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88
89#define X_CQ_ESB_BAR 0x0A
90#define CQ_ESB_BAR 0x050
91#define CQ_BAR_VALID PPC_BIT(0)
92#define CQ_BAR_64K PPC_BIT(1)
93
94#define CQ_BAR_ADDR PPC_BITMASK(8, 39)
95#define CQ_BAR_SET_DIV PPC_BITMASK(56, 58)
96#define CQ_BAR_RANGE PPC_BITMASK(59, 63)
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99
100#define X_CQ_END_BAR 0x0B
101#define CQ_END_BAR 0x058
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104#define X_CQ_NVPG_BAR 0x0C
105#define CQ_NVPG_BAR 0x060
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108#define X_CQ_NVC_BAR 0x0D
109#define CQ_NVC_BAR 0x068
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112#define X_CQ_TAR 0x0E
113#define CQ_TAR 0x070
114#define CQ_TAR_AUTOINC PPC_BIT(0)
115#define CQ_TAR_SELECT PPC_BITMASK(12, 15)
116#define CQ_TAR_ESB 0
117#define CQ_TAR_END 2
118#define CQ_TAR_NVPG 3
119#define CQ_TAR_NVC 5
120#define CQ_TAR_ENTRY_SELECT PPC_BITMASK(28, 31)
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122
123#define X_CQ_TDR 0x0F
124#define CQ_TDR 0x078
125
126#define CQ_TDR_VALID PPC_BIT(0)
127#define CQ_TDR_BLOCK_ID PPC_BITMASK(60, 63)
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134#define X_CQ_MSGSND 0x10
135#define CQ_MSGSND 0x080
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137
138#define X_CQ_RST_CTL 0x12
139#define CQ_RST_CTL 0x090
140#define CQ_RST_SYNC_RESET PPC_BIT(0)
141#define CQ_RST_QUIESCE_PB PPC_BIT(1)
142#define CQ_RST_MASTER_IDLE PPC_BIT(2)
143#define CQ_RST_SAVE_IDLE PPC_BIT(3)
144#define CQ_RST_PB_BAR_RESET PPC_BIT(4)
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146
147#define X_CQ_CFG_PB_GEN 0x14
148#define CQ_CFG_PB_GEN 0x0A0
149#define CQ_CFG_PB_GEN_PB_INIT PPC_BIT(45)
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156#define X_CQ_FIR 0x30
157#define X_CQ_FIR_AND 0x31
158#define X_CQ_FIR_OR 0x32
159#define CQ_FIR 0x180
160#define CQ_FIR_AND 0x188
161#define CQ_FIR_OR 0x190
162#define CQ_FIR_PB_RCMDX_CI_ERR1 PPC_BIT(19)
163#define CQ_FIR_VC_INFO_ERROR_0_2 PPC_BITMASK(61, 63)
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170#define X_CQ_FIRMASK 0x33
171#define X_CQ_FIRMASK_AND 0x34
172#define X_CQ_FIRMASK_OR 0x35
173#define CQ_FIRMASK 0x198
174#define CQ_FIRMASK_AND 0x1A0
175#define CQ_FIRMASK_OR 0x1A8
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181
182#define X_VC_VSD_TABLE_ADDR 0x100
183#define VC_VSD_TABLE_ADDR 0x000
184#define VC_VSD_TABLE_AUTOINC PPC_BIT(0)
185#define VC_VSD_TABLE_SELECT PPC_BITMASK(12, 15)
186#define VC_VSD_TABLE_ADDRESS PPC_BITMASK(28, 31)
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188
189#define X_VC_VSD_TABLE_DATA 0x101
190#define VC_VSD_TABLE_DATA 0x008
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193#define X_VC_AT_MACRO_KILL 0x102
194#define VC_AT_MACRO_KILL 0x010
195#define VC_AT_MACRO_KILL_VALID PPC_BIT(0)
196#define VC_AT_MACRO_KILL_VSD PPC_BITMASK(12, 15)
197#define VC_AT_MACRO_KILL_BLOCK_ID PPC_BITMASK(28, 31)
198#define VC_AT_MACRO_KILL_OFFSET PPC_BITMASK(48, 60)
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200
201#define X_VC_AT_MACRO_KILL_MASK 0x103
202#define VC_AT_MACRO_KILL_MASK 0x018
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204
205#define X_VC_QUEUES_CFG_REM0 0x117
206
207#define VC_QUEUES_CFG_REM0 0x0B8
208#define VC_QUEUES_CFG_REM1 0x0C0
209#define VC_QUEUES_CFG_REM2 0x0C8
210#define VC_QUEUES_CFG_REM3 0x0D0
211#define VC_QUEUES_CFG_REM4 0x0D8
212#define VC_QUEUES_CFG_REM5 0x0E0
213#define VC_QUEUES_CFG_REM6 0x0E8
214#define VC_QUEUES_CFG_MEMB_EN PPC_BIT(38)
215#define VC_QUEUES_CFG_MEMB_SZ PPC_BITMASK(42, 47)
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222#define X_VC_ESBC_FLUSH_CTRL 0x140
223#define VC_ESBC_FLUSH_CTRL 0x200
224#define VC_ESBC_FLUSH_CTRL_POLL_VALID PPC_BIT(0)
225#define VC_ESBC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2)
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227
228#define X_VC_ESBC_FLUSH_POLL 0x141
229#define VC_ESBC_FLUSH_POLL 0x208
230#define VC_ESBC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(0, 3)
231#define VC_ESBC_FLUSH_POLL_OFFSET PPC_BITMASK(4, 31)
232#define VC_ESBC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(32, 35)
233#define VC_ESBC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(36, 63)
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235
236#define X_VC_EASC_FLUSH_CTRL 0x160
237#define VC_EASC_FLUSH_CTRL 0x300
238#define VC_EASC_FLUSH_CTRL_POLL_VALID PPC_BIT(0)
239#define VC_EASC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2)
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241
242#define X_VC_EASC_FLUSH_POLL 0x161
243#define VC_EASC_FLUSH_POLL 0x308
244#define VC_EASC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(0, 3)
245#define VC_EASC_FLUSH_POLL_OFFSET PPC_BITMASK(4, 31)
246#define VC_EASC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(32, 35)
247#define VC_EASC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(36, 63)
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254#define X_VC_ENDC_FLUSH_CTRL 0x180
255#define VC_ENDC_FLUSH_CTRL 0x400
256#define VC_ENDC_FLUSH_CTRL_POLL_VALID PPC_BIT(0)
257#define VC_ENDC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2)
258#define VC_ENDC_FLUSH_CTRL_WANT_INVALIDATE PPC_BIT(3)
259#define VC_ENDC_FLUSH_CTRL_INJECT_INVALIDATE PPC_BIT(7)
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261
262#define X_VC_ENDC_FLUSH_POLL 0x181
263#define VC_ENDC_FLUSH_POLL 0x408
264#define VC_ENDC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(4, 7)
265#define VC_ENDC_FLUSH_POLL_OFFSET PPC_BITMASK(8, 31)
266#define VC_ENDC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(36, 39)
267#define VC_ENDC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(40, 63)
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270#define X_VC_ENDC_SYNC_DONE 0x184
271#define VC_ENDC_SYNC_DONE 0x420
272#define VC_ENDC_SYNC_POLL_DONE PPC_BITMASK(0, 6)
273#define VC_ENDC_SYNC_QUEUE_IPI PPC_BIT(0)
274#define VC_ENDC_SYNC_QUEUE_HWD PPC_BIT(1)
275#define VC_ENDC_SYNC_QUEUE_NXC PPC_BIT(2)
276#define VC_ENDC_SYNC_QUEUE_INT PPC_BIT(3)
277#define VC_ENDC_SYNC_QUEUE_OS PPC_BIT(4)
278#define VC_ENDC_SYNC_QUEUE_POOL PPC_BIT(5)
279#define VC_ENDC_SYNC_QUEUE_HARD PPC_BIT(6)
280#define VC_QUEUE_COUNT 7
281
282
283#define X_VC_ENDC_WATCH0_SPEC 0x1A0
284#define VC_ENDC_WATCH0_SPEC 0x500
285#define VC_ENDC_WATCH_CONFLICT PPC_BIT(0)
286#define VC_ENDC_WATCH_FULL PPC_BIT(8)
287#define VC_ENDC_WATCH_BLOCK_ID PPC_BITMASK(28, 31)
288#define VC_ENDC_WATCH_INDEX PPC_BITMASK(40, 63)
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291#define X_VC_ENDC_WATCH0_DATA0 0x1A4
292#define X_VC_ENDC_WATCH0_DATA1 0x1A5
293#define X_VC_ENDC_WATCH0_DATA2 0x1A6
294#define X_VC_ENDC_WATCH0_DATA3 0x1A7
295
296#define VC_ENDC_WATCH0_DATA0 0x520
297#define VC_ENDC_WATCH0_DATA1 0x528
298#define VC_ENDC_WATCH0_DATA2 0x530
299#define VC_ENDC_WATCH0_DATA3 0x538
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306#define X_PC_VSD_TABLE_ADDR 0x200
307#define PC_VSD_TABLE_ADDR 0x000
308#define PC_VSD_TABLE_AUTOINC PPC_BIT(0)
309#define PC_VSD_TABLE_SELECT PPC_BITMASK(12, 15)
310#define PC_VSD_TABLE_ADDRESS PPC_BITMASK(28, 31)
311
312
313#define X_PC_VSD_TABLE_DATA 0x201
314#define PC_VSD_TABLE_DATA 0x008
315
316
317#define X_PC_AT_KILL 0x202
318#define PC_AT_KILL 0x010
319#define PC_AT_KILL_VALID PPC_BIT(0)
320#define PC_AT_KILL_VSD_TYPE PPC_BITMASK(24, 27)
321
322#define PC_AT_KILL_BLOCK_ID PPC_BITMASK(28, 31)
323#define PC_AT_KILL_OFFSET PPC_BITMASK(48, 60)
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325
326#define X_PC_AT_KILL_MASK 0x203
327#define PC_AT_KILL_MASK 0x018
328#define PC_AT_KILL_MASK_VSD_TYPE PPC_BITMASK(24, 27)
329#define PC_AT_KILL_MASK_BLOCK_ID PPC_BITMASK(28, 31)
330#define PC_AT_KILL_MASK_OFFSET PPC_BITMASK(48, 60)
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336
337#define X_PC_NXC_FLUSH_CTRL 0x280
338#define PC_NXC_FLUSH_CTRL 0x400
339#define PC_NXC_FLUSH_CTRL_POLL_VALID PPC_BIT(0)
340#define PC_NXC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2)
341#define PC_NXC_FLUSH_CTRL_WANT_INVALIDATE PPC_BIT(3)
342#define PC_NXC_FLUSH_CTRL_INJECT_INVALIDATE PPC_BIT(7)
343
344
345#define X_PC_NXC_FLUSH_POLL 0x281
346#define PC_NXC_FLUSH_POLL 0x408
347#define PC_NXC_FLUSH_POLL_NXC_TYPE PPC_BITMASK(2, 3)
348#define PC_NXC_FLUSH_POLL_NXC_TYPE_NVP 0
349#define PC_NXC_FLUSH_POLL_NXC_TYPE_NVG 2
350#define PC_NXC_FLUSH_POLL_NXC_TYPE_NVC 3
351#define PC_NXC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(4, 7)
352#define PC_NXC_FLUSH_POLL_OFFSET PPC_BITMASK(8, 31)
353#define PC_NXC_FLUSH_POLL_NXC_TYPE_MASK PPC_BITMASK(34, 35)
354#define PC_NXC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(36, 39)
355#define PC_NXC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(40, 63)
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357
358#define X_PC_NXC_WATCH0_SPEC 0x2A0
359#define PC_NXC_WATCH0_SPEC 0x500
360#define PC_NXC_WATCH_CONFLICT PPC_BIT(0)
361#define PC_NXC_WATCH_FULL PPC_BIT(8)
362#define PC_NXC_WATCH_NXC_TYPE PPC_BITMASK(26, 27)
363#define PC_NXC_WATCH_NXC_NVP 0
364#define PC_NXC_WATCH_NXC_NVG 2
365#define PC_NXC_WATCH_NXC_NVC 3
366#define PC_NXC_WATCH_BLOCK_ID PPC_BITMASK(28, 31)
367#define PC_NXC_WATCH_INDEX PPC_BITMASK(40, 63)
368
369
370#define X_PC_NXC_WATCH0_DATA0 0x2A4
371#define X_PC_NXC_WATCH0_DATA1 0x2A5
372#define X_PC_NXC_WATCH0_DATA2 0x2A6
373#define X_PC_NXC_WATCH0_DATA3 0x2A7
374
375#define PC_NXC_WATCH0_DATA0 0x520
376#define PC_NXC_WATCH0_DATA1 0x528
377#define PC_NXC_WATCH0_DATA2 0x530
378#define PC_NXC_WATCH0_DATA3 0x538
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385#define X_TCTXT_EN0 0x300
386#define TCTXT_EN0 0x000
387
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389#define X_TCTXT_EN0_SET 0x302
390#define TCTXT_EN0_SET 0x010
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393#define X_TCTXT_EN0_RESET 0x303
394#define TCTXT_EN0_RESET 0x018
395
396
397#define X_TCTXT_EN1 0x304
398#define TCTXT_EN1 0x020
399
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401#define X_TCTXT_EN1_SET 0x306
402#define TCTXT_EN1_SET 0x030
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404
405#define X_TCTXT_EN1_RESET 0x307
406#define TCTXT_EN1_RESET 0x038
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411#define VST_ESB 0
412#define VST_EAS 1
413#define VST_END 2
414#define VST_NVP 3
415#define VST_NVG 4
416#define VST_NVC 5
417#define VST_IC 6
418#define VST_SYNC 7
419#define VST_ERQ 8
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429
430#define VSD_MODE PPC_BITMASK(0, 1)
431#define VSD_MODE_SHARED 1
432#define VSD_MODE_EXCLUSIVE 2
433#define VSD_MODE_FORWARD 3
434#define VSD_FIRMWARE PPC_BIT(2)
435#define VSD_FIRMWARE2 PPC_BIT(3)
436#define VSD_RESERVED PPC_BITMASK(4, 7)
437#define VSD_ADDRESS_MASK 0x00fffffffffff000ull
438#define VSD_MIGRATION_REG PPC_BITMASK(52, 55)
439#define VSD_INDIRECT PPC_BIT(56)
440#define VSD_TSIZE PPC_BITMASK(59, 63)
441
442#endif
443