1
2
3
4
5
6
7
8
9#include "qemu/osdep.h"
10#include "qemu/log.h"
11#include "qapi/visitor.h"
12#include "qapi/error.h"
13#include "monitor/monitor.h"
14#include "target/ppc/cpu.h"
15#include "hw/pci-host/pnv_phb4_regs.h"
16#include "hw/pci-host/pnv_phb4.h"
17#include "hw/pci/pcie_host.h"
18#include "hw/pci/pcie_port.h"
19#include "hw/ppc/pnv.h"
20#include "hw/ppc/pnv_xscom.h"
21#include "hw/irq.h"
22#include "hw/qdev-properties.h"
23#include "qom/object.h"
24#include "trace.h"
25
26#define phb_error(phb, fmt, ...) \
27 qemu_log_mask(LOG_GUEST_ERROR, "phb4[%d:%d]: " fmt "\n", \
28 (phb)->chip_id, (phb)->phb_id, ## __VA_ARGS__)
29
30#define phb_pec_error(pec, fmt, ...) \
31 qemu_log_mask(LOG_GUEST_ERROR, "phb4_pec[%d:%d]: " fmt "\n", \
32 (pec)->chip_id, (pec)->index, ## __VA_ARGS__)
33
34static PCIDevice *pnv_phb4_find_cfg_dev(PnvPHB4 *phb)
35{
36 PCIHostState *pci = PCI_HOST_BRIDGE(phb);
37 uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3];
38 uint8_t bus, devfn;
39
40 if (!(addr >> 63)) {
41 return NULL;
42 }
43 bus = (addr >> 52) & 0xff;
44 devfn = (addr >> 44) & 0xff;
45
46
47 if (bus == 0 && devfn == 0) {
48 return NULL;
49 }
50 return pci_find_device(pci->bus, bus, devfn);
51}
52
53
54
55
56
57static void pnv_phb4_config_write(PnvPHB4 *phb, unsigned off,
58 unsigned size, uint64_t val)
59{
60 uint32_t cfg_addr, limit;
61 PCIDevice *pdev;
62
63 pdev = pnv_phb4_find_cfg_dev(phb);
64 if (!pdev) {
65 return;
66 }
67 cfg_addr = (phb->regs[PHB_CONFIG_ADDRESS >> 3] >> 32) & 0xffc;
68 cfg_addr |= off;
69 limit = pci_config_size(pdev);
70 if (limit <= cfg_addr) {
71
72
73
74
75 return;
76 }
77 switch (size) {
78 case 1:
79 break;
80 case 2:
81 val = bswap16(val);
82 break;
83 case 4:
84 val = bswap32(val);
85 break;
86 default:
87 g_assert_not_reached();
88 }
89 pci_host_config_write_common(pdev, cfg_addr, limit, val, size);
90}
91
92static uint64_t pnv_phb4_config_read(PnvPHB4 *phb, unsigned off,
93 unsigned size)
94{
95 uint32_t cfg_addr, limit;
96 PCIDevice *pdev;
97 uint64_t val;
98
99 pdev = pnv_phb4_find_cfg_dev(phb);
100 if (!pdev) {
101 return ~0ull;
102 }
103 cfg_addr = (phb->regs[PHB_CONFIG_ADDRESS >> 3] >> 32) & 0xffc;
104 cfg_addr |= off;
105 limit = pci_config_size(pdev);
106 if (limit <= cfg_addr) {
107
108
109
110
111 return ~0ull;
112 }
113 val = pci_host_config_read_common(pdev, cfg_addr, limit, size);
114 switch (size) {
115 case 1:
116 return val;
117 case 2:
118 return bswap16(val);
119 case 4:
120 return bswap32(val);
121 default:
122 g_assert_not_reached();
123 }
124}
125
126
127
128
129static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off,
130 unsigned size, uint64_t val)
131{
132 PCIHostState *pci = PCI_HOST_BRIDGE(phb);
133 PCIDevice *pdev;
134
135 if (size != 4) {
136 phb_error(phb, "rc_config_write invalid size %d\n", size);
137 return;
138 }
139
140 pdev = pci_find_device(pci->bus, 0, 0);
141 if (!pdev) {
142 phb_error(phb, "rc_config_write device not found\n");
143 return;
144 }
145
146 pci_host_config_write_common(pdev, off, PHB_RC_CONFIG_SIZE,
147 bswap32(val), 4);
148}
149
150static uint64_t pnv_phb4_rc_config_read(PnvPHB4 *phb, unsigned off,
151 unsigned size)
152{
153 PCIHostState *pci = PCI_HOST_BRIDGE(phb);
154 PCIDevice *pdev;
155 uint64_t val;
156
157 if (size != 4) {
158 phb_error(phb, "rc_config_read invalid size %d\n", size);
159 return ~0ull;
160 }
161
162 pdev = pci_find_device(pci->bus, 0, 0);
163 if (!pdev) {
164 phb_error(phb, "rc_config_read device not found\n");
165 return ~0ull;
166 }
167
168 val = pci_host_config_read_common(pdev, off, PHB_RC_CONFIG_SIZE, 4);
169 return bswap32(val);
170}
171
172static void pnv_phb4_check_mbt(PnvPHB4 *phb, uint32_t index)
173{
174 uint64_t base, start, size, mbe0, mbe1;
175 MemoryRegion *parent;
176 char name[64];
177
178
179 if (memory_region_is_mapped(&phb->mr_mmio[index])) {
180
181 memory_region_del_subregion(phb->mr_mmio[index].container,
182 &phb->mr_mmio[index]);
183 }
184
185
186 mbe0 = phb->ioda_MBT[(index << 1)];
187 mbe1 = phb->ioda_MBT[(index << 1) + 1];
188
189 if (!(mbe0 & IODA3_MBT0_ENABLE)) {
190 return;
191 }
192
193
194 base = GETFIELD(IODA3_MBT0_BASE_ADDR, mbe0) << 12;
195 size = GETFIELD(IODA3_MBT1_MASK, mbe1) << 12;
196 size |= 0xff00000000000000ull;
197 size = ~size + 1;
198
199
200 if (mbe0 & IODA3_MBT0_TYPE_M32) {
201 start = phb->regs[PHB_M32_START_ADDR >> 3];
202 if ((start + size) > 0x100000000ull) {
203 phb_error(phb, "M32 set beyond 4GB boundary !");
204 size = 0x100000000 - start;
205 }
206 } else {
207 start = base | (phb->regs[PHB_M64_UPPER_BITS >> 3]);
208 }
209
210
211
212
213 if (memory_region_is_mapped(&phb->mmbar0) &&
214 base >= phb->mmio0_base &&
215 (base + size) <= (phb->mmio0_base + phb->mmio0_size)) {
216 parent = &phb->mmbar0;
217 base -= phb->mmio0_base;
218 } else if (memory_region_is_mapped(&phb->mmbar1) &&
219 base >= phb->mmio1_base &&
220 (base + size) <= (phb->mmio1_base + phb->mmio1_size)) {
221 parent = &phb->mmbar1;
222 base -= phb->mmio1_base;
223 } else {
224 phb_error(phb, "PHB MBAR %d out of parent bounds", index);
225 return;
226 }
227
228
229 snprintf(name, sizeof(name), "phb4-mbar%d", index);
230 memory_region_init_alias(&phb->mr_mmio[index], OBJECT(phb), name,
231 &phb->pci_mmio, start, size);
232 memory_region_add_subregion(parent, base, &phb->mr_mmio[index]);
233}
234
235static void pnv_phb4_check_all_mbt(PnvPHB4 *phb)
236{
237 uint64_t i;
238 uint32_t num_windows = phb->big_phb ? PNV_PHB4_MAX_MMIO_WINDOWS :
239 PNV_PHB4_MIN_MMIO_WINDOWS;
240
241 for (i = 0; i < num_windows; i++) {
242 pnv_phb4_check_mbt(phb, i);
243 }
244}
245
246static uint64_t *pnv_phb4_ioda_access(PnvPHB4 *phb,
247 unsigned *out_table, unsigned *out_idx)
248{
249 uint64_t adreg = phb->regs[PHB_IODA_ADDR >> 3];
250 unsigned int index = GETFIELD(PHB_IODA_AD_TADR, adreg);
251 unsigned int table = GETFIELD(PHB_IODA_AD_TSEL, adreg);
252 unsigned int mask;
253 uint64_t *tptr = NULL;
254
255 switch (table) {
256 case IODA3_TBL_LIST:
257 tptr = phb->ioda_LIST;
258 mask = 7;
259 break;
260 case IODA3_TBL_MIST:
261 tptr = phb->ioda_MIST;
262 mask = phb->big_phb ? PNV_PHB4_MAX_MIST : (PNV_PHB4_MAX_MIST >> 1);
263 mask -= 1;
264 break;
265 case IODA3_TBL_RCAM:
266 mask = phb->big_phb ? 127 : 63;
267 break;
268 case IODA3_TBL_MRT:
269 mask = phb->big_phb ? 15 : 7;
270 break;
271 case IODA3_TBL_PESTA:
272 case IODA3_TBL_PESTB:
273 mask = phb->big_phb ? PNV_PHB4_MAX_PEs : (PNV_PHB4_MAX_PEs >> 1);
274 mask -= 1;
275 break;
276 case IODA3_TBL_TVT:
277 tptr = phb->ioda_TVT;
278 mask = phb->big_phb ? PNV_PHB4_MAX_TVEs : (PNV_PHB4_MAX_TVEs >> 1);
279 mask -= 1;
280 break;
281 case IODA3_TBL_TCR:
282 case IODA3_TBL_TDR:
283 mask = phb->big_phb ? 1023 : 511;
284 break;
285 case IODA3_TBL_MBT:
286 tptr = phb->ioda_MBT;
287 mask = phb->big_phb ? PNV_PHB4_MAX_MBEs : (PNV_PHB4_MAX_MBEs >> 1);
288 mask -= 1;
289 break;
290 case IODA3_TBL_MDT:
291 tptr = phb->ioda_MDT;
292 mask = phb->big_phb ? PNV_PHB4_MAX_PEs : (PNV_PHB4_MAX_PEs >> 1);
293 mask -= 1;
294 break;
295 case IODA3_TBL_PEEV:
296 tptr = phb->ioda_PEEV;
297 mask = phb->big_phb ? PNV_PHB4_MAX_PEEVs : (PNV_PHB4_MAX_PEEVs >> 1);
298 mask -= 1;
299 break;
300 default:
301 phb_error(phb, "invalid IODA table %d", table);
302 return NULL;
303 }
304 index &= mask;
305 if (out_idx) {
306 *out_idx = index;
307 }
308 if (out_table) {
309 *out_table = table;
310 }
311 if (tptr) {
312 tptr += index;
313 }
314 if (adreg & PHB_IODA_AD_AUTOINC) {
315 index = (index + 1) & mask;
316 adreg = SETFIELD(PHB_IODA_AD_TADR, adreg, index);
317 }
318
319 phb->regs[PHB_IODA_ADDR >> 3] = adreg;
320 return tptr;
321}
322
323static uint64_t pnv_phb4_ioda_read(PnvPHB4 *phb)
324{
325 unsigned table, idx;
326 uint64_t *tptr;
327
328 tptr = pnv_phb4_ioda_access(phb, &table, &idx);
329 if (!tptr) {
330
331 if (table == IODA3_TBL_PESTA) {
332 return ((uint64_t)(phb->ioda_PEST_AB[idx] & 1)) << 63;
333 } else if (table == IODA3_TBL_PESTB) {
334 return ((uint64_t)(phb->ioda_PEST_AB[idx] & 2)) << 62;
335 }
336
337 return 0;
338 }
339 return *tptr;
340}
341
342static void pnv_phb4_ioda_write(PnvPHB4 *phb, uint64_t val)
343{
344 unsigned table, idx;
345 uint64_t *tptr;
346
347 tptr = pnv_phb4_ioda_access(phb, &table, &idx);
348 if (!tptr) {
349
350 if (table == IODA3_TBL_PESTA) {
351 phb->ioda_PEST_AB[idx] &= ~1;
352 phb->ioda_PEST_AB[idx] |= (val >> 63) & 1;
353 } else if (table == IODA3_TBL_PESTB) {
354 phb->ioda_PEST_AB[idx] &= ~2;
355 phb->ioda_PEST_AB[idx] |= (val >> 62) & 2;
356 }
357 return;
358 }
359
360
361 switch (table) {
362 case IODA3_TBL_LIST:
363 break;
364 case IODA3_TBL_MIST: {
365
366 uint64_t adreg = phb->regs[PHB_IODA_ADDR >> 3];
367 uint32_t mmask = GETFIELD(PHB_IODA_AD_MIST_PWV, adreg);
368 uint64_t v = *tptr;
369 if (mmask == 0) {
370 mmask = 0xf;
371 }
372 if (mmask & 8) {
373 v &= 0x0000ffffffffffffull;
374 v |= 0xcfff000000000000ull & val;
375 }
376 if (mmask & 4) {
377 v &= 0xffff0000ffffffffull;
378 v |= 0x0000cfff00000000ull & val;
379 }
380 if (mmask & 2) {
381 v &= 0xffffffff0000ffffull;
382 v |= 0x00000000cfff0000ull & val;
383 }
384 if (mmask & 1) {
385 v &= 0xffffffffffff0000ull;
386 v |= 0x000000000000cfffull & val;
387 }
388 *tptr = v;
389 break;
390 }
391 case IODA3_TBL_MBT:
392 *tptr = val;
393
394
395 phb->ioda_MBT[idx ^ 1] &= 0x7fffffffffffffffull;
396 phb->ioda_MBT[idx ^ 1] |= 0x8000000000000000ull & val;
397
398
399 pnv_phb4_check_mbt(phb, idx >> 1);
400 break;
401 default:
402 *tptr = val;
403 }
404}
405
406static void pnv_phb4_rtc_invalidate(PnvPHB4 *phb, uint64_t val)
407{
408 PnvPhb4DMASpace *ds;
409
410
411 QLIST_FOREACH(ds, &phb->dma_spaces, list) {
412 ds->pe_num = PHB_INVALID_PE;
413 }
414}
415
416static void pnv_phb4_update_msi_regions(PnvPhb4DMASpace *ds)
417{
418 uint64_t cfg = ds->phb->regs[PHB_PHB4_CONFIG >> 3];
419
420 if (cfg & PHB_PHB4C_32BIT_MSI_EN) {
421 if (!memory_region_is_mapped(MEMORY_REGION(&ds->msi32_mr))) {
422 memory_region_add_subregion(MEMORY_REGION(&ds->dma_mr),
423 0xffff0000, &ds->msi32_mr);
424 }
425 } else {
426 if (memory_region_is_mapped(MEMORY_REGION(&ds->msi32_mr))) {
427 memory_region_del_subregion(MEMORY_REGION(&ds->dma_mr),
428 &ds->msi32_mr);
429 }
430 }
431
432 if (cfg & PHB_PHB4C_64BIT_MSI_EN) {
433 if (!memory_region_is_mapped(MEMORY_REGION(&ds->msi64_mr))) {
434 memory_region_add_subregion(MEMORY_REGION(&ds->dma_mr),
435 (1ull << 60), &ds->msi64_mr);
436 }
437 } else {
438 if (memory_region_is_mapped(MEMORY_REGION(&ds->msi64_mr))) {
439 memory_region_del_subregion(MEMORY_REGION(&ds->dma_mr),
440 &ds->msi64_mr);
441 }
442 }
443}
444
445static void pnv_phb4_update_all_msi_regions(PnvPHB4 *phb)
446{
447 PnvPhb4DMASpace *ds;
448
449 QLIST_FOREACH(ds, &phb->dma_spaces, list) {
450 pnv_phb4_update_msi_regions(ds);
451 }
452}
453
454static void pnv_phb4_update_xsrc(PnvPHB4 *phb)
455{
456 int shift, flags, i, lsi_base;
457 XiveSource *xsrc = &phb->xsrc;
458
459
460 if (phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_PGSZ_64K) {
461 shift = XIVE_ESB_64K;
462 } else {
463 shift = XIVE_ESB_4K;
464 }
465 if (phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_STORE_EOI) {
466 flags = XIVE_SRC_STORE_EOI;
467 } else {
468 flags = 0;
469 }
470
471
472
473
474
475
476 if (phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_PQ_DISABLE) {
477 flags |= XIVE_SRC_PQ_DISABLE;
478 }
479
480 phb->xsrc.esb_shift = shift;
481 phb->xsrc.esb_flags = flags;
482
483 lsi_base = GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3]);
484 lsi_base <<= 3;
485
486
487 if (!lsi_base) {
488 return;
489 }
490
491
492 bitmap_zero(xsrc->lsi_map, xsrc->nr_irqs);
493
494 for (i = 0; i < xsrc->nr_irqs; i++) {
495 bool msi = (i < lsi_base || i >= (lsi_base + 8));
496 if (!msi) {
497 xive_source_irq_set_lsi(xsrc, i);
498 }
499 }
500}
501
502static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val,
503 unsigned size)
504{
505 PnvPHB4 *phb = PNV_PHB4(opaque);
506 bool changed;
507
508
509 if ((off & 0xfffc) == PHB_CONFIG_DATA) {
510 pnv_phb4_config_write(phb, off & 0x3, size, val);
511 return;
512 }
513
514
515 if ((off & 0xf800) == PHB_RC_CONFIG_BASE) {
516 pnv_phb4_rc_config_write(phb, off & 0x7ff, size, val);
517 return;
518 }
519
520
521 if (size != 8 || off & 0x7) {
522 phb_error(phb, "Invalid register access, offset: 0x%"PRIx64" size: %d",
523 off, size);
524 return;
525 }
526
527
528 switch (off) {
529 case PHB_LSI_SOURCE_ID:
530 val &= PHB_LSI_SRC_ID;
531 break;
532 case PHB_M64_UPPER_BITS:
533 val &= 0xff00000000000000ull;
534 break;
535
536 case PHB_TCE_KILL:
537
538 val &= ~(PHB_TCE_KILL_ALL | PHB_TCE_KILL_PE | PHB_TCE_KILL_ONE);
539 break;
540 case PHB_Q_DMA_R:
541
542
543
544
545 if (val & PHB_Q_DMA_R_AUTORESET) {
546 val = 0;
547 } else {
548 val &= PHB_Q_DMA_R_QUIESCE_DMA;
549 }
550 break;
551
552 case PHB_LEM_FIR_AND_MASK:
553 phb->regs[PHB_LEM_FIR_ACCUM >> 3] &= val;
554 return;
555 case PHB_LEM_FIR_OR_MASK:
556 phb->regs[PHB_LEM_FIR_ACCUM >> 3] |= val;
557 return;
558 case PHB_LEM_ERROR_AND_MASK:
559 phb->regs[PHB_LEM_ERROR_MASK >> 3] &= val;
560 return;
561 case PHB_LEM_ERROR_OR_MASK:
562 phb->regs[PHB_LEM_ERROR_MASK >> 3] |= val;
563 return;
564 case PHB_LEM_WOF:
565 val = 0;
566 break;
567
568
569
570 case PHB_CPU_LOADSTORE_STATUS:
571 case PHB_ETU_ERR_SUMMARY:
572 case PHB_PHB4_GEN_CAP:
573 case PHB_PHB4_TCE_CAP:
574 case PHB_PHB4_IRQ_CAP:
575 case PHB_PHB4_EEH_CAP:
576 return;
577 }
578
579
580 changed = phb->regs[off >> 3] != val;
581
582
583 phb->regs[off >> 3] = val;
584
585
586 switch (off) {
587 case PHB_PHB4_CONFIG:
588 if (changed) {
589 pnv_phb4_update_all_msi_regions(phb);
590 }
591 break;
592 case PHB_M32_START_ADDR:
593 case PHB_M64_UPPER_BITS:
594 if (changed) {
595 pnv_phb4_check_all_mbt(phb);
596 }
597 break;
598
599
600 case PHB_IODA_DATA0:
601 pnv_phb4_ioda_write(phb, val);
602 break;
603
604
605 case PHB_RTC_INVALIDATE:
606 pnv_phb4_rtc_invalidate(phb, val);
607 break;
608
609
610 case PHB_CTRLR:
611 case PHB_LSI_SOURCE_ID:
612 pnv_phb4_update_xsrc(phb);
613 break;
614
615
616 case PHB_ASN_CMPM:
617 case PHB_CONFIG_ADDRESS:
618 case PHB_IODA_ADDR:
619 case PHB_TCE_KILL:
620 case PHB_TCE_SPEC_CTL:
621 case PHB_PEST_BAR:
622 case PHB_PELTV_BAR:
623 case PHB_RTT_BAR:
624 case PHB_LEM_FIR_ACCUM:
625 case PHB_LEM_ERROR_MASK:
626 case PHB_LEM_ACTION0:
627 case PHB_LEM_ACTION1:
628 case PHB_TCE_TAG_ENABLE:
629 case PHB_INT_NOTIFY_ADDR:
630 case PHB_INT_NOTIFY_INDEX:
631 case PHB_DMARD_SYNC:
632 break;
633
634
635 default:
636 qemu_log_mask(LOG_UNIMP, "phb4: reg_write 0x%"PRIx64"=%"PRIx64"\n",
637 off, val);
638 }
639}
640
641static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size)
642{
643 PnvPHB4 *phb = PNV_PHB4(opaque);
644 uint64_t val;
645
646 if ((off & 0xfffc) == PHB_CONFIG_DATA) {
647 return pnv_phb4_config_read(phb, off & 0x3, size);
648 }
649
650
651 if ((off & 0xf800) == PHB_RC_CONFIG_BASE) {
652 return pnv_phb4_rc_config_read(phb, off & 0x7ff, size);
653 }
654
655
656 if (size != 8 || off & 0x7) {
657 phb_error(phb, "Invalid register access, offset: 0x%"PRIx64" size: %d",
658 off, size);
659 return ~0ull;
660 }
661
662
663 val = phb->regs[off >> 3];
664
665 switch (off) {
666 case PHB_VERSION:
667 return PNV_PHB4_PEC_GET_CLASS(phb->pec)->version;
668
669
670 case PHB_PHB4_GEN_CAP:
671 return 0xe4b8000000000000ull;
672 case PHB_PHB4_TCE_CAP:
673 return phb->big_phb ? 0x4008440000000400ull : 0x2008440000000200ull;
674 case PHB_PHB4_IRQ_CAP:
675 return phb->big_phb ? 0x0800000000001000ull : 0x0800000000000800ull;
676 case PHB_PHB4_EEH_CAP:
677 return phb->big_phb ? 0x2000000000000000ull : 0x1000000000000000ull;
678
679
680 case PHB_IODA_DATA0:
681 return pnv_phb4_ioda_read(phb);
682
683
684 case PHB_PCIE_DLP_TRAIN_CTL:
685
686 return PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT;
687
688
689 case PHB_DMARD_SYNC:
690 return PHB_DMARD_SYNC_COMPLETE;
691
692
693 case PHB_LSI_SOURCE_ID:
694 case PHB_CPU_LOADSTORE_STATUS:
695 case PHB_ASN_CMPM:
696 case PHB_PHB4_CONFIG:
697 case PHB_M32_START_ADDR:
698 case PHB_CONFIG_ADDRESS:
699 case PHB_IODA_ADDR:
700 case PHB_RTC_INVALIDATE:
701 case PHB_TCE_KILL:
702 case PHB_TCE_SPEC_CTL:
703 case PHB_PEST_BAR:
704 case PHB_PELTV_BAR:
705 case PHB_RTT_BAR:
706 case PHB_M64_UPPER_BITS:
707 case PHB_CTRLR:
708 case PHB_LEM_FIR_ACCUM:
709 case PHB_LEM_ERROR_MASK:
710 case PHB_LEM_ACTION0:
711 case PHB_LEM_ACTION1:
712 case PHB_TCE_TAG_ENABLE:
713 case PHB_INT_NOTIFY_ADDR:
714 case PHB_INT_NOTIFY_INDEX:
715 case PHB_Q_DMA_R:
716 case PHB_ETU_ERR_SUMMARY:
717 break;
718
719
720 default:
721 qemu_log_mask(LOG_UNIMP, "phb4: reg_read 0x%"PRIx64"=%"PRIx64"\n",
722 off, val);
723 }
724 return val;
725}
726
727static const MemoryRegionOps pnv_phb4_reg_ops = {
728 .read = pnv_phb4_reg_read,
729 .write = pnv_phb4_reg_write,
730 .valid.min_access_size = 1,
731 .valid.max_access_size = 8,
732 .impl.min_access_size = 1,
733 .impl.max_access_size = 8,
734 .endianness = DEVICE_BIG_ENDIAN,
735};
736
737static uint64_t pnv_phb4_xscom_read(void *opaque, hwaddr addr, unsigned size)
738{
739 PnvPHB4 *phb = PNV_PHB4(opaque);
740 uint32_t reg = addr >> 3;
741 uint64_t val;
742 hwaddr offset;
743
744 switch (reg) {
745 case PHB_SCOM_HV_IND_ADDR:
746 return phb->scom_hv_ind_addr_reg;
747
748 case PHB_SCOM_HV_IND_DATA:
749 if (!(phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_VALID)) {
750 phb_error(phb, "Invalid indirect address");
751 return ~0ull;
752 }
753 size = (phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_4B) ? 4 : 8;
754 offset = GETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR, phb->scom_hv_ind_addr_reg);
755 val = pnv_phb4_reg_read(phb, offset, size);
756 if (phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_AUTOINC) {
757 offset += size;
758 offset &= 0x3fff;
759 phb->scom_hv_ind_addr_reg = SETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR,
760 phb->scom_hv_ind_addr_reg,
761 offset);
762 }
763 return val;
764 case PHB_SCOM_ETU_LEM_FIR:
765 case PHB_SCOM_ETU_LEM_FIR_AND:
766 case PHB_SCOM_ETU_LEM_FIR_OR:
767 case PHB_SCOM_ETU_LEM_FIR_MSK:
768 case PHB_SCOM_ETU_LEM_ERR_MSK_AND:
769 case PHB_SCOM_ETU_LEM_ERR_MSK_OR:
770 case PHB_SCOM_ETU_LEM_ACT0:
771 case PHB_SCOM_ETU_LEM_ACT1:
772 case PHB_SCOM_ETU_LEM_WOF:
773 offset = ((reg - PHB_SCOM_ETU_LEM_FIR) << 3) + PHB_LEM_FIR_ACCUM;
774 return pnv_phb4_reg_read(phb, offset, size);
775 case PHB_SCOM_ETU_PMON_CONFIG:
776 case PHB_SCOM_ETU_PMON_CTR0:
777 case PHB_SCOM_ETU_PMON_CTR1:
778 case PHB_SCOM_ETU_PMON_CTR2:
779 case PHB_SCOM_ETU_PMON_CTR3:
780 offset = ((reg - PHB_SCOM_ETU_PMON_CONFIG) << 3) + PHB_PERFMON_CONFIG;
781 return pnv_phb4_reg_read(phb, offset, size);
782
783 default:
784 qemu_log_mask(LOG_UNIMP, "phb4: xscom_read 0x%"HWADDR_PRIx"\n", addr);
785 return ~0ull;
786 }
787}
788
789static void pnv_phb4_xscom_write(void *opaque, hwaddr addr,
790 uint64_t val, unsigned size)
791{
792 PnvPHB4 *phb = PNV_PHB4(opaque);
793 uint32_t reg = addr >> 3;
794 hwaddr offset;
795
796 switch (reg) {
797 case PHB_SCOM_HV_IND_ADDR:
798 phb->scom_hv_ind_addr_reg = val & 0xe000000000001fff;
799 break;
800 case PHB_SCOM_HV_IND_DATA:
801 if (!(phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_VALID)) {
802 phb_error(phb, "Invalid indirect address");
803 break;
804 }
805 size = (phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_4B) ? 4 : 8;
806 offset = GETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR, phb->scom_hv_ind_addr_reg);
807 pnv_phb4_reg_write(phb, offset, val, size);
808 if (phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_AUTOINC) {
809 offset += size;
810 offset &= 0x3fff;
811 phb->scom_hv_ind_addr_reg = SETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR,
812 phb->scom_hv_ind_addr_reg,
813 offset);
814 }
815 break;
816 case PHB_SCOM_ETU_LEM_FIR:
817 case PHB_SCOM_ETU_LEM_FIR_AND:
818 case PHB_SCOM_ETU_LEM_FIR_OR:
819 case PHB_SCOM_ETU_LEM_FIR_MSK:
820 case PHB_SCOM_ETU_LEM_ERR_MSK_AND:
821 case PHB_SCOM_ETU_LEM_ERR_MSK_OR:
822 case PHB_SCOM_ETU_LEM_ACT0:
823 case PHB_SCOM_ETU_LEM_ACT1:
824 case PHB_SCOM_ETU_LEM_WOF:
825 offset = ((reg - PHB_SCOM_ETU_LEM_FIR) << 3) + PHB_LEM_FIR_ACCUM;
826 pnv_phb4_reg_write(phb, offset, val, size);
827 break;
828 case PHB_SCOM_ETU_PMON_CONFIG:
829 case PHB_SCOM_ETU_PMON_CTR0:
830 case PHB_SCOM_ETU_PMON_CTR1:
831 case PHB_SCOM_ETU_PMON_CTR2:
832 case PHB_SCOM_ETU_PMON_CTR3:
833 offset = ((reg - PHB_SCOM_ETU_PMON_CONFIG) << 3) + PHB_PERFMON_CONFIG;
834 pnv_phb4_reg_write(phb, offset, val, size);
835 break;
836 default:
837 qemu_log_mask(LOG_UNIMP, "phb4: xscom_write 0x%"HWADDR_PRIx
838 "=%"PRIx64"\n", addr, val);
839 }
840}
841
842const MemoryRegionOps pnv_phb4_xscom_ops = {
843 .read = pnv_phb4_xscom_read,
844 .write = pnv_phb4_xscom_write,
845 .valid.min_access_size = 8,
846 .valid.max_access_size = 8,
847 .impl.min_access_size = 8,
848 .impl.max_access_size = 8,
849 .endianness = DEVICE_BIG_ENDIAN,
850};
851
852static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque, hwaddr addr,
853 unsigned size)
854{
855 PnvPHB4 *phb = PNV_PHB4(opaque);
856 uint32_t reg = addr >> 3;
857
858
859 return phb->nest_regs[reg];
860}
861
862
863
864
865
866
867
868
869
870static int pnv_phb4_get_phb_stack_no(PnvPHB4 *phb)
871{
872 PnvPhb4PecState *pec = phb->pec;
873 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
874 int index = pec->index;
875 int stack_no = phb->phb_id;
876
877 while (index--) {
878 stack_no -= pecc->num_phbs[index];
879 }
880
881 return stack_no;
882}
883
884static void pnv_phb4_update_regions(PnvPHB4 *phb)
885{
886
887 if (memory_region_is_mapped(&phb->mr_regs)) {
888 memory_region_del_subregion(&phb->phbbar, &phb->mr_regs);
889 }
890 if (memory_region_is_mapped(&phb->xsrc.esb_mmio)) {
891 memory_region_del_subregion(&phb->intbar, &phb->xsrc.esb_mmio);
892 }
893
894
895 if (memory_region_is_mapped(&phb->phbbar)) {
896 memory_region_add_subregion(&phb->phbbar, 0, &phb->mr_regs);
897 }
898
899
900 if (memory_region_is_mapped(&phb->intbar)) {
901 memory_region_add_subregion(&phb->intbar, 0, &phb->xsrc.esb_mmio);
902 }
903
904
905 pnv_phb4_check_all_mbt(phb);
906}
907
908static void pnv_pec_phb_update_map(PnvPHB4 *phb)
909{
910 PnvPhb4PecState *pec = phb->pec;
911 MemoryRegion *sysmem = get_system_memory();
912 uint64_t bar_en = phb->nest_regs[PEC_NEST_STK_BAR_EN];
913 int stack_no = pnv_phb4_get_phb_stack_no(phb);
914 uint64_t bar, mask, size;
915 char name[64];
916
917
918
919
920
921
922
923
924
925
926 if (memory_region_is_mapped(&phb->mmbar0) &&
927 !(bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) {
928 memory_region_del_subregion(sysmem, &phb->mmbar0);
929 }
930 if (memory_region_is_mapped(&phb->mmbar1) &&
931 !(bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) {
932 memory_region_del_subregion(sysmem, &phb->mmbar1);
933 }
934 if (memory_region_is_mapped(&phb->phbbar) &&
935 !(bar_en & PEC_NEST_STK_BAR_EN_PHB)) {
936 memory_region_del_subregion(sysmem, &phb->phbbar);
937 }
938 if (memory_region_is_mapped(&phb->intbar) &&
939 !(bar_en & PEC_NEST_STK_BAR_EN_INT)) {
940 memory_region_del_subregion(sysmem, &phb->intbar);
941 }
942
943
944 pnv_phb4_update_regions(phb);
945
946
947 if (!memory_region_is_mapped(&phb->mmbar0) &&
948 (bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) {
949 bar = phb->nest_regs[PEC_NEST_STK_MMIO_BAR0] >> 8;
950 mask = phb->nest_regs[PEC_NEST_STK_MMIO_BAR0_MASK];
951 size = ((~mask) >> 8) + 1;
952 snprintf(name, sizeof(name), "pec-%d.%d-phb-%d-mmio0",
953 pec->chip_id, pec->index, stack_no);
954 memory_region_init(&phb->mmbar0, OBJECT(phb), name, size);
955 memory_region_add_subregion(sysmem, bar, &phb->mmbar0);
956 phb->mmio0_base = bar;
957 phb->mmio0_size = size;
958 }
959 if (!memory_region_is_mapped(&phb->mmbar1) &&
960 (bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) {
961 bar = phb->nest_regs[PEC_NEST_STK_MMIO_BAR1] >> 8;
962 mask = phb->nest_regs[PEC_NEST_STK_MMIO_BAR1_MASK];
963 size = ((~mask) >> 8) + 1;
964 snprintf(name, sizeof(name), "pec-%d.%d-phb-%d-mmio1",
965 pec->chip_id, pec->index, stack_no);
966 memory_region_init(&phb->mmbar1, OBJECT(phb), name, size);
967 memory_region_add_subregion(sysmem, bar, &phb->mmbar1);
968 phb->mmio1_base = bar;
969 phb->mmio1_size = size;
970 }
971 if (!memory_region_is_mapped(&phb->phbbar) &&
972 (bar_en & PEC_NEST_STK_BAR_EN_PHB)) {
973 bar = phb->nest_regs[PEC_NEST_STK_PHB_REGS_BAR] >> 8;
974 size = PNV_PHB4_NUM_REGS << 3;
975 snprintf(name, sizeof(name), "pec-%d.%d-phb-%d",
976 pec->chip_id, pec->index, stack_no);
977 memory_region_init(&phb->phbbar, OBJECT(phb), name, size);
978 memory_region_add_subregion(sysmem, bar, &phb->phbbar);
979 }
980 if (!memory_region_is_mapped(&phb->intbar) &&
981 (bar_en & PEC_NEST_STK_BAR_EN_INT)) {
982 bar = phb->nest_regs[PEC_NEST_STK_INT_BAR] >> 8;
983 size = PNV_PHB4_MAX_INTs << 16;
984 snprintf(name, sizeof(name), "pec-%d.%d-phb-%d-int",
985 phb->pec->chip_id, phb->pec->index, stack_no);
986 memory_region_init(&phb->intbar, OBJECT(phb), name, size);
987 memory_region_add_subregion(sysmem, bar, &phb->intbar);
988 }
989
990
991 pnv_phb4_update_regions(phb);
992}
993
994static void pnv_pec_stk_nest_xscom_write(void *opaque, hwaddr addr,
995 uint64_t val, unsigned size)
996{
997 PnvPHB4 *phb = PNV_PHB4(opaque);
998 PnvPhb4PecState *pec = phb->pec;
999 uint32_t reg = addr >> 3;
1000
1001 switch (reg) {
1002 case PEC_NEST_STK_PCI_NEST_FIR:
1003 phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] = val;
1004 break;
1005 case PEC_NEST_STK_PCI_NEST_FIR_CLR:
1006 phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] &= val;
1007 break;
1008 case PEC_NEST_STK_PCI_NEST_FIR_SET:
1009 phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] |= val;
1010 break;
1011 case PEC_NEST_STK_PCI_NEST_FIR_MSK:
1012 phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] = val;
1013 break;
1014 case PEC_NEST_STK_PCI_NEST_FIR_MSKC:
1015 phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] &= val;
1016 break;
1017 case PEC_NEST_STK_PCI_NEST_FIR_MSKS:
1018 phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] |= val;
1019 break;
1020 case PEC_NEST_STK_PCI_NEST_FIR_ACT0:
1021 case PEC_NEST_STK_PCI_NEST_FIR_ACT1:
1022 phb->nest_regs[reg] = val;
1023 break;
1024 case PEC_NEST_STK_PCI_NEST_FIR_WOF:
1025 phb->nest_regs[reg] = 0;
1026 break;
1027 case PEC_NEST_STK_ERR_REPORT_0:
1028 case PEC_NEST_STK_ERR_REPORT_1:
1029 case PEC_NEST_STK_PBCQ_GNRL_STATUS:
1030
1031 break;
1032 case PEC_NEST_STK_PBCQ_MODE:
1033 phb->nest_regs[reg] = val & 0xff00000000000000ull;
1034 break;
1035 case PEC_NEST_STK_MMIO_BAR0:
1036 case PEC_NEST_STK_MMIO_BAR0_MASK:
1037 case PEC_NEST_STK_MMIO_BAR1:
1038 case PEC_NEST_STK_MMIO_BAR1_MASK:
1039 if (phb->nest_regs[PEC_NEST_STK_BAR_EN] &
1040 (PEC_NEST_STK_BAR_EN_MMIO0 |
1041 PEC_NEST_STK_BAR_EN_MMIO1)) {
1042 phb_pec_error(pec, "Changing enabled BAR unsupported\n");
1043 }
1044 phb->nest_regs[reg] = val & 0xffffffffff000000ull;
1045 break;
1046 case PEC_NEST_STK_PHB_REGS_BAR:
1047 if (phb->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_PHB) {
1048 phb_pec_error(pec, "Changing enabled BAR unsupported\n");
1049 }
1050 phb->nest_regs[reg] = val & 0xffffffffffc00000ull;
1051 break;
1052 case PEC_NEST_STK_INT_BAR:
1053 if (phb->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_INT) {
1054 phb_pec_error(pec, "Changing enabled BAR unsupported\n");
1055 }
1056 phb->nest_regs[reg] = val & 0xfffffff000000000ull;
1057 break;
1058 case PEC_NEST_STK_BAR_EN:
1059 phb->nest_regs[reg] = val & 0xf000000000000000ull;
1060 pnv_pec_phb_update_map(phb);
1061 break;
1062 case PEC_NEST_STK_DATA_FRZ_TYPE:
1063 case PEC_NEST_STK_PBCQ_TUN_BAR:
1064
1065 phb->nest_regs[reg] = val;
1066 break;
1067 default:
1068 qemu_log_mask(LOG_UNIMP, "phb4_pec: nest_xscom_write 0x%"HWADDR_PRIx
1069 "=%"PRIx64"\n", addr, val);
1070 }
1071}
1072
1073static const MemoryRegionOps pnv_pec_stk_nest_xscom_ops = {
1074 .read = pnv_pec_stk_nest_xscom_read,
1075 .write = pnv_pec_stk_nest_xscom_write,
1076 .valid.min_access_size = 8,
1077 .valid.max_access_size = 8,
1078 .impl.min_access_size = 8,
1079 .impl.max_access_size = 8,
1080 .endianness = DEVICE_BIG_ENDIAN,
1081};
1082
1083static uint64_t pnv_pec_stk_pci_xscom_read(void *opaque, hwaddr addr,
1084 unsigned size)
1085{
1086 PnvPHB4 *phb = PNV_PHB4(opaque);
1087 uint32_t reg = addr >> 3;
1088
1089
1090 return phb->pci_regs[reg];
1091}
1092
1093static void pnv_pec_stk_pci_xscom_write(void *opaque, hwaddr addr,
1094 uint64_t val, unsigned size)
1095{
1096 PnvPHB4 *phb = PNV_PHB4(opaque);
1097 uint32_t reg = addr >> 3;
1098
1099 switch (reg) {
1100 case PEC_PCI_STK_PCI_FIR:
1101 phb->pci_regs[reg] = val;
1102 break;
1103 case PEC_PCI_STK_PCI_FIR_CLR:
1104 phb->pci_regs[PEC_PCI_STK_PCI_FIR] &= val;
1105 break;
1106 case PEC_PCI_STK_PCI_FIR_SET:
1107 phb->pci_regs[PEC_PCI_STK_PCI_FIR] |= val;
1108 break;
1109 case PEC_PCI_STK_PCI_FIR_MSK:
1110 phb->pci_regs[reg] = val;
1111 break;
1112 case PEC_PCI_STK_PCI_FIR_MSKC:
1113 phb->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] &= val;
1114 break;
1115 case PEC_PCI_STK_PCI_FIR_MSKS:
1116 phb->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] |= val;
1117 break;
1118 case PEC_PCI_STK_PCI_FIR_ACT0:
1119 case PEC_PCI_STK_PCI_FIR_ACT1:
1120 phb->pci_regs[reg] = val;
1121 break;
1122 case PEC_PCI_STK_PCI_FIR_WOF:
1123 phb->pci_regs[reg] = 0;
1124 break;
1125 case PEC_PCI_STK_ETU_RESET:
1126 phb->pci_regs[reg] = val & 0x8000000000000000ull;
1127
1128 break;
1129 case PEC_PCI_STK_PBAIB_ERR_REPORT:
1130 break;
1131 case PEC_PCI_STK_PBAIB_TX_CMD_CRED:
1132 case PEC_PCI_STK_PBAIB_TX_DAT_CRED:
1133 phb->pci_regs[reg] = val;
1134 break;
1135 default:
1136 qemu_log_mask(LOG_UNIMP, "phb4_pec_stk: pci_xscom_write 0x%"HWADDR_PRIx
1137 "=%"PRIx64"\n", addr, val);
1138 }
1139}
1140
1141static const MemoryRegionOps pnv_pec_stk_pci_xscom_ops = {
1142 .read = pnv_pec_stk_pci_xscom_read,
1143 .write = pnv_pec_stk_pci_xscom_write,
1144 .valid.min_access_size = 8,
1145 .valid.max_access_size = 8,
1146 .impl.min_access_size = 8,
1147 .impl.max_access_size = 8,
1148 .endianness = DEVICE_BIG_ENDIAN,
1149};
1150
1151static int pnv_phb4_map_irq(PCIDevice *pci_dev, int irq_num)
1152{
1153
1154 return irq_num & 3;
1155}
1156
1157static void pnv_phb4_set_irq(void *opaque, int irq_num, int level)
1158{
1159 PnvPHB4 *phb = PNV_PHB4(opaque);
1160 uint32_t lsi_base;
1161
1162
1163 if (irq_num > 3) {
1164 phb_error(phb, "IRQ %x is not an LSI", irq_num);
1165 }
1166 lsi_base = GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3]);
1167 lsi_base <<= 3;
1168 qemu_set_irq(phb->qirqs[lsi_base + irq_num], level);
1169}
1170
1171static bool pnv_phb4_resolve_pe(PnvPhb4DMASpace *ds)
1172{
1173 uint64_t rtt, addr;
1174 uint16_t rte;
1175 int bus_num;
1176 int num_PEs;
1177
1178
1179 if (ds->pe_num != PHB_INVALID_PE) {
1180 return true;
1181 }
1182
1183
1184 rtt = ds->phb->regs[PHB_RTT_BAR >> 3];
1185 if (!(rtt & PHB_RTT_BAR_ENABLE)) {
1186 phb_error(ds->phb, "DMA with RTT BAR disabled !");
1187
1188 return false;
1189 }
1190
1191
1192 bus_num = pci_bus_num(ds->bus);
1193 addr = rtt & PHB_RTT_BASE_ADDRESS_MASK;
1194 addr += 2 * PCI_BUILD_BDF(bus_num, ds->devfn);
1195 if (dma_memory_read(&address_space_memory, addr, &rte,
1196 sizeof(rte), MEMTXATTRS_UNSPECIFIED)) {
1197 phb_error(ds->phb, "Failed to read RTT entry at 0x%"PRIx64, addr);
1198
1199 return false;
1200 }
1201 rte = be16_to_cpu(rte);
1202
1203
1204 num_PEs = ds->phb->big_phb ? PNV_PHB4_MAX_PEs : (PNV_PHB4_MAX_PEs >> 1);
1205 if (rte >= num_PEs) {
1206 phb_error(ds->phb, "RTE for RID 0x%x invalid (%04x", ds->devfn, rte);
1207 rte &= num_PEs - 1;
1208 }
1209 ds->pe_num = rte;
1210 return true;
1211}
1212
1213static void pnv_phb4_translate_tve(PnvPhb4DMASpace *ds, hwaddr addr,
1214 bool is_write, uint64_t tve,
1215 IOMMUTLBEntry *tlb)
1216{
1217 uint64_t tta = GETFIELD(IODA3_TVT_TABLE_ADDR, tve);
1218 int32_t lev = GETFIELD(IODA3_TVT_NUM_LEVELS, tve);
1219 uint32_t tts = GETFIELD(IODA3_TVT_TCE_TABLE_SIZE, tve);
1220 uint32_t tps = GETFIELD(IODA3_TVT_IO_PSIZE, tve);
1221
1222
1223 if (lev > 4) {
1224 phb_error(ds->phb, "Invalid #levels in TVE %d", lev);
1225 return;
1226 }
1227
1228
1229 if (tts == 0) {
1230 phb_error(ds->phb, "Access to invalid TVE");
1231 return;
1232 }
1233
1234
1235 if (tps == 0) {
1236
1237
1238
1239 tlb->iova = addr & 0xfffffffffffff000ull;
1240 tlb->translated_addr = addr & 0x0003fffffffff000ull;
1241 tlb->addr_mask = 0xfffull;
1242 tlb->perm = IOMMU_RW;
1243 } else {
1244 uint32_t tce_shift, tbl_shift, sh;
1245 uint64_t base, taddr, tce, tce_mask;
1246
1247
1248 tce_shift = tps + 11;
1249
1250
1251 tbl_shift = tts + 8;
1252
1253
1254 base = tta << 12;
1255
1256
1257 sh = tbl_shift * lev + tce_shift;
1258
1259
1260
1261
1262 do {
1263 lev--;
1264
1265
1266 taddr = base | (((addr >> sh) & ((1ul << tbl_shift) - 1)) << 3);
1267 if (dma_memory_read(&address_space_memory, taddr, &tce,
1268 sizeof(tce), MEMTXATTRS_UNSPECIFIED)) {
1269 phb_error(ds->phb, "Failed to read TCE at 0x%"PRIx64, taddr);
1270 return;
1271 }
1272 tce = be64_to_cpu(tce);
1273
1274
1275 if ((lev >= 0) && !(tce & 3)) {
1276 phb_error(ds->phb, "Invalid indirect TCE at 0x%"PRIx64, taddr);
1277 phb_error(ds->phb, " xlate %"PRIx64":%c TVE=%"PRIx64, addr,
1278 is_write ? 'W' : 'R', tve);
1279 phb_error(ds->phb, " tta=%"PRIx64" lev=%d tts=%d tps=%d",
1280 tta, lev, tts, tps);
1281 return;
1282 }
1283 sh -= tbl_shift;
1284 base = tce & ~0xfffull;
1285 } while (lev >= 0);
1286
1287
1288 if ((is_write & !(tce & 2)) || ((!is_write) && !(tce & 1))) {
1289 phb_error(ds->phb, "TCE access fault at 0x%"PRIx64, taddr);
1290 phb_error(ds->phb, " xlate %"PRIx64":%c TVE=%"PRIx64, addr,
1291 is_write ? 'W' : 'R', tve);
1292 phb_error(ds->phb, " tta=%"PRIx64" lev=%d tts=%d tps=%d",
1293 tta, lev, tts, tps);
1294 return;
1295 }
1296 tce_mask = ~((1ull << tce_shift) - 1);
1297 tlb->iova = addr & tce_mask;
1298 tlb->translated_addr = tce & tce_mask;
1299 tlb->addr_mask = ~tce_mask;
1300 tlb->perm = tce & 3;
1301 }
1302}
1303
1304static IOMMUTLBEntry pnv_phb4_translate_iommu(IOMMUMemoryRegion *iommu,
1305 hwaddr addr,
1306 IOMMUAccessFlags flag,
1307 int iommu_idx)
1308{
1309 PnvPhb4DMASpace *ds = container_of(iommu, PnvPhb4DMASpace, dma_mr);
1310 int tve_sel;
1311 uint64_t tve, cfg;
1312 IOMMUTLBEntry ret = {
1313 .target_as = &address_space_memory,
1314 .iova = addr,
1315 .translated_addr = 0,
1316 .addr_mask = ~(hwaddr)0,
1317 .perm = IOMMU_NONE,
1318 };
1319
1320
1321 if (!pnv_phb4_resolve_pe(ds)) {
1322 phb_error(ds->phb, "Failed to resolve PE# for bus @%p (%d) devfn 0x%x",
1323 ds->bus, pci_bus_num(ds->bus), ds->devfn);
1324 return ret;
1325 }
1326
1327
1328 switch (addr >> 60) {
1329 case 00:
1330
1331 cfg = ds->phb->regs[PHB_PHB4_CONFIG >> 3];
1332 if ((cfg & PHB_PHB4C_32BIT_MSI_EN) &&
1333 ((addr & 0xffffffffffff0000ull) == 0xffff0000ull)) {
1334 phb_error(ds->phb, "xlate on 32-bit MSI region");
1335 return ret;
1336 }
1337
1338 tve_sel = (addr >> 59) & 1;
1339 tve = ds->phb->ioda_TVT[ds->pe_num * 2 + tve_sel];
1340 pnv_phb4_translate_tve(ds, addr, flag & IOMMU_WO, tve, &ret);
1341 break;
1342 case 01:
1343 phb_error(ds->phb, "xlate on 64-bit MSI region");
1344 break;
1345 default:
1346 phb_error(ds->phb, "xlate on unsupported address 0x%"PRIx64, addr);
1347 }
1348 return ret;
1349}
1350
1351#define TYPE_PNV_PHB4_IOMMU_MEMORY_REGION "pnv-phb4-iommu-memory-region"
1352DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, PNV_PHB4_IOMMU_MEMORY_REGION,
1353 TYPE_PNV_PHB4_IOMMU_MEMORY_REGION)
1354
1355static void pnv_phb4_iommu_memory_region_class_init(ObjectClass *klass,
1356 void *data)
1357{
1358 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
1359
1360 imrc->translate = pnv_phb4_translate_iommu;
1361}
1362
1363static const TypeInfo pnv_phb4_iommu_memory_region_info = {
1364 .parent = TYPE_IOMMU_MEMORY_REGION,
1365 .name = TYPE_PNV_PHB4_IOMMU_MEMORY_REGION,
1366 .class_init = pnv_phb4_iommu_memory_region_class_init,
1367};
1368
1369
1370
1371
1372
1373int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index)
1374{
1375 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1376 int index = pec->index;
1377 int offset = 0;
1378
1379 while (index--) {
1380 offset += pecc->num_phbs[index];
1381 }
1382
1383 return offset + stack_index;
1384}
1385
1386
1387
1388
1389
1390static void pnv_phb4_msi_write(void *opaque, hwaddr addr,
1391 uint64_t data, unsigned size)
1392{
1393 PnvPhb4DMASpace *ds = opaque;
1394 PnvPHB4 *phb = ds->phb;
1395
1396 uint32_t src = ((addr >> 4) & 0xffff) | (data & 0x1f);
1397
1398
1399 if (!pnv_phb4_resolve_pe(ds)) {
1400 phb_error(phb, "Failed to resolve PE# for bus @%p (%d) devfn 0x%x",
1401 ds->bus, pci_bus_num(ds->bus), ds->devfn);
1402 return;
1403 }
1404
1405
1406 if (src >= phb->xsrc.nr_irqs) {
1407 phb_error(phb, "MSI %d out of bounds", src);
1408 return;
1409 }
1410
1411
1412
1413 qemu_irq_pulse(phb->qirqs[src]);
1414}
1415
1416
1417static uint64_t pnv_phb4_msi_read(void *opaque, hwaddr addr, unsigned size)
1418{
1419 PnvPhb4DMASpace *ds = opaque;
1420
1421 phb_error(ds->phb, "Invalid MSI read @ 0x%" HWADDR_PRIx, addr);
1422 return -1;
1423}
1424
1425static const MemoryRegionOps pnv_phb4_msi_ops = {
1426 .read = pnv_phb4_msi_read,
1427 .write = pnv_phb4_msi_write,
1428 .endianness = DEVICE_LITTLE_ENDIAN
1429};
1430
1431static PnvPhb4DMASpace *pnv_phb4_dma_find(PnvPHB4 *phb, PCIBus *bus, int devfn)
1432{
1433 PnvPhb4DMASpace *ds;
1434
1435 QLIST_FOREACH(ds, &phb->dma_spaces, list) {
1436 if (ds->bus == bus && ds->devfn == devfn) {
1437 break;
1438 }
1439 }
1440 return ds;
1441}
1442
1443static AddressSpace *pnv_phb4_dma_iommu(PCIBus *bus, void *opaque, int devfn)
1444{
1445 PnvPHB4 *phb = opaque;
1446 PnvPhb4DMASpace *ds;
1447 char name[32];
1448
1449 ds = pnv_phb4_dma_find(phb, bus, devfn);
1450
1451 if (ds == NULL) {
1452 ds = g_new0(PnvPhb4DMASpace, 1);
1453 ds->bus = bus;
1454 ds->devfn = devfn;
1455 ds->pe_num = PHB_INVALID_PE;
1456 ds->phb = phb;
1457 snprintf(name, sizeof(name), "phb4-%d.%d-iommu", phb->chip_id,
1458 phb->phb_id);
1459 memory_region_init_iommu(&ds->dma_mr, sizeof(ds->dma_mr),
1460 TYPE_PNV_PHB4_IOMMU_MEMORY_REGION,
1461 OBJECT(phb), name, UINT64_MAX);
1462 address_space_init(&ds->dma_as, MEMORY_REGION(&ds->dma_mr),
1463 name);
1464 memory_region_init_io(&ds->msi32_mr, OBJECT(phb), &pnv_phb4_msi_ops,
1465 ds, "msi32", 0x10000);
1466 memory_region_init_io(&ds->msi64_mr, OBJECT(phb), &pnv_phb4_msi_ops,
1467 ds, "msi64", 0x100000);
1468 pnv_phb4_update_msi_regions(ds);
1469
1470 QLIST_INSERT_HEAD(&phb->dma_spaces, ds, list);
1471 }
1472 return &ds->dma_as;
1473}
1474
1475static void pnv_phb4_xscom_realize(PnvPHB4 *phb)
1476{
1477 PnvPhb4PecState *pec = phb->pec;
1478 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1479 int stack_no = pnv_phb4_get_phb_stack_no(phb);
1480 uint32_t pec_nest_base;
1481 uint32_t pec_pci_base;
1482 char name[64];
1483
1484 assert(pec);
1485
1486
1487 snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest-phb-%d",
1488 pec->chip_id, pec->index, stack_no);
1489 pnv_xscom_region_init(&phb->nest_regs_mr, OBJECT(phb),
1490 &pnv_pec_stk_nest_xscom_ops, phb, name,
1491 PHB4_PEC_NEST_STK_REGS_COUNT);
1492
1493 snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-phb-%d",
1494 pec->chip_id, pec->index, stack_no);
1495 pnv_xscom_region_init(&phb->pci_regs_mr, OBJECT(phb),
1496 &pnv_pec_stk_pci_xscom_ops, phb, name,
1497 PHB4_PEC_PCI_STK_REGS_COUNT);
1498
1499
1500 snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-phb-%d",
1501 pec->chip_id, pec->index, stack_no);
1502 pnv_xscom_region_init(&phb->phb_regs_mr, OBJECT(phb),
1503 &pnv_phb4_xscom_ops, phb, name, 0x40);
1504
1505 pec_nest_base = pecc->xscom_nest_base(pec);
1506 pec_pci_base = pecc->xscom_pci_base(pec);
1507
1508
1509 pnv_xscom_add_subregion(pec->chip,
1510 pec_nest_base + 0x40 * (stack_no + 1),
1511 &phb->nest_regs_mr);
1512 pnv_xscom_add_subregion(pec->chip,
1513 pec_pci_base + 0x40 * (stack_no + 1),
1514 &phb->pci_regs_mr);
1515 pnv_xscom_add_subregion(pec->chip,
1516 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 +
1517 0x40 * stack_no,
1518 &phb->phb_regs_mr);
1519}
1520
1521static void pnv_phb4_instance_init(Object *obj)
1522{
1523 PnvPHB4 *phb = PNV_PHB4(obj);
1524
1525 QLIST_INIT(&phb->dma_spaces);
1526
1527
1528 object_initialize_child(obj, "source", &phb->xsrc, TYPE_XIVE_SOURCE);
1529}
1530
1531static void pnv_phb4_realize(DeviceState *dev, Error **errp)
1532{
1533 PnvPHB4 *phb = PNV_PHB4(dev);
1534 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(phb->pec);
1535 PCIHostState *pci = PCI_HOST_BRIDGE(dev);
1536 XiveSource *xsrc = &phb->xsrc;
1537 int nr_irqs;
1538 char name[32];
1539
1540
1541 phb->big_phb = phb->phb_id == 0 || phb->phb_id == 3;
1542
1543
1544 snprintf(name, sizeof(name), "phb4-%d.%d-regs", phb->chip_id,
1545 phb->phb_id);
1546 memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb4_reg_ops, phb,
1547 name, 0x2000);
1548
1549
1550
1551
1552
1553
1554
1555 snprintf(name, sizeof(name), "phb4-%d.%d-pci-io", phb->chip_id,
1556 phb->phb_id);
1557 memory_region_init(&phb->pci_io, OBJECT(phb), name, 0x10000);
1558
1559 snprintf(name, sizeof(name), "phb4-%d.%d-pci-mmio", phb->chip_id,
1560 phb->phb_id);
1561 memory_region_init(&phb->pci_mmio, OBJECT(phb), name,
1562 PCI_MMIO_TOTAL_SIZE);
1563
1564 pci->bus = pci_register_root_bus(dev, dev->id,
1565 pnv_phb4_set_irq, pnv_phb4_map_irq, phb,
1566 &phb->pci_mmio, &phb->pci_io,
1567 0, 4, TYPE_PNV_PHB4_ROOT_BUS);
1568 pci_setup_iommu(pci->bus, pnv_phb4_dma_iommu, phb);
1569 pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
1570
1571
1572 pnv_phb_attach_root_port(pci, pecc->rp_model,
1573 phb->phb_id, phb->chip_id);
1574
1575
1576 if (phb->big_phb) {
1577 nr_irqs = PNV_PHB4_MAX_INTs;
1578 } else {
1579 nr_irqs = PNV_PHB4_MAX_INTs >> 1;
1580 }
1581 object_property_set_int(OBJECT(xsrc), "nr-irqs", nr_irqs, &error_fatal);
1582 object_property_set_link(OBJECT(xsrc), "xive", OBJECT(phb), &error_fatal);
1583 if (!qdev_realize(DEVICE(xsrc), NULL, errp)) {
1584 return;
1585 }
1586
1587 pnv_phb4_update_xsrc(phb);
1588
1589 phb->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);
1590
1591 pnv_phb4_xscom_realize(phb);
1592}
1593
1594static const char *pnv_phb4_root_bus_path(PCIHostState *host_bridge,
1595 PCIBus *rootbus)
1596{
1597 PnvPHB4 *phb = PNV_PHB4(host_bridge);
1598
1599 snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x",
1600 phb->chip_id, phb->phb_id);
1601 return phb->bus_path;
1602}
1603
1604
1605
1606
1607
1608
1609static void pnv_phb4_xive_notify_abt(PnvPHB4 *phb, uint32_t srcno,
1610 bool pq_checked)
1611{
1612 uint64_t notif_port = phb->regs[PHB_INT_NOTIFY_ADDR >> 3];
1613 uint64_t data = 0;
1614 hwaddr addr;
1615 MemTxResult result;
1616 int esb_shift;
1617
1618 if (notif_port & PHB_INT_NOTIFY_ADDR_64K) {
1619 esb_shift = 16;
1620 } else {
1621 esb_shift = 12;
1622 }
1623
1624
1625 addr = (notif_port & ~PHB_INT_NOTIFY_ADDR_64K);
1626 addr |= (1ull << (esb_shift + 1)) * srcno;
1627 addr |= (1ull << esb_shift);
1628
1629
1630
1631
1632
1633
1634
1635 if (pq_checked) {
1636 addr |= XIVE_ESB_INJECT;
1637 }
1638
1639 trace_pnv_phb4_xive_notify_ic(addr, data);
1640
1641 address_space_stq_be(&address_space_memory, addr, data,
1642 MEMTXATTRS_UNSPECIFIED, &result);
1643 if (result != MEMTX_OK) {
1644 phb_error(phb, "trigger failed @%"HWADDR_PRIx "\n", addr);
1645 return;
1646 }
1647}
1648
1649static void pnv_phb4_xive_notify_ic(PnvPHB4 *phb, uint32_t srcno,
1650 bool pq_checked)
1651{
1652 uint64_t notif_port = phb->regs[PHB_INT_NOTIFY_ADDR >> 3];
1653 uint32_t offset = phb->regs[PHB_INT_NOTIFY_INDEX >> 3];
1654 uint64_t data = offset | srcno;
1655 MemTxResult result;
1656
1657 if (pq_checked) {
1658 data |= XIVE_TRIGGER_PQ;
1659 }
1660
1661 trace_pnv_phb4_xive_notify_ic(notif_port, data);
1662
1663 address_space_stq_be(&address_space_memory, notif_port, data,
1664 MEMTXATTRS_UNSPECIFIED, &result);
1665 if (result != MEMTX_OK) {
1666 phb_error(phb, "trigger failed @%"HWADDR_PRIx "\n", notif_port);
1667 return;
1668 }
1669}
1670
1671static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno,
1672 bool pq_checked)
1673{
1674 PnvPHB4 *phb = PNV_PHB4(xf);
1675
1676 if (phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_ABT_MODE) {
1677 pnv_phb4_xive_notify_abt(phb, srcno, pq_checked);
1678 } else {
1679 pnv_phb4_xive_notify_ic(phb, srcno, pq_checked);
1680 }
1681}
1682
1683static Property pnv_phb4_properties[] = {
1684 DEFINE_PROP_UINT32("index", PnvPHB4, phb_id, 0),
1685 DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0),
1686 DEFINE_PROP_LINK("pec", PnvPHB4, pec, TYPE_PNV_PHB4_PEC,
1687 PnvPhb4PecState *),
1688 DEFINE_PROP_END_OF_LIST(),
1689};
1690
1691static void pnv_phb4_class_init(ObjectClass *klass, void *data)
1692{
1693 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
1694 DeviceClass *dc = DEVICE_CLASS(klass);
1695 XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass);
1696
1697 hc->root_bus_path = pnv_phb4_root_bus_path;
1698 dc->realize = pnv_phb4_realize;
1699 device_class_set_props(dc, pnv_phb4_properties);
1700 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
1701 dc->user_creatable = false;
1702
1703 xfc->notify = pnv_phb4_xive_notify;
1704}
1705
1706static const TypeInfo pnv_phb4_type_info = {
1707 .name = TYPE_PNV_PHB4,
1708 .parent = TYPE_PCIE_HOST_BRIDGE,
1709 .instance_init = pnv_phb4_instance_init,
1710 .instance_size = sizeof(PnvPHB4),
1711 .class_init = pnv_phb4_class_init,
1712 .interfaces = (InterfaceInfo[]) {
1713 { TYPE_XIVE_NOTIFIER },
1714 { },
1715 }
1716};
1717
1718static const TypeInfo pnv_phb5_type_info = {
1719 .name = TYPE_PNV_PHB5,
1720 .parent = TYPE_PNV_PHB4,
1721 .instance_size = sizeof(PnvPHB4),
1722};
1723
1724static void pnv_phb4_root_bus_class_init(ObjectClass *klass, void *data)
1725{
1726 BusClass *k = BUS_CLASS(klass);
1727
1728
1729
1730
1731
1732 k->max_dev = 1;
1733}
1734
1735static const TypeInfo pnv_phb4_root_bus_info = {
1736 .name = TYPE_PNV_PHB4_ROOT_BUS,
1737 .parent = TYPE_PCIE_BUS,
1738 .class_init = pnv_phb4_root_bus_class_init,
1739};
1740
1741static void pnv_phb4_root_port_reset(DeviceState *dev)
1742{
1743 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
1744 PCIDevice *d = PCI_DEVICE(dev);
1745 uint8_t *conf = d->config;
1746
1747 rpc->parent_reset(dev);
1748
1749 pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
1750 PCI_IO_RANGE_MASK & 0xff);
1751 pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
1752 PCI_IO_RANGE_MASK & 0xff);
1753 pci_set_word(conf + PCI_MEMORY_BASE, 0);
1754 pci_set_word(conf + PCI_MEMORY_LIMIT, 0xfff0);
1755 pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0x1);
1756 pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1);
1757 pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1);
1758 pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff);
1759 pci_config_set_interrupt_pin(conf, 0);
1760}
1761
1762static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp)
1763{
1764 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
1765 Error *local_err = NULL;
1766
1767 rpc->parent_realize(dev, &local_err);
1768 if (local_err) {
1769 error_propagate(errp, local_err);
1770 return;
1771 }
1772}
1773
1774static void pnv_phb4_root_port_class_init(ObjectClass *klass, void *data)
1775{
1776 DeviceClass *dc = DEVICE_CLASS(klass);
1777 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1778 PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
1779
1780 dc->desc = "IBM PHB4 PCIE Root Port";
1781 dc->user_creatable = false;
1782
1783 device_class_set_parent_realize(dc, pnv_phb4_root_port_realize,
1784 &rpc->parent_realize);
1785 device_class_set_parent_reset(dc, pnv_phb4_root_port_reset,
1786 &rpc->parent_reset);
1787
1788 k->vendor_id = PCI_VENDOR_ID_IBM;
1789 k->device_id = PNV_PHB4_DEVICE_ID;
1790 k->revision = 0;
1791
1792 rpc->exp_offset = 0x48;
1793 rpc->aer_offset = 0x100;
1794
1795 dc->reset = &pnv_phb4_root_port_reset;
1796}
1797
1798static const TypeInfo pnv_phb4_root_port_info = {
1799 .name = TYPE_PNV_PHB4_ROOT_PORT,
1800 .parent = TYPE_PCIE_ROOT_PORT,
1801 .instance_size = sizeof(PnvPHB4RootPort),
1802 .class_init = pnv_phb4_root_port_class_init,
1803};
1804
1805static void pnv_phb5_root_port_class_init(ObjectClass *klass, void *data)
1806{
1807 DeviceClass *dc = DEVICE_CLASS(klass);
1808 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1809
1810 dc->desc = "IBM PHB5 PCIE Root Port";
1811 dc->user_creatable = false;
1812
1813 k->vendor_id = PCI_VENDOR_ID_IBM;
1814 k->device_id = PNV_PHB5_DEVICE_ID;
1815}
1816
1817static const TypeInfo pnv_phb5_root_port_info = {
1818 .name = TYPE_PNV_PHB5_ROOT_PORT,
1819 .parent = TYPE_PNV_PHB4_ROOT_PORT,
1820 .instance_size = sizeof(PnvPHB4RootPort),
1821 .class_init = pnv_phb5_root_port_class_init,
1822};
1823
1824static void pnv_phb4_register_types(void)
1825{
1826 type_register_static(&pnv_phb4_root_bus_info);
1827 type_register_static(&pnv_phb5_root_port_info);
1828 type_register_static(&pnv_phb4_root_port_info);
1829 type_register_static(&pnv_phb4_type_info);
1830 type_register_static(&pnv_phb5_type_info);
1831 type_register_static(&pnv_phb4_iommu_memory_region_info);
1832}
1833
1834type_init(pnv_phb4_register_types);
1835
1836void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon)
1837{
1838 uint64_t notif_port =
1839 phb->regs[PHB_INT_NOTIFY_ADDR >> 3] & ~PHB_INT_NOTIFY_ADDR_64K;
1840 uint32_t offset = phb->regs[PHB_INT_NOTIFY_INDEX >> 3];
1841 bool abt = !!(phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_ABT_MODE);
1842
1843 monitor_printf(mon, "PHB4[%x:%x] Source %08x .. %08x %s @%"HWADDR_PRIx"\n",
1844 phb->chip_id, phb->phb_id,
1845 offset, offset + phb->xsrc.nr_irqs - 1,
1846 abt ? "ABT" : "",
1847 notif_port);
1848 xive_source_pic_print_info(&phb->xsrc, 0, mon);
1849}
1850
