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14#include "qemu/osdep.h"
15#include "qemu/units.h"
16#include "qemu/error-report.h"
17#include "qemu/datadir.h"
18#include "qemu/error-report.h"
19#include "net/net.h"
20#include "hw/pci/pci.h"
21#include "hw/boards.h"
22#include "sysemu/kvm.h"
23#include "kvm_ppc.h"
24#include "sysemu/device_tree.h"
25#include "hw/loader.h"
26#include "elf.h"
27#include "hw/char/serial.h"
28#include "hw/ppc/ppc.h"
29#include "ppc405.h"
30#include "sysemu/sysemu.h"
31#include "sysemu/reset.h"
32#include "hw/sysbus.h"
33#include "hw/intc/ppc-uic.h"
34#include "hw/qdev-properties.h"
35#include "qapi/error.h"
36
37#define BINARY_DEVICE_TREE_FILE "bamboo.dtb"
38
39
40#define KERNEL_ADDR 0x1000000
41#define FDT_ADDR 0x1800000
42#define RAMDISK_ADDR 0x1900000
43
44#define PPC440EP_PCI_CONFIG 0xeec00000
45#define PPC440EP_PCI_INTACK 0xeed00000
46#define PPC440EP_PCI_SPECIAL 0xeed00000
47#define PPC440EP_PCI_REGS 0xef400000
48#define PPC440EP_PCI_IO 0xe8000000
49#define PPC440EP_PCI_IOLEN 0x00010000
50
51#define PPC440EP_SDRAM_NR_BANKS 4
52
53static const ram_addr_t ppc440ep_sdram_bank_sizes[] = {
54 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0
55};
56
57static hwaddr entry;
58
59static int bamboo_load_device_tree(hwaddr addr,
60 uint32_t ramsize,
61 hwaddr initrd_base,
62 hwaddr initrd_size,
63 const char *kernel_cmdline)
64{
65 int ret = -1;
66 uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) };
67 char *filename;
68 int fdt_size;
69 void *fdt;
70 uint32_t tb_freq = 400000000;
71 uint32_t clock_freq = 400000000;
72
73 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
74 if (!filename) {
75 return -1;
76 }
77 fdt = load_device_tree(filename, &fdt_size);
78 g_free(filename);
79 if (fdt == NULL) {
80 return -1;
81 }
82
83
84
85 ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
86 sizeof(mem_reg_property));
87 if (ret < 0)
88 fprintf(stderr, "couldn't set /memory/reg\n");
89
90 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
91 initrd_base);
92 if (ret < 0)
93 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
94
95 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
96 (initrd_base + initrd_size));
97 if (ret < 0)
98 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
99
100 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
101 kernel_cmdline);
102 if (ret < 0)
103 fprintf(stderr, "couldn't set /chosen/bootargs\n");
104
105
106
107
108 if (kvm_enabled()) {
109 tb_freq = kvmppc_get_tbfreq();
110 clock_freq = kvmppc_get_clockfreq();
111 }
112
113 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency",
114 clock_freq);
115 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency",
116 tb_freq);
117
118 rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
119 g_free(fdt);
120 return 0;
121}
122
123
124static void mmubooke_create_initial_mapping(CPUPPCState *env,
125 target_ulong va,
126 hwaddr pa)
127{
128 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
129
130 tlb->attr = 0;
131 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
132 tlb->size = 1U << 31;
133 tlb->EPN = va & TARGET_PAGE_MASK;
134 tlb->RPN = pa & TARGET_PAGE_MASK;
135 tlb->PID = 0;
136
137 tlb = &env->tlb.tlbe[1];
138 tlb->attr = 0;
139 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
140 tlb->size = 1U << 31;
141 tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
142 tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
143 tlb->PID = 0;
144}
145
146static void main_cpu_reset(void *opaque)
147{
148 PowerPCCPU *cpu = opaque;
149 CPUPPCState *env = &cpu->env;
150
151 cpu_reset(CPU(cpu));
152 env->gpr[1] = (16 * MiB) - 8;
153 env->gpr[3] = FDT_ADDR;
154 env->nip = entry;
155
156
157 mmubooke_create_initial_mapping(env, 0, 0);
158}
159
160static void bamboo_init(MachineState *machine)
161{
162 const char *kernel_filename = machine->kernel_filename;
163 const char *kernel_cmdline = machine->kernel_cmdline;
164 const char *initrd_filename = machine->initrd_filename;
165 unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 };
166 MemoryRegion *address_space_mem = get_system_memory();
167 MemoryRegion *isa = g_new(MemoryRegion, 1);
168 MemoryRegion *ram_memories = g_new(MemoryRegion, PPC440EP_SDRAM_NR_BANKS);
169 hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS];
170 hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS];
171 PCIBus *pcibus;
172 PowerPCCPU *cpu;
173 CPUPPCState *env;
174 target_long initrd_size = 0;
175 DeviceState *dev;
176 DeviceState *uicdev;
177 SysBusDevice *uicsbd;
178 int success;
179 int i;
180
181 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
182 env = &cpu->env;
183
184 if (env->mmu_model != POWERPC_MMU_BOOKE) {
185 error_report("MMU model %i not supported by this machine",
186 env->mmu_model);
187 exit(1);
188 }
189
190 qemu_register_reset(main_cpu_reset, cpu);
191 ppc_booke_timers_init(cpu, 400000000, 0);
192 ppc_dcr_init(env, NULL, NULL);
193
194
195 uicdev = qdev_new(TYPE_PPC_UIC);
196 uicsbd = SYS_BUS_DEVICE(uicdev);
197
198 object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
199 &error_fatal);
200 sysbus_realize_and_unref(uicsbd, &error_fatal);
201
202 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
203 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
204 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
205 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
206
207
208 memset(ram_bases, 0, sizeof(ram_bases));
209 memset(ram_sizes, 0, sizeof(ram_sizes));
210 ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories,
211 ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes);
212
213 ppc4xx_sdram_init(env,
214 qdev_get_gpio_in(uicdev, 14),
215 PPC440EP_SDRAM_NR_BANKS, ram_memories,
216 ram_bases, ram_sizes, 1);
217
218
219 dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
220 PPC440EP_PCI_CONFIG,
221 qdev_get_gpio_in(uicdev, pci_irq_nrs[0]),
222 qdev_get_gpio_in(uicdev, pci_irq_nrs[1]),
223 qdev_get_gpio_in(uicdev, pci_irq_nrs[2]),
224 qdev_get_gpio_in(uicdev, pci_irq_nrs[3]),
225 NULL);
226 pcibus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
227 if (!pcibus) {
228 error_report("couldn't create PCI controller");
229 exit(1);
230 }
231
232 memory_region_init_alias(isa, NULL, "isa_mmio",
233 get_system_io(), 0, PPC440EP_PCI_IOLEN);
234 memory_region_add_subregion(get_system_memory(), PPC440EP_PCI_IO, isa);
235
236 if (serial_hd(0) != NULL) {
237 serial_mm_init(address_space_mem, 0xef600300, 0,
238 qdev_get_gpio_in(uicdev, 0),
239 PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
240 DEVICE_BIG_ENDIAN);
241 }
242 if (serial_hd(1) != NULL) {
243 serial_mm_init(address_space_mem, 0xef600400, 0,
244 qdev_get_gpio_in(uicdev, 1),
245 PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
246 DEVICE_BIG_ENDIAN);
247 }
248
249 if (pcibus) {
250
251 for (i = 0; i < nb_nics; i++) {
252
253
254 pci_nic_init_nofail(&nd_table[i], pcibus, "e1000", NULL);
255 }
256 }
257
258
259 if (kernel_filename) {
260 hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID;
261 success = load_uimage(kernel_filename, &entry, &loadaddr, NULL,
262 NULL, NULL);
263 if (success < 0) {
264 uint64_t elf_entry;
265 success = load_elf(kernel_filename, NULL, NULL, NULL, &elf_entry,
266 NULL, NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
267 entry = elf_entry;
268 }
269
270 if (success < 0) {
271 error_report("could not load kernel '%s'", kernel_filename);
272 exit(1);
273 }
274 }
275
276
277 if (initrd_filename) {
278 initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR,
279 machine->ram_size - RAMDISK_ADDR);
280
281 if (initrd_size < 0) {
282 error_report("could not load ram disk '%s' at %x",
283 initrd_filename, RAMDISK_ADDR);
284 exit(1);
285 }
286 }
287
288
289 if (kernel_filename) {
290 if (bamboo_load_device_tree(FDT_ADDR, machine->ram_size, RAMDISK_ADDR,
291 initrd_size, kernel_cmdline) < 0) {
292 error_report("couldn't load device tree");
293 exit(1);
294 }
295 }
296}
297
298static void bamboo_machine_init(MachineClass *mc)
299{
300 mc->desc = "bamboo";
301 mc->init = bamboo_init;
302 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440epb");
303 mc->default_ram_id = "ppc4xx.sdram";
304}
305
306DEFINE_MACHINE("bamboo", bamboo_machine_init)
307
