1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25#include "qemu/osdep.h"
26#include "qemu/units.h"
27#include "qemu/error-report.h"
28#include "qapi/error.h"
29#include "qemu/datadir.h"
30#include "cpu.h"
31#include "hw/pci/pci.h"
32#include "hw/pci/pci_bridge.h"
33#include "hw/pci/pci_bus.h"
34#include "hw/pci/pci_host.h"
35#include "hw/qdev-properties.h"
36#include "hw/pci-host/sabre.h"
37#include "hw/char/serial.h"
38#include "hw/char/parallel.h"
39#include "hw/rtc/m48t59.h"
40#include "migration/vmstate.h"
41#include "hw/input/i8042.h"
42#include "hw/block/fdc.h"
43#include "net/net.h"
44#include "qemu/timer.h"
45#include "sysemu/runstate.h"
46#include "sysemu/sysemu.h"
47#include "hw/boards.h"
48#include "hw/nvram/sun_nvram.h"
49#include "hw/nvram/chrp_nvram.h"
50#include "hw/sparc/sparc64.h"
51#include "hw/nvram/fw_cfg.h"
52#include "hw/sysbus.h"
53#include "hw/ide/pci.h"
54#include "hw/loader.h"
55#include "hw/fw-path-provider.h"
56#include "elf.h"
57#include "trace.h"
58#include "qom/object.h"
59
60#define KERNEL_LOAD_ADDR 0x00404000
61#define CMDLINE_ADDR 0x003ff000
62#define PROM_SIZE_MAX (4 * MiB)
63#define PROM_VADDR 0x000ffd00000ULL
64#define PBM_SPECIAL_BASE 0x1fe00000000ULL
65#define PBM_MEM_BASE 0x1ff00000000ULL
66#define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL)
67#define PROM_FILENAME "openbios-sparc64"
68#define NVRAM_SIZE 0x2000
69#define MAX_IDE_BUS 2
70#define BIOS_CFG_IOPORT 0x510
71#define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
72#define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
73#define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
74
75#define IVEC_MAX 0x40
76
77struct hwdef {
78 uint16_t machine_id;
79 uint64_t prom_addr;
80 uint64_t console_serial_base;
81};
82
83struct EbusState {
84
85 PCIDevice parent_obj;
86
87 ISABus *isa_bus;
88 qemu_irq isa_bus_irqs[ISA_NUM_IRQS];
89 uint64_t console_serial_base;
90 MemoryRegion bar0;
91 MemoryRegion bar1;
92};
93
94#define TYPE_EBUS "ebus"
95OBJECT_DECLARE_SIMPLE_TYPE(EbusState, EBUS)
96
97const char *fw_cfg_arch_key_name(uint16_t key)
98{
99 static const struct {
100 uint16_t key;
101 const char *name;
102 } fw_cfg_arch_wellknown_keys[] = {
103 {FW_CFG_SPARC64_WIDTH, "width"},
104 {FW_CFG_SPARC64_HEIGHT, "height"},
105 {FW_CFG_SPARC64_DEPTH, "depth"},
106 };
107
108 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
109 if (fw_cfg_arch_wellknown_keys[i].key == key) {
110 return fw_cfg_arch_wellknown_keys[i].name;
111 }
112 }
113 return NULL;
114}
115
116static void fw_cfg_boot_set(void *opaque, const char *boot_device,
117 Error **errp)
118{
119 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
120}
121
122static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
123 const char *arch, ram_addr_t RAM_size,
124 const char *boot_devices,
125 uint32_t kernel_image, uint32_t kernel_size,
126 const char *cmdline,
127 uint32_t initrd_image, uint32_t initrd_size,
128 uint32_t NVRAM_image,
129 int width, int height, int depth,
130 const uint8_t *macaddr)
131{
132 unsigned int i;
133 int sysp_end;
134 uint8_t image[0x1ff0];
135 NvramClass *k = NVRAM_GET_CLASS(nvram);
136
137 memset(image, '\0', sizeof(image));
138
139
140 sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0);
141
142
143 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
144
145 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
146
147 for (i = 0; i < sizeof(image); i++) {
148 (k->write)(nvram, i, image[i]);
149 }
150
151 return 0;
152}
153
154static uint64_t sun4u_load_kernel(const char *kernel_filename,
155 const char *initrd_filename,
156 ram_addr_t RAM_size, uint64_t *initrd_size,
157 uint64_t *initrd_addr, uint64_t *kernel_addr,
158 uint64_t *kernel_entry)
159{
160 int linux_boot;
161 unsigned int i;
162 long kernel_size;
163 uint8_t *ptr;
164 uint64_t kernel_top = 0;
165
166 linux_boot = (kernel_filename != NULL);
167
168 kernel_size = 0;
169 if (linux_boot) {
170 int bswap_needed;
171
172#ifdef BSWAP_NEEDED
173 bswap_needed = 1;
174#else
175 bswap_needed = 0;
176#endif
177 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, kernel_entry,
178 kernel_addr, &kernel_top, NULL, 1, EM_SPARCV9, 0,
179 0);
180 if (kernel_size < 0) {
181 *kernel_addr = KERNEL_LOAD_ADDR;
182 *kernel_entry = KERNEL_LOAD_ADDR;
183 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
184 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
185 TARGET_PAGE_SIZE);
186 }
187 if (kernel_size < 0) {
188 kernel_size = load_image_targphys(kernel_filename,
189 KERNEL_LOAD_ADDR,
190 RAM_size - KERNEL_LOAD_ADDR);
191 }
192 if (kernel_size < 0) {
193 error_report("could not load kernel '%s'", kernel_filename);
194 exit(1);
195 }
196
197 *initrd_size = 0;
198 if (initrd_filename && kernel_top) {
199 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
200
201 *initrd_size = load_image_targphys(initrd_filename,
202 *initrd_addr,
203 RAM_size - *initrd_addr);
204 if ((int)*initrd_size < 0) {
205 error_report("could not load initial ram disk '%s'",
206 initrd_filename);
207 exit(1);
208 }
209 }
210 if (*initrd_size > 0) {
211 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
212 ptr = rom_ptr(*kernel_addr + i, 32);
213 if (ptr && ldl_p(ptr + 8) == 0x48647253) {
214 stl_p(ptr + 24, *initrd_addr + *kernel_addr);
215 stl_p(ptr + 28, *initrd_size);
216 break;
217 }
218 }
219 }
220 }
221 return kernel_size;
222}
223
224typedef struct ResetData {
225 SPARCCPU *cpu;
226 uint64_t prom_addr;
227} ResetData;
228
229#define TYPE_SUN4U_POWER "power"
230OBJECT_DECLARE_SIMPLE_TYPE(PowerDevice, SUN4U_POWER)
231
232struct PowerDevice {
233 SysBusDevice parent_obj;
234
235 MemoryRegion power_mmio;
236};
237
238
239static uint64_t power_mem_read(void *opaque, hwaddr addr, unsigned size)
240{
241 return 0;
242}
243
244static void power_mem_write(void *opaque, hwaddr addr,
245 uint64_t val, unsigned size)
246{
247
248 if (val & 0x1000000) {
249 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
250 }
251}
252
253static const MemoryRegionOps power_mem_ops = {
254 .read = power_mem_read,
255 .write = power_mem_write,
256 .endianness = DEVICE_NATIVE_ENDIAN,
257 .valid = {
258 .min_access_size = 4,
259 .max_access_size = 4,
260 },
261};
262
263static void power_realize(DeviceState *dev, Error **errp)
264{
265 PowerDevice *d = SUN4U_POWER(dev);
266 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
267
268 memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d,
269 "power", sizeof(uint32_t));
270
271 sysbus_init_mmio(sbd, &d->power_mmio);
272}
273
274static void power_class_init(ObjectClass *klass, void *data)
275{
276 DeviceClass *dc = DEVICE_CLASS(klass);
277
278 dc->realize = power_realize;
279}
280
281static const TypeInfo power_info = {
282 .name = TYPE_SUN4U_POWER,
283 .parent = TYPE_SYS_BUS_DEVICE,
284 .instance_size = sizeof(PowerDevice),
285 .class_init = power_class_init,
286};
287
288static void ebus_isa_irq_handler(void *opaque, int n, int level)
289{
290 EbusState *s = EBUS(opaque);
291 qemu_irq irq = s->isa_bus_irqs[n];
292
293
294 trace_ebus_isa_irq_handler(n, level);
295 if (irq) {
296 qemu_set_irq(irq, level);
297 }
298}
299
300
301static void ebus_realize(PCIDevice *pci_dev, Error **errp)
302{
303 EbusState *s = EBUS(pci_dev);
304 ISADevice *isa_dev;
305 SysBusDevice *sbd;
306 DeviceState *dev;
307 qemu_irq *isa_irq;
308 DriveInfo *fd[MAX_FD];
309 int i;
310
311 s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(),
312 pci_address_space_io(pci_dev), errp);
313 if (!s->isa_bus) {
314 error_setg(errp, "unable to instantiate EBUS ISA bus");
315 return;
316 }
317
318
319 isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
320 isa_bus_irqs(s->isa_bus, isa_irq);
321 qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq",
322 ISA_NUM_IRQS);
323
324
325 i = 0;
326 if (s->console_serial_base) {
327 serial_mm_init(pci_address_space(pci_dev), s->console_serial_base,
328 0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN);
329 i++;
330 }
331 serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS);
332
333
334 parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
335
336
337 isa_create_simple(s->isa_bus, TYPE_I8042);
338
339
340 for (i = 0; i < MAX_FD; i++) {
341 fd[i] = drive_get(IF_FLOPPY, 0, i);
342 }
343 isa_dev = isa_new(TYPE_ISA_FDC);
344 dev = DEVICE(isa_dev);
345 qdev_prop_set_uint32(dev, "dma", -1);
346 isa_realize_and_unref(isa_dev, s->isa_bus, &error_fatal);
347 isa_fdc_init_drives(isa_dev, fd);
348
349
350 dev = qdev_new(TYPE_SUN4U_POWER);
351 sbd = SYS_BUS_DEVICE(dev);
352 sysbus_realize_and_unref(sbd, &error_fatal);
353 memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240,
354 sysbus_mmio_get_region(sbd, 0));
355
356
357 pci_dev->config[0x04] = 0x06;
358 pci_dev->config[0x05] = 0x00;
359 pci_dev->config[0x06] = 0xa0;
360 pci_dev->config[0x07] = 0x03;
361 pci_dev->config[0x09] = 0x00;
362 pci_dev->config[0x0D] = 0x0a;
363
364 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
365 0, 0x1000000);
366 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
367 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
368 0, 0x8000);
369 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
370}
371
372static Property ebus_properties[] = {
373 DEFINE_PROP_UINT64("console-serial-base", EbusState,
374 console_serial_base, 0),
375 DEFINE_PROP_END_OF_LIST(),
376};
377
378static void ebus_class_init(ObjectClass *klass, void *data)
379{
380 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
381 DeviceClass *dc = DEVICE_CLASS(klass);
382
383 k->realize = ebus_realize;
384 k->vendor_id = PCI_VENDOR_ID_SUN;
385 k->device_id = PCI_DEVICE_ID_SUN_EBUS;
386 k->revision = 0x01;
387 k->class_id = PCI_CLASS_BRIDGE_OTHER;
388 device_class_set_props(dc, ebus_properties);
389}
390
391static const TypeInfo ebus_info = {
392 .name = TYPE_EBUS,
393 .parent = TYPE_PCI_DEVICE,
394 .class_init = ebus_class_init,
395 .instance_size = sizeof(EbusState),
396 .interfaces = (InterfaceInfo[]) {
397 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
398 { },
399 },
400};
401
402#define TYPE_OPENPROM "openprom"
403typedef struct PROMState PROMState;
404DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM,
405 TYPE_OPENPROM)
406
407struct PROMState {
408 SysBusDevice parent_obj;
409
410 MemoryRegion prom;
411};
412
413static uint64_t translate_prom_address(void *opaque, uint64_t addr)
414{
415 hwaddr *base_addr = (hwaddr *)opaque;
416 return addr + *base_addr - PROM_VADDR;
417}
418
419
420static void prom_init(hwaddr addr, const char *bios_name)
421{
422 DeviceState *dev;
423 SysBusDevice *s;
424 char *filename;
425 int ret;
426
427 dev = qdev_new(TYPE_OPENPROM);
428 s = SYS_BUS_DEVICE(dev);
429 sysbus_realize_and_unref(s, &error_fatal);
430
431 sysbus_mmio_map(s, 0, addr);
432
433
434 if (bios_name == NULL) {
435 bios_name = PROM_FILENAME;
436 }
437 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
438 if (filename) {
439 ret = load_elf(filename, NULL, translate_prom_address, &addr,
440 NULL, NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0);
441 if (ret < 0 || ret > PROM_SIZE_MAX) {
442 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
443 }
444 g_free(filename);
445 } else {
446 ret = -1;
447 }
448 if (ret < 0 || ret > PROM_SIZE_MAX) {
449 error_report("could not load prom '%s'", bios_name);
450 exit(1);
451 }
452}
453
454static void prom_realize(DeviceState *ds, Error **errp)
455{
456 PROMState *s = OPENPROM(ds);
457 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
458 Error *local_err = NULL;
459
460 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom",
461 PROM_SIZE_MAX, &local_err);
462 if (local_err) {
463 error_propagate(errp, local_err);
464 return;
465 }
466
467 vmstate_register_ram_global(&s->prom);
468 memory_region_set_readonly(&s->prom, true);
469 sysbus_init_mmio(dev, &s->prom);
470}
471
472static Property prom_properties[] = {
473 {},
474};
475
476static void prom_class_init(ObjectClass *klass, void *data)
477{
478 DeviceClass *dc = DEVICE_CLASS(klass);
479
480 device_class_set_props(dc, prom_properties);
481 dc->realize = prom_realize;
482}
483
484static const TypeInfo prom_info = {
485 .name = TYPE_OPENPROM,
486 .parent = TYPE_SYS_BUS_DEVICE,
487 .instance_size = sizeof(PROMState),
488 .class_init = prom_class_init,
489};
490
491
492#define TYPE_SUN4U_MEMORY "memory"
493typedef struct RamDevice RamDevice;
494DECLARE_INSTANCE_CHECKER(RamDevice, SUN4U_RAM,
495 TYPE_SUN4U_MEMORY)
496
497struct RamDevice {
498 SysBusDevice parent_obj;
499
500 MemoryRegion ram;
501 uint64_t size;
502};
503
504
505static void ram_realize(DeviceState *dev, Error **errp)
506{
507 RamDevice *d = SUN4U_RAM(dev);
508 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
509
510 memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size,
511 &error_fatal);
512 vmstate_register_ram_global(&d->ram);
513 sysbus_init_mmio(sbd, &d->ram);
514}
515
516static void ram_init(hwaddr addr, ram_addr_t RAM_size)
517{
518 DeviceState *dev;
519 SysBusDevice *s;
520 RamDevice *d;
521
522
523 dev = qdev_new(TYPE_SUN4U_MEMORY);
524 s = SYS_BUS_DEVICE(dev);
525
526 d = SUN4U_RAM(dev);
527 d->size = RAM_size;
528 sysbus_realize_and_unref(s, &error_fatal);
529
530 sysbus_mmio_map(s, 0, addr);
531}
532
533static Property ram_properties[] = {
534 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
535 DEFINE_PROP_END_OF_LIST(),
536};
537
538static void ram_class_init(ObjectClass *klass, void *data)
539{
540 DeviceClass *dc = DEVICE_CLASS(klass);
541
542 dc->realize = ram_realize;
543 device_class_set_props(dc, ram_properties);
544}
545
546static const TypeInfo ram_info = {
547 .name = TYPE_SUN4U_MEMORY,
548 .parent = TYPE_SYS_BUS_DEVICE,
549 .instance_size = sizeof(RamDevice),
550 .class_init = ram_class_init,
551};
552
553static void sun4uv_init(MemoryRegion *address_space_mem,
554 MachineState *machine,
555 const struct hwdef *hwdef)
556{
557 SPARCCPU *cpu;
558 Nvram *nvram;
559 unsigned int i;
560 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
561 SabreState *sabre;
562 PCIBus *pci_bus, *pci_busA, *pci_busB;
563 PCIDevice *ebus, *pci_dev;
564 SysBusDevice *s;
565 DeviceState *iommu, *dev;
566 FWCfgState *fw_cfg;
567 NICInfo *nd;
568 MACAddr macaddr;
569 bool onboard_nic;
570
571
572 cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr);
573
574
575 iommu = qdev_new(TYPE_SUN4U_IOMMU);
576 sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu), &error_fatal);
577
578
579 ram_init(0, machine->ram_size);
580
581 prom_init(hwdef->prom_addr, machine->firmware);
582
583
584 sabre = SABRE(qdev_new(TYPE_SABRE));
585 qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
586 qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
587 object_property_set_link(OBJECT(sabre), "iommu", OBJECT(iommu),
588 &error_abort);
589 sysbus_realize_and_unref(SYS_BUS_DEVICE(sabre), &error_fatal);
590
591
592 sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 0, PBM_SPECIAL_BASE);
593
594 sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 1, PBM_SPECIAL_BASE + 0x1000000ULL);
595
596 sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 2, PBM_SPECIAL_BASE + 0x2000000ULL);
597
598
599 for (i = 0; i < IVEC_MAX; i++) {
600 qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
601 qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
602 }
603
604 pci_bus = PCI_HOST_BRIDGE(sabre)->bus;
605 pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA);
606 pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB);
607
608
609
610
611 pci_bus->slot_reserved_mask = 0xfffffffc;
612 pci_busA->slot_reserved_mask = 0xfffffff1;
613 pci_busB->slot_reserved_mask = 0xfffffff0;
614
615 ebus = pci_new_multifunction(PCI_DEVFN(1, 0), true, TYPE_EBUS);
616 qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
617 hwdef->console_serial_base);
618 pci_realize_and_unref(ebus, pci_busA, &error_fatal);
619
620
621 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
622 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ));
623 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
624 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ));
625 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
626 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ));
627 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
628 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ));
629 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
630 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ));
631
632 switch (vga_interface_type) {
633 case VGA_STD:
634 pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
635 vga_interface_created = true;
636 break;
637 case VGA_NONE:
638 break;
639 default:
640 abort();
641 }
642
643 memset(&macaddr, 0, sizeof(MACAddr));
644 onboard_nic = false;
645 for (i = 0; i < nb_nics; i++) {
646 PCIBus *bus;
647 nd = &nd_table[i];
648
649 if (!nd->model || strcmp(nd->model, "sunhme") == 0) {
650 if (!onboard_nic) {
651 pci_dev = pci_new_multifunction(PCI_DEVFN(1, 1),
652 true, "sunhme");
653 bus = pci_busA;
654 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
655 onboard_nic = true;
656 } else {
657 pci_dev = pci_new(-1, "sunhme");
658 bus = pci_busB;
659 }
660 } else {
661 pci_dev = pci_new(-1, nd->model);
662 bus = pci_busB;
663 }
664
665 dev = &pci_dev->qdev;
666 qdev_set_nic_properties(dev, nd);
667 pci_realize_and_unref(pci_dev, bus, &error_fatal);
668 }
669
670
671
672 if (!onboard_nic) {
673 qemu_macaddr_default_if_unset(&macaddr);
674 }
675
676 pci_dev = pci_new(PCI_DEVFN(3, 0), "cmd646-ide");
677 qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
678 pci_realize_and_unref(pci_dev, pci_busA, &error_fatal);
679 pci_ide_create_devs(pci_dev);
680
681
682 dev = qdev_new("sysbus-m48t59");
683 qdev_prop_set_int32(dev, "base-year", 1968);
684 s = SYS_BUS_DEVICE(dev);
685 sysbus_realize_and_unref(s, &error_fatal);
686 memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
687 sysbus_mmio_get_region(s, 0));
688 nvram = NVRAM(dev);
689
690 initrd_size = 0;
691 initrd_addr = 0;
692 kernel_size = sun4u_load_kernel(machine->kernel_filename,
693 machine->initrd_filename,
694 machine->ram_size, &initrd_size, &initrd_addr,
695 &kernel_addr, &kernel_entry);
696
697 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
698 machine->boot_config.order,
699 kernel_addr, kernel_size,
700 machine->kernel_cmdline,
701 initrd_addr, initrd_size,
702
703 0,
704 graphic_width, graphic_height, graphic_depth,
705 (uint8_t *)&macaddr);
706
707 dev = qdev_new(TYPE_FW_CFG_IO);
708 qdev_prop_set_bit(dev, "dma_enabled", false);
709 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev));
710 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
711 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT,
712 &FW_CFG_IO(dev)->comb_iomem);
713
714 fw_cfg = FW_CFG(dev);
715 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus);
716 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
717 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
718 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
719 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
720 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
721 if (machine->kernel_cmdline) {
722 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
723 strlen(machine->kernel_cmdline) + 1);
724 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
725 } else {
726 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
727 }
728 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
729 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
730 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_config.order[0]);
731
732 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
733 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
734 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
735
736 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
737}
738
739enum {
740 sun4u_id = 0,
741 sun4v_id = 64,
742};
743
744
745
746
747
748static char *sun4u_fw_dev_path(FWPathProvider *p, BusState *bus,
749 DeviceState *dev)
750{
751 PCIDevice *pci;
752
753 if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) {
754 pci = PCI_DEVICE(dev);
755
756 if (PCI_FUNC(pci->devfn)) {
757 return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci->devfn),
758 PCI_FUNC(pci->devfn));
759 } else {
760 return g_strdup_printf("pci@%x", PCI_SLOT(pci->devfn));
761 }
762 }
763
764 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
765 return g_strdup("disk");
766 }
767
768 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
769 return g_strdup("cdrom");
770 }
771
772 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
773 return g_strdup("disk");
774 }
775
776 return NULL;
777}
778
779static const struct hwdef hwdefs[] = {
780
781 {
782 .machine_id = sun4u_id,
783 .prom_addr = 0x1fff0000000ULL,
784 .console_serial_base = 0,
785 },
786
787 {
788 .machine_id = sun4v_id,
789 .prom_addr = 0x1fff0000000ULL,
790 .console_serial_base = 0,
791 },
792};
793
794
795static void sun4u_init(MachineState *machine)
796{
797 sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
798}
799
800
801static void sun4v_init(MachineState *machine)
802{
803 sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
804}
805
806static void sun4u_class_init(ObjectClass *oc, void *data)
807{
808 MachineClass *mc = MACHINE_CLASS(oc);
809 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
810
811 mc->desc = "Sun4u platform";
812 mc->init = sun4u_init;
813 mc->block_default_type = IF_IDE;
814 mc->max_cpus = 1;
815 mc->is_default = true;
816 mc->default_boot_order = "c";
817 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi");
818 mc->ignore_boot_device_suffixes = true;
819 mc->default_display = "std";
820 fwc->get_dev_path = sun4u_fw_dev_path;
821}
822
823static const TypeInfo sun4u_type = {
824 .name = MACHINE_TYPE_NAME("sun4u"),
825 .parent = TYPE_MACHINE,
826 .class_init = sun4u_class_init,
827 .interfaces = (InterfaceInfo[]) {
828 { TYPE_FW_PATH_PROVIDER },
829 { }
830 },
831};
832
833static void sun4v_class_init(ObjectClass *oc, void *data)
834{
835 MachineClass *mc = MACHINE_CLASS(oc);
836
837 mc->desc = "Sun4v platform";
838 mc->init = sun4v_init;
839 mc->block_default_type = IF_IDE;
840 mc->max_cpus = 1;
841 mc->default_boot_order = "c";
842 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
843 mc->default_display = "std";
844}
845
846static const TypeInfo sun4v_type = {
847 .name = MACHINE_TYPE_NAME("sun4v"),
848 .parent = TYPE_MACHINE,
849 .class_init = sun4v_class_init,
850};
851
852static void sun4u_register_types(void)
853{
854 type_register_static(&power_info);
855 type_register_static(&ebus_info);
856 type_register_static(&prom_info);
857 type_register_static(&ram_info);
858
859 type_register_static(&sun4u_type);
860 type_register_static(&sun4v_type);
861}
862
863type_init(sun4u_register_types)
864
