LXR qemu/hw/timer/digic-timer.c

   1/*
   2 * QEMU model of the Canon DIGIC timer block.
   3 *
   4 * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
   5 *
   6 * This model is based on reverse engineering efforts
   7 * made by CHDK (http://chdk.wikia.com) and
   8 * Magic Lantern (http://www.magiclantern.fm) projects
   9 * contributors.
  10 *
  11 * See "Timer/Clock Module" docs here:
  12 *   http://magiclantern.wikia.com/wiki/Register_Map
  13 *
  14 * The QEMU model of the OSTimer in PKUnity SoC by Guan Xuetao
  15 * is used as a template.
  16 *
  17 * This program is free software; you can redistribute it and/or modify
  18 * it under the terms of the GNU General Public License as published by
  19 * the Free Software Foundation; either version 2 of the License, or
  20 * (at your option) any later version.
  21 *
  22 * This program is distributed in the hope that it will be useful,
  23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25 * GNU General Public License for more details.
  26 *
  27 */
  28
  29#include "qemu/osdep.h"
  30#include "hw/sysbus.h"
  31#include "hw/ptimer.h"
  32#include "qemu/module.h"
  33#include "qemu/log.h"
  34
  35#include "hw/timer/digic-timer.h"
  36#include "migration/vmstate.h"
  37
  38static const VMStateDescription vmstate_digic_timer = {
  39    .name = "digic.timer",
  40    .version_id = 1,
  41    .minimum_version_id = 1,
  42    .fields = (VMStateField[]) {
  43        VMSTATE_PTIMER(ptimer, DigicTimerState),
  44        VMSTATE_UINT32(control, DigicTimerState),
  45        VMSTATE_UINT32(relvalue, DigicTimerState),
  46        VMSTATE_END_OF_LIST()
  47    }
  48};
  49
  50static void digic_timer_reset(DeviceState *dev)
  51{
  52    DigicTimerState *s = DIGIC_TIMER(dev);
  53
  54    ptimer_transaction_begin(s->ptimer);
  55    ptimer_stop(s->ptimer);
  56    ptimer_transaction_commit(s->ptimer);
  57    s->control = 0;
  58    s->relvalue = 0;
  59}
  60
  61static uint64_t digic_timer_read(void *opaque, hwaddr offset, unsigned size)
  62{
  63    DigicTimerState *s = opaque;
  64    uint64_t ret = 0;
  65
  66    switch (offset) {
  67    case DIGIC_TIMER_CONTROL:
  68        ret = s->control;
  69        break;
  70    case DIGIC_TIMER_RELVALUE:
  71        ret = s->relvalue;
  72        break;
  73    case DIGIC_TIMER_VALUE:
  74        ret = ptimer_get_count(s->ptimer) & 0xffff;
  75        break;
  76    default:
  77        qemu_log_mask(LOG_UNIMP,
  78                      "digic-timer: read access to unknown register 0x"
  79                      TARGET_FMT_plx "\n", offset);
  80    }
  81
  82    return ret;
  83}
  84
  85static void digic_timer_write(void *opaque, hwaddr offset,
  86                              uint64_t value, unsigned size)
  87{
  88    DigicTimerState *s = opaque;
  89
  90    switch (offset) {
  91    case DIGIC_TIMER_CONTROL:
  92        if (value & DIGIC_TIMER_CONTROL_RST) {
  93            digic_timer_reset((DeviceState *)s);
  94            break;
  95        }
  96
  97        ptimer_transaction_begin(s->ptimer);
  98        if (value & DIGIC_TIMER_CONTROL_EN) {
  99            ptimer_run(s->ptimer, 0);
 100        }
 101
 102        s->control = (uint32_t)value;
 103        ptimer_transaction_commit(s->ptimer);
 104        break;
 105
 106    case DIGIC_TIMER_RELVALUE:
 107        s->relvalue = extract32(value, 0, 16);
 108        ptimer_transaction_begin(s->ptimer);
 109        ptimer_set_limit(s->ptimer, s->relvalue, 1);
 110        ptimer_transaction_commit(s->ptimer);
 111        break;
 112
 113    case DIGIC_TIMER_VALUE:
 114        break;
 115
 116    default:
 117        qemu_log_mask(LOG_UNIMP,
 118                      "digic-timer: read access to unknown register 0x"
 119                      TARGET_FMT_plx "\n", offset);
 120    }
 121}
 122
 123static const MemoryRegionOps digic_timer_ops = {
 124    .read = digic_timer_read,
 125    .write = digic_timer_write,
 126    .impl = {
 127        .min_access_size = 4,
 128        .max_access_size = 4,
 129    },
 130    .endianness = DEVICE_NATIVE_ENDIAN,
 131};
 132
 133static void digic_timer_tick(void *opaque)
 134{
 135    /* Nothing to do on timer rollover */
 136}
 137
 138static void digic_timer_init(Object *obj)
 139{
 140    DigicTimerState *s = DIGIC_TIMER(obj);
 141
 142    s->ptimer = ptimer_init(digic_timer_tick, NULL, PTIMER_POLICY_LEGACY);
 143
 144    /*
 145     * FIXME: there is no documentation on Digic timer
 146     * frequency setup so let it always run at 1 MHz
 147     */
 148    ptimer_transaction_begin(s->ptimer);
 149    ptimer_set_freq(s->ptimer, 1 * 1000 * 1000);
 150    ptimer_transaction_commit(s->ptimer);
 151
 152    memory_region_init_io(&s->iomem, OBJECT(s), &digic_timer_ops, s,
 153                          TYPE_DIGIC_TIMER, 0x100);
 154    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
 155}
 156
 157static void digic_timer_finalize(Object *obj)
 158{
 159    DigicTimerState *s = DIGIC_TIMER(obj);
 160
 161    ptimer_free(s->ptimer);
 162}
 163
 164static void digic_timer_class_init(ObjectClass *klass, void *class_data)
 165{
 166    DeviceClass *dc = DEVICE_CLASS(klass);
 167
 168    dc->reset = digic_timer_reset;
 169    dc->vmsd = &vmstate_digic_timer;
 170}
 171
 172static const TypeInfo digic_timer_info = {
 173    .name = TYPE_DIGIC_TIMER,
 174    .parent = TYPE_SYS_BUS_DEVICE,
 175    .instance_size = sizeof(DigicTimerState),
 176    .instance_init = digic_timer_init,
 177    .instance_finalize = digic_timer_finalize,
 178    .class_init = digic_timer_class_init,
 179};
 180
 181static void digic_timer_register_type(void)
 182{
 183    type_register_static(&digic_timer_info);
 184}
 185
 186type_init(digic_timer_register_type)
 187