LXR qemu/include/exec/memattrs.h

   1/*
   2 * Memory transaction attributes
   3 *
   4 * Copyright (c) 2015 Linaro Limited.
   5 *
   6 * Authors:
   7 *  Peter Maydell <peter.maydell@linaro.org>
   8 *
   9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10 * See the COPYING file in the top-level directory.
  11 *
  12 */
  13
  14#ifndef MEMATTRS_H
  15#define MEMATTRS_H
  16
  17/* Every memory transaction has associated with it a set of
  18 * attributes. Some of these are generic (such as the ID of
  19 * the bus master); some are specific to a particular kind of
  20 * bus (such as the ARM Secure/NonSecure bit). We define them
  21 * all as non-overlapping bitfields in a single struct to avoid
  22 * confusion if different parts of QEMU used the same bit for
  23 * different semantics.
  24 */
  25typedef struct MemTxAttrs {
  26    /* Bus masters which don't specify any attributes will get this
  27     * (via the MEMTXATTRS_UNSPECIFIED constant), so that we can
  28     * distinguish "all attributes deliberately clear" from
  29     * "didn't specify" if necessary.
  30     */
  31    unsigned int unspecified:1;
  32    /* ARM/AMBA: TrustZone Secure access
  33     * x86: System Management Mode access
  34     */
  35    unsigned int secure:1;
  36    /* Memory access is usermode (unprivileged) */
  37    unsigned int user:1;
  38    /*
  39     * Bus interconnect and peripherals can access anything (memories,
  40     * devices) by default. By setting the 'memory' bit, bus transaction
  41     * are restricted to "normal" memories (per the AMBA documentation)
  42     * versus devices. Access to devices will be logged and rejected
  43     * (see MEMTX_ACCESS_ERROR).
  44     */
  45    unsigned int memory:1;
  46    /* Requester ID (for MSI for example) */
  47    unsigned int requester_id:16;
  48    /* Invert endianness for this page */
  49    unsigned int byte_swap:1;
  50    /*
  51     * The following are target-specific page-table bits.  These are not
  52     * related to actual memory transactions at all.  However, this structure
  53     * is part of the tlb_fill interface, cached in the cputlb structure,
  54     * and has unused bits.  These fields will be read by target-specific
  55     * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bitN.
  56     */
  57    unsigned int target_tlb_bit0 : 1;
  58    unsigned int target_tlb_bit1 : 1;
  59    unsigned int target_tlb_bit2 : 1;
  60} MemTxAttrs;
  61
  62/* Bus masters which don't specify any attributes will get this,
  63 * which has all attribute bits clear except the topmost one
  64 * (so that we can distinguish "all attributes deliberately clear"
  65 * from "didn't specify" if necessary).
  66 */
  67#define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified = 1 })
  68
  69/* New-style MMIO accessors can indicate that the transaction failed.
  70 * A zero (MEMTX_OK) response means success; anything else is a failure
  71 * of some kind. The memory subsystem will bitwise-OR together results
  72 * if it is synthesizing an operation from multiple smaller accesses.
  73 */
  74#define MEMTX_OK 0
  75#define MEMTX_ERROR             (1U << 0) /* device returned an error */
  76#define MEMTX_DECODE_ERROR      (1U << 1) /* nothing at that address */
  77#define MEMTX_ACCESS_ERROR      (1U << 2) /* access denied */
  78typedef uint32_t MemTxResult;
  79
  80#endif
  81