LXR qemu/include/hw/arm/npcm7xx.h

   1/*
   2 * Nuvoton NPCM7xx SoC family.
   3 *
   4 * Copyright 2020 Google LLC
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms of the GNU General Public License as published by the
   8 * Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful, but WITHOUT
  12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  14 * for more details.
  15 */
  16#ifndef NPCM7XX_H
  17#define NPCM7XX_H
  18
  19#include "hw/boards.h"
  20#include "hw/adc/npcm7xx_adc.h"
  21#include "hw/core/split-irq.h"
  22#include "hw/cpu/a9mpcore.h"
  23#include "hw/gpio/npcm7xx_gpio.h"
  24#include "hw/i2c/npcm7xx_smbus.h"
  25#include "hw/mem/npcm7xx_mc.h"
  26#include "hw/misc/npcm7xx_clk.h"
  27#include "hw/misc/npcm7xx_gcr.h"
  28#include "hw/misc/npcm7xx_mft.h"
  29#include "hw/misc/npcm7xx_pwm.h"
  30#include "hw/misc/npcm7xx_rng.h"
  31#include "hw/net/npcm7xx_emc.h"
  32#include "hw/nvram/npcm7xx_otp.h"
  33#include "hw/timer/npcm7xx_timer.h"
  34#include "hw/ssi/npcm7xx_fiu.h"
  35#include "hw/usb/hcd-ehci.h"
  36#include "hw/usb/hcd-ohci.h"
  37#include "target/arm/cpu.h"
  38#include "hw/sd/npcm7xx_sdhci.h"
  39
  40#define NPCM7XX_MAX_NUM_CPUS    (2)
  41
  42/* The first half of the address space is reserved for DDR4 DRAM. */
  43#define NPCM7XX_DRAM_BA         (0x00000000)
  44#define NPCM7XX_DRAM_SZ         (2 * GiB)
  45
  46/* Magic addresses for setting up direct kernel booting and SMP boot stubs. */
  47#define NPCM7XX_LOADER_START            (0x00000000)  /* Start of SDRAM */
  48#define NPCM7XX_SMP_LOADER_START        (0xffff0000)  /* Boot ROM */
  49#define NPCM7XX_SMP_BOOTREG_ADDR        (0xf080013c)  /* GCR.SCRPAD */
  50#define NPCM7XX_GIC_CPU_IF_ADDR         (0xf03fe100)  /* GIC within A9 */
  51#define NPCM7XX_BOARD_SETUP_ADDR        (0xffff1000)  /* Boot ROM */
  52
  53#define NPCM7XX_NR_PWM_MODULES 2
  54
  55typedef struct NPCM7xxMachine {
  56    MachineState        parent;
  57    /*
  58     * PWM fan splitter. each splitter connects to one PWM output and
  59     * multiple MFT inputs.
  60     */
  61    SplitIRQ            fan_splitter[NPCM7XX_NR_PWM_MODULES *
  62                                     NPCM7XX_PWM_PER_MODULE];
  63} NPCM7xxMachine;
  64
  65#define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx")
  66#define NPCM7XX_MACHINE(obj)                                            \
  67    OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE)
  68
  69typedef struct NPCM7xxMachineClass {
  70    MachineClass        parent;
  71
  72    const char          *soc_type;
  73} NPCM7xxMachineClass;
  74
  75#define NPCM7XX_MACHINE_CLASS(klass)                                    \
  76    OBJECT_CLASS_CHECK(NPCM7xxMachineClass, (klass), TYPE_NPCM7XX_MACHINE)
  77#define NPCM7XX_MACHINE_GET_CLASS(obj)                                  \
  78    OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE)
  79
  80typedef struct NPCM7xxState {
  81    DeviceState         parent;
  82
  83    ARMCPU              cpu[NPCM7XX_MAX_NUM_CPUS];
  84    A9MPPrivState       a9mpcore;
  85
  86    MemoryRegion        sram;
  87    MemoryRegion        irom;
  88    MemoryRegion        ram3;
  89    MemoryRegion        *dram;
  90
  91    NPCM7xxGCRState     gcr;
  92    NPCM7xxCLKState     clk;
  93    NPCM7xxTimerCtrlState tim[3];
  94    NPCM7xxADCState     adc;
  95    NPCM7xxPWMState     pwm[NPCM7XX_NR_PWM_MODULES];
  96    NPCM7xxMFTState     mft[8];
  97    NPCM7xxOTPState     key_storage;
  98    NPCM7xxOTPState     fuse_array;
  99    NPCM7xxMCState      mc;
 100    NPCM7xxRNGState     rng;
 101    NPCM7xxGPIOState    gpio[8];
 102    NPCM7xxSMBusState   smbus[16];
 103    EHCISysBusState     ehci;
 104    OHCISysBusState     ohci;
 105    NPCM7xxFIUState     fiu[2];
 106    NPCM7xxEMCState     emc[2];
 107    NPCM7xxSDHCIState   mmc;
 108} NPCM7xxState;
 109
 110#define TYPE_NPCM7XX    "npcm7xx"
 111#define NPCM7XX(obj)    OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX)
 112
 113#define TYPE_NPCM730    "npcm730"
 114#define TYPE_NPCM750    "npcm750"
 115
 116typedef struct NPCM7xxClass {
 117    DeviceClass         parent;
 118
 119    /* Bitmask of modules that are permanently disabled on this chip. */
 120    uint32_t            disabled_modules;
 121    /* Number of CPU cores enabled in this SoC class (may be 1 or 2). */
 122    uint32_t            num_cpus;
 123} NPCM7xxClass;
 124
 125#define NPCM7XX_CLASS(klass)                                            \
 126    OBJECT_CLASS_CHECK(NPCM7xxClass, (klass), TYPE_NPCM7XX)
 127#define NPCM7XX_GET_CLASS(obj)                                          \
 128    OBJECT_GET_CLASS(NPCM7xxClass, (obj), TYPE_NPCM7XX)
 129
 130/**
 131 * npcm7xx_load_kernel - Loads memory with everything needed to boot
 132 * @machine - The machine containing the SoC to be booted.
 133 * @soc - The SoC containing the CPU to be booted.
 134 *
 135 * This will set up the ARM boot info structure for the specific NPCM7xx
 136 * derivative and call arm_load_kernel() to set up loading of the kernel, etc.
 137 * into memory, if requested by the user.
 138 */
 139void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc);
 140
 141#endif /* NPCM7XX_H */
 142