1#ifndef HW_ICH9_H
2#define HW_ICH9_H
3
4#include "hw/isa/isa.h"
5#include "hw/sysbus.h"
6#include "hw/i386/pc.h"
7#include "hw/isa/apm.h"
8#include "hw/pci/pci.h"
9#include "hw/pci/pcie_host.h"
10#include "hw/pci/pci_bridge.h"
11#include "hw/acpi/acpi.h"
12#include "hw/acpi/ich9.h"
13#include "hw/pci/pci_bus.h"
14#include "qom/object.h"
15
16void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
17int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
18PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
19void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled);
20I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
21
22void ich9_generate_smi(void);
23
24#define ICH9_CC_SIZE (16 * 1024)
25
26#define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
27OBJECT_DECLARE_SIMPLE_TYPE(ICH9LPCState, ICH9_LPC_DEVICE)
28
29struct ICH9LPCState {
30
31 PCIDevice d;
32
33
34
35
36
37
38
39
40 uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
41
42 APMState apm;
43 ICH9LPCPMRegs pm;
44 uint32_t sci_level;
45 uint8_t sci_gsi;
46
47
48 struct {
49 bool spkr_hi;
50 } pin_strap;
51
52
53
54 uint8_t chip_config[ICH9_CC_SIZE];
55
56
57
58
59
60
61 uint8_t rst_cnt;
62 MemoryRegion rst_cnt_mem;
63
64
65 uint64_t smi_host_features;
66 uint8_t smi_host_features_le[8];
67
68 uint8_t smi_guest_features_le[8];
69
70 uint8_t smi_features_ok;
71
72 uint64_t smi_negotiated_features;
73
74
75 ISABus *isa_bus;
76 MemoryRegion rcrb_mem;
77 Notifier machine_ready;
78
79 qemu_irq gsi[GSI_NUM_PINS];
80};
81
82#define Q35_MASK(bit, ms_bit, ls_bit) \
83((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
84
85
86#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1)
87
88#define ICH9_CC
89#define ICH9_CC_D28IP 0x310C
90#define ICH9_CC_D28IP_SHIFT 4
91#define ICH9_CC_D28IP_MASK 0xf
92#define ICH9_CC_D28IP_DEFAULT 0x00214321
93#define ICH9_CC_D31IR 0x3140
94#define ICH9_CC_D30IR 0x3142
95#define ICH9_CC_D29IR 0x3144
96#define ICH9_CC_D28IR 0x3146
97#define ICH9_CC_D27IR 0x3148
98#define ICH9_CC_D26IR 0x314C
99#define ICH9_CC_D25IR 0x3150
100#define ICH9_CC_DIR_DEFAULT 0x3210
101#define ICH9_CC_D30IR_DEFAULT 0x0
102#define ICH9_CC_DIR_SHIFT 4
103#define ICH9_CC_DIR_MASK 0x7
104#define ICH9_CC_OIC 0x31FF
105#define ICH9_CC_OIC_AEN 0x1
106#define ICH9_CC_GCS 0x3410
107#define ICH9_CC_GCS_DEFAULT 0x00000020
108#define ICH9_CC_GCS_NO_REBOOT (1 << 5)
109
110
111#define ICH9_PCIE_DEV 28
112#define ICH9_PCIE_FUNC_MAX 6
113
114
115
116#define ICH9_USB_UHCI1_DEV 29
117#define ICH9_USB_UHCI1_FUNC 0
118
119
120#define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE"
121#define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0
122
123#define ICH9_D2P_BRIDGE_DEV 30
124#define ICH9_D2P_BRIDGE_FUNC 0
125
126#define ICH9_D2P_SECONDARY_DEFAULT (256 - 8)
127
128#define ICH9_D2P_A2_REVISION 0x92
129
130
131#define ICH9_RST_CNT_IOPORT 0xCF9
132
133
134#define ICH9_A2_LPC "ICH9 A2 LPC"
135#define ICH9_A2_LPC_SAVEVM_VERSION 0
136
137#define ICH9_LPC_DEV 31
138#define ICH9_LPC_FUNC 0
139
140#define ICH9_A2_LPC_REVISION 0x2
141#define ICH9_LPC_NB_PIRQS 8
142
143#define ICH9_LPC_PMBASE 0x40
144#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7)
145#define ICH9_LPC_PMBASE_RTE 0x1
146#define ICH9_LPC_PMBASE_DEFAULT 0x1
147
148#define ICH9_LPC_ACPI_CTRL 0x44
149#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80
150#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0)
151#define ICH9_LPC_ACPI_CTRL_9 0x0
152#define ICH9_LPC_ACPI_CTRL_10 0x1
153#define ICH9_LPC_ACPI_CTRL_11 0x2
154#define ICH9_LPC_ACPI_CTRL_20 0x4
155#define ICH9_LPC_ACPI_CTRL_21 0x5
156#define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0
157
158#define ICH9_LPC_PIRQA_ROUT 0x60
159#define ICH9_LPC_PIRQB_ROUT 0x61
160#define ICH9_LPC_PIRQC_ROUT 0x62
161#define ICH9_LPC_PIRQD_ROUT 0x63
162
163#define ICH9_LPC_PIRQE_ROUT 0x68
164#define ICH9_LPC_PIRQF_ROUT 0x69
165#define ICH9_LPC_PIRQG_ROUT 0x6a
166#define ICH9_LPC_PIRQH_ROUT 0x6b
167
168#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80
169#define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0)
170#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80
171
172#define ICH9_LPC_GEN_PMCON_1 0xa0
173#define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4)
174#define ICH9_LPC_GEN_PMCON_2 0xa2
175#define ICH9_LPC_GEN_PMCON_3 0xa4
176#define ICH9_LPC_GEN_PMCON_LOCK 0xa6
177
178#define ICH9_LPC_RCBA 0xf0
179#define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14)
180#define ICH9_LPC_RCBA_EN 0x1
181#define ICH9_LPC_RCBA_DEFAULT 0x0
182
183#define ICH9_LPC_PIC_NUM_PINS 16
184#define ICH9_LPC_IOAPIC_NUM_PINS 24
185
186#define ICH9_GPIO_GSI "gsi"
187
188
189#define ICH9_SATA1_DEV 31
190#define ICH9_SATA1_FUNC 2
191
192
193
194
195
196#define ICH9_PMIO_SIZE 128
197#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1)
198
199#define ICH9_PMIO_PM1_STS 0x00
200#define ICH9_PMIO_PM1_EN 0x02
201#define ICH9_PMIO_PM1_CNT 0x04
202#define ICH9_PMIO_PM1_TMR 0x08
203#define ICH9_PMIO_GPE0_STS 0x20
204#define ICH9_PMIO_GPE0_EN 0x28
205#define ICH9_PMIO_GPE0_LEN 16
206#define ICH9_PMIO_SMI_EN 0x30
207#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5)
208#define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13)
209#define ICH9_PMIO_SMI_STS 0x34
210#define ICH9_PMIO_TCO_RLD 0x60
211#define ICH9_PMIO_TCO_LEN 32
212
213
214#define ICH9_APM_ACPI_ENABLE 0x2
215#define ICH9_APM_ACPI_DISABLE 0x3
216
217
218
219#define TYPE_ICH9_SMB_DEVICE "ICH9-SMB"
220
221#define ICH9_A2_SMB_REVISION 0x02
222#define ICH9_SMB_PI 0x00
223
224#define ICH9_SMB_SMBMBAR0 0x10
225#define ICH9_SMB_SMBMBAR1 0x14
226#define ICH9_SMB_SMBM_BAR 0
227#define ICH9_SMB_SMBM_SIZE (1 << 8)
228#define ICH9_SMB_SMB_BASE 0x20
229#define ICH9_SMB_SMB_BASE_BAR 4
230#define ICH9_SMB_SMB_BASE_SIZE (1 << 5)
231#define ICH9_SMB_HOSTC 0x40
232#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3))
233#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2))
234#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1))
235#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0))
236
237
238#define ICH9_SMB_DEV 31
239#define ICH9_SMB_FUNC 3
240
241#define ICH9_SMB_HST_STS 0x00
242#define ICH9_SMB_HST_CNT 0x02
243#define ICH9_SMB_HST_CMD 0x03
244#define ICH9_SMB_XMIT_SLVA 0x04
245#define ICH9_SMB_HST_D0 0x05
246#define ICH9_SMB_HST_D1 0x06
247#define ICH9_SMB_HOST_BLOCK_DB 0x07
248
249#define ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP "x-smi-negotiated-features"
250
251
252#define ICH9_LPC_SMI_F_BROADCAST_BIT 0
253#define ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT 1
254#define ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT 2
255
256#endif
257