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24#ifndef HW_ARM_GICV3_COMMON_H
25#define HW_ARM_GICV3_COMMON_H
26
27#include "hw/sysbus.h"
28#include "hw/intc/arm_gic_common.h"
29#include "qom/object.h"
30
31
32
33
34
35
36#define GICV3_MAXIRQ 1020
37#define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL)
38
39#define GICV3_LPI_INTID_START 8192
40
41
42
43
44
45#define GICV3_REDIST_SIZE 0x20000
46#define GICV4_REDIST_SIZE 0x40000
47
48
49#define GICV3_TARGETLIST_BITS 16
50
51
52#define GICV3_LR_MAX 16
53
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66
67
68#define GICV3_BMP_SIZE DIV_ROUND_UP(GICV3_MAXIRQ, 32)
69
70#define GIC_DECLARE_BITMAP(name) \
71 uint32_t name[GICV3_BMP_SIZE]
72
73#define GIC_BIT_MASK(nr) (1U << ((nr) % 32))
74#define GIC_BIT_WORD(nr) ((nr) / 32)
75
76static inline void gic_bmp_set_bit(int nr, uint32_t *addr)
77{
78 uint32_t mask = GIC_BIT_MASK(nr);
79 uint32_t *p = addr + GIC_BIT_WORD(nr);
80
81 *p |= mask;
82}
83
84static inline void gic_bmp_clear_bit(int nr, uint32_t *addr)
85{
86 uint32_t mask = GIC_BIT_MASK(nr);
87 uint32_t *p = addr + GIC_BIT_WORD(nr);
88
89 *p &= ~mask;
90}
91
92static inline int gic_bmp_test_bit(int nr, const uint32_t *addr)
93{
94 return 1U & (addr[GIC_BIT_WORD(nr)] >> (nr & 31));
95}
96
97static inline void gic_bmp_replace_bit(int nr, uint32_t *addr, int val)
98{
99 uint32_t mask = GIC_BIT_MASK(nr);
100 uint32_t *p = addr + GIC_BIT_WORD(nr);
101
102 *p &= ~mask;
103 *p |= (val & 1U) << (nr % 32);
104}
105
106
107static inline uint32_t *gic_bmp_ptr32(uint32_t *addr, int nr)
108{
109 return addr + GIC_BIT_WORD(nr);
110}
111
112typedef struct GICv3State GICv3State;
113typedef struct GICv3CPUState GICv3CPUState;
114
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132
133#define GICV3_G0 0
134#define GICV3_G1 1
135#define GICV3_G1NS 2
136
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140
141
142#define GICV3_S 0
143#define GICV3_NS 1
144
145typedef struct {
146 int irq;
147 uint8_t prio;
148 int grp;
149} PendingIrq;
150
151struct GICv3CPUState {
152 GICv3State *gic;
153 CPUState *cpu;
154 qemu_irq parent_irq;
155 qemu_irq parent_fiq;
156 qemu_irq parent_virq;
157 qemu_irq parent_vfiq;
158
159
160 uint32_t level;
161
162 uint32_t gicr_ctlr;
163 uint64_t gicr_typer;
164 uint32_t gicr_statusr[2];
165 uint32_t gicr_waker;
166 uint64_t gicr_propbaser;
167 uint64_t gicr_pendbaser;
168
169 uint32_t gicr_igroupr0;
170 uint32_t gicr_ienabler0;
171 uint32_t gicr_ipendr0;
172 uint32_t gicr_iactiver0;
173 uint32_t edge_trigger;
174 uint32_t gicr_igrpmodr0;
175 uint32_t gicr_nsacr;
176 uint8_t gicr_ipriorityr[GIC_INTERNAL];
177
178 uint64_t gicr_vpropbaser;
179 uint64_t gicr_vpendbaser;
180
181
182 uint64_t icc_sre_el1;
183 uint64_t icc_ctlr_el1[2];
184 uint64_t icc_pmr_el1;
185 uint64_t icc_bpr[3];
186 uint64_t icc_apr[3][4];
187 uint64_t icc_igrpen[3];
188 uint64_t icc_ctlr_el3;
189
190
191 uint64_t ich_apr[3][4];
192 uint64_t ich_hcr_el2;
193 uint64_t ich_lr_el2[GICV3_LR_MAX];
194 uint64_t ich_vmcr_el2;
195
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198
199
200
201 int num_list_regs;
202 int vpribits;
203 int vprebits;
204 int pribits;
205 int prebits;
206
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210
211 PendingIrq hppi;
212
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216
217 PendingIrq hpplpi;
218
219
220 PendingIrq hppvlpi;
221
222
223 bool seenbetter;
224};
225
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228
229
230typedef struct GICv3RedistRegion {
231 GICv3State *gic;
232 MemoryRegion iomem;
233 uint32_t cpuidx;
234} GICv3RedistRegion;
235
236struct GICv3State {
237
238 SysBusDevice parent_obj;
239
240
241 MemoryRegion iomem_dist;
242 GICv3RedistRegion *redist_regions;
243 uint32_t *redist_region_count;
244 uint32_t nb_redist_regions;
245
246 uint32_t num_cpu;
247 uint32_t num_irq;
248 uint32_t revision;
249 bool lpi_enable;
250 bool security_extn;
251 bool force_8bit_prio;
252 bool irq_reset_nonsecure;
253 bool gicd_no_migration_shift_bug;
254
255 int dev_fd;
256 Error *migration_blocker;
257
258 MemoryRegion *dma;
259 AddressSpace dma_as;
260
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264
265
266 uint32_t gicd_ctlr;
267 uint32_t gicd_statusr[2];
268 GIC_DECLARE_BITMAP(group);
269 GIC_DECLARE_BITMAP(grpmod);
270 GIC_DECLARE_BITMAP(enabled);
271 GIC_DECLARE_BITMAP(pending);
272 GIC_DECLARE_BITMAP(active);
273 GIC_DECLARE_BITMAP(level);
274 GIC_DECLARE_BITMAP(edge_trigger);
275 uint8_t gicd_ipriority[GICV3_MAXIRQ];
276 uint64_t gicd_irouter[GICV3_MAXIRQ];
277
278
279
280 GICv3CPUState *gicd_irouter_target[GICV3_MAXIRQ];
281 uint32_t gicd_nsacr[DIV_ROUND_UP(GICV3_MAXIRQ, 16)];
282
283 GICv3CPUState *cpu;
284
285 GPtrArray *itslist;
286};
287
288#define GICV3_BITMAP_ACCESSORS(BMP) \
289 static inline void gicv3_gicd_##BMP##_set(GICv3State *s, int irq) \
290 { \
291 gic_bmp_set_bit(irq, s->BMP); \
292 } \
293 static inline int gicv3_gicd_##BMP##_test(GICv3State *s, int irq) \
294 { \
295 return gic_bmp_test_bit(irq, s->BMP); \
296 } \
297 static inline void gicv3_gicd_##BMP##_clear(GICv3State *s, int irq) \
298 { \
299 gic_bmp_clear_bit(irq, s->BMP); \
300 } \
301 static inline void gicv3_gicd_##BMP##_replace(GICv3State *s, \
302 int irq, int value) \
303 { \
304 gic_bmp_replace_bit(irq, s->BMP, value); \
305 }
306
307GICV3_BITMAP_ACCESSORS(group)
308GICV3_BITMAP_ACCESSORS(grpmod)
309GICV3_BITMAP_ACCESSORS(enabled)
310GICV3_BITMAP_ACCESSORS(pending)
311GICV3_BITMAP_ACCESSORS(active)
312GICV3_BITMAP_ACCESSORS(level)
313GICV3_BITMAP_ACCESSORS(edge_trigger)
314
315#define TYPE_ARM_GICV3_COMMON "arm-gicv3-common"
316typedef struct ARMGICv3CommonClass ARMGICv3CommonClass;
317DECLARE_OBJ_CHECKERS(GICv3State, ARMGICv3CommonClass,
318 ARM_GICV3_COMMON, TYPE_ARM_GICV3_COMMON)
319
320struct ARMGICv3CommonClass {
321
322 SysBusDeviceClass parent_class;
323
324
325 void (*pre_save)(GICv3State *s);
326 void (*post_load)(GICv3State *s);
327};
328
329void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
330 const MemoryRegionOps *ops);
331
332#endif
333