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20#ifndef PPC_PNV_H
21#define PPC_PNV_H
22
23#include "hw/boards.h"
24#include "hw/sysbus.h"
25#include "hw/ipmi/ipmi.h"
26#include "hw/ppc/pnv_lpc.h"
27#include "hw/ppc/pnv_pnor.h"
28#include "hw/ppc/pnv_psi.h"
29#include "hw/ppc/pnv_occ.h"
30#include "hw/ppc/pnv_homer.h"
31#include "hw/ppc/pnv_xive.h"
32#include "hw/ppc/pnv_core.h"
33#include "hw/pci-host/pnv_phb3.h"
34#include "hw/pci-host/pnv_phb4.h"
35#include "qom/object.h"
36
37#define TYPE_PNV_CHIP "pnv-chip"
38OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass,
39 PNV_CHIP)
40
41struct PnvChip {
42
43 SysBusDevice parent_obj;
44
45
46 uint32_t chip_id;
47 uint64_t ram_start;
48 uint64_t ram_size;
49
50 uint32_t nr_cores;
51 uint32_t nr_threads;
52 uint64_t cores_mask;
53 PnvCore **cores;
54
55 uint32_t num_pecs;
56
57 MemoryRegion xscom_mmio;
58 MemoryRegion xscom;
59 AddressSpace xscom_as;
60
61 MemoryRegion *fw_mr;
62 gchar *dt_isa_nodename;
63};
64
65#define TYPE_PNV8_CHIP "pnv8-chip"
66typedef struct Pnv8Chip Pnv8Chip;
67DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP,
68 TYPE_PNV8_CHIP)
69
70struct Pnv8Chip {
71
72 PnvChip parent_obj;
73
74
75 MemoryRegion icp_mmio;
76
77 PnvLpcController lpc;
78 Pnv8Psi psi;
79 PnvOCC occ;
80 PnvHomer homer;
81
82#define PNV8_CHIP_PHB3_MAX 4
83 PnvPHB3 phbs[PNV8_CHIP_PHB3_MAX];
84 uint32_t num_phbs;
85
86 XICSFabric *xics;
87};
88
89#define TYPE_PNV9_CHIP "pnv9-chip"
90typedef struct Pnv9Chip Pnv9Chip;
91DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP,
92 TYPE_PNV9_CHIP)
93
94struct Pnv9Chip {
95
96 PnvChip parent_obj;
97
98
99 PnvXive xive;
100 Pnv9Psi psi;
101 PnvLpcController lpc;
102 PnvOCC occ;
103 PnvHomer homer;
104
105 uint32_t nr_quads;
106 PnvQuad *quads;
107
108#define PNV9_CHIP_MAX_PEC 3
109 PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC];
110};
111
112
113
114
115#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
116#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
117
118#define TYPE_PNV10_CHIP "pnv10-chip"
119typedef struct Pnv10Chip Pnv10Chip;
120DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP,
121 TYPE_PNV10_CHIP)
122
123struct Pnv10Chip {
124
125 PnvChip parent_obj;
126
127
128 PnvXive2 xive;
129 Pnv9Psi psi;
130 PnvLpcController lpc;
131 PnvOCC occ;
132 PnvHomer homer;
133
134 uint32_t nr_quads;
135 PnvQuad *quads;
136
137#define PNV10_CHIP_MAX_PEC 2
138 PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC];
139};
140
141#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
142#define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
143
144struct PnvChipClass {
145
146 SysBusDeviceClass parent_class;
147
148
149 uint64_t chip_cfam_id;
150 uint64_t cores_mask;
151 uint32_t num_pecs;
152 uint32_t num_phbs;
153
154 DeviceRealize parent_realize;
155
156 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
157 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
158 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
159 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
160 void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon);
161 ISABus *(*isa_create)(PnvChip *chip, Error **errp);
162 void (*dt_populate)(PnvChip *chip, void *fdt);
163 void (*pic_print_info)(PnvChip *chip, Monitor *mon);
164 uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id);
165 uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr);
166};
167
168#define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
169#define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
170
171#define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
172DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8E,
173 TYPE_PNV_CHIP_POWER8E)
174
175#define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
176DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8,
177 TYPE_PNV_CHIP_POWER8)
178
179#define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
180DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL,
181 TYPE_PNV_CHIP_POWER8NVL)
182
183#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0")
184DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9,
185 TYPE_PNV_CHIP_POWER9)
186
187#define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v2.0")
188DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
189 TYPE_PNV_CHIP_POWER10)
190
191PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
192void pnv_phb_attach_root_port(PCIHostState *pci, const char *name,
193 int index, int chip_id);
194
195#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
196typedef struct PnvMachineClass PnvMachineClass;
197typedef struct PnvMachineState PnvMachineState;
198DECLARE_OBJ_CHECKERS(PnvMachineState, PnvMachineClass,
199 PNV_MACHINE, TYPE_PNV_MACHINE)
200
201
202struct PnvMachineClass {
203
204 MachineClass parent_class;
205
206
207 const char *compat;
208 int compat_size;
209
210 void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt);
211};
212
213struct PnvMachineState {
214
215 MachineState parent_obj;
216
217 uint32_t initrd_base;
218 long initrd_size;
219
220 uint32_t num_chips;
221 PnvChip **chips;
222
223 ISABus *isa_bus;
224 uint32_t cpld_irqstate;
225
226 IPMIBmc *bmc;
227 Notifier powerdown_notifier;
228
229 PnvPnor *pnor;
230
231 hwaddr fw_load_addr;
232};
233
234PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id);
235
236#define PNV_FDT_ADDR 0x01000000
237#define PNV_TIMEBASE_FREQ 512000000ULL
238
239
240
241
242void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
243void pnv_bmc_powerdown(IPMIBmc *bmc);
244IPMIBmc *pnv_bmc_create(PnvPnor *pnor);
245IPMIBmc *pnv_bmc_find(Error **errp);
246void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
247
248
249
250
251#define PNV_XSCOM_SIZE 0x800000000ull
252#define PNV_XSCOM_BASE(chip) \
253 (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
254
255#define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
256#define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull
257#define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \
258 PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
259
260#define PNV_HOMER_SIZE 0x0000000000400000ull
261#define PNV_HOMER_BASE(chip) \
262 (0x7ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE)
263
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277
278
279#define PNV_ICP_SIZE 0x0000000000100000ull
280#define PNV_ICP_BASE(chip) \
281 (0x0003ffff80000000ull + (uint64_t) (chip)->chip_id * PNV_ICP_SIZE)
282
283
284#define PNV_PSIHB_SIZE 0x0000000000100000ull
285#define PNV_PSIHB_BASE(chip) \
286 (0x0003fffe80000000ull + (uint64_t)(chip)->chip_id * PNV_PSIHB_SIZE)
287
288#define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull
289#define PNV_PSIHB_FSP_BASE(chip) \
290 (0x0003ffe000000000ull + (uint64_t)(chip)->chip_id * \
291 PNV_PSIHB_FSP_SIZE)
292
293
294
295
296#define PNV9_CHIP_BASE(chip, base) \
297 ((base) + ((uint64_t) (chip)->chip_id << 42))
298
299#define PNV9_XIVE_VC_SIZE 0x0000008000000000ull
300#define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull)
301
302#define PNV9_XIVE_PC_SIZE 0x0000001000000000ull
303#define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull)
304
305#define PNV9_LPCM_SIZE 0x0000000100000000ull
306#define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull)
307
308#define PNV9_PSIHB_SIZE 0x0000000000100000ull
309#define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull)
310
311#define PNV9_XIVE_IC_SIZE 0x0000000000080000ull
312#define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull)
313
314#define PNV9_XIVE_TM_SIZE 0x0000000000040000ull
315#define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull)
316
317#define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull
318#define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull)
319
320#define PNV9_XSCOM_SIZE 0x0000000400000000ull
321#define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull)
322
323#define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
324#define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull
325#define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \
326 PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
327
328#define PNV9_HOMER_SIZE 0x0000000000400000ull
329#define PNV9_HOMER_BASE(chip) \
330 (0x203ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV9_HOMER_SIZE)
331
332
333
334
335#define PNV10_CHIP_BASE(chip, base) \
336 ((base) + ((uint64_t) (chip)->chip_id << 44))
337
338#define PNV10_XSCOM_SIZE 0x0000000400000000ull
339#define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull)
340
341#define PNV10_LPCM_SIZE 0x0000000100000000ull
342#define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull)
343
344#define PNV10_XIVE2_IC_SIZE 0x0000000002000000ull
345#define PNV10_XIVE2_IC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030200000000ull)
346
347#define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull
348#define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull)
349
350#define PNV10_PSIHB_SIZE 0x0000000000100000ull
351#define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull)
352
353#define PNV10_XIVE2_TM_SIZE 0x0000000000040000ull
354#define PNV10_XIVE2_TM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203180000ull)
355
356#define PNV10_XIVE2_NVC_SIZE 0x0000000008000000ull
357#define PNV10_XIVE2_NVC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030208000000ull)
358
359#define PNV10_XIVE2_NVPG_SIZE 0x0000010000000000ull
360#define PNV10_XIVE2_NVPG_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006040000000000ull)
361
362#define PNV10_XIVE2_ESB_SIZE 0x0000010000000000ull
363#define PNV10_XIVE2_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006050000000000ull)
364
365#define PNV10_XIVE2_END_SIZE 0x0000020000000000ull
366#define PNV10_XIVE2_END_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006060000000000ull)
367
368#define PNV10_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
369#define PNV10_OCC_COMMON_AREA_BASE 0x300fff800000ull
370#define PNV10_OCC_SENSOR_BASE(chip) (PNV10_OCC_COMMON_AREA_BASE + \
371 PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
372
373#define PNV10_HOMER_SIZE 0x0000000000400000ull
374#define PNV10_HOMER_BASE(chip) \
375 (0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV10_HOMER_SIZE)
376
377#endif
378
