LXR qemu/include/hw/ppc/spapr.h

   1#ifndef HW_SPAPR_H
   2#define HW_SPAPR_H
   3
   4#include "qemu/units.h"
   5#include "sysemu/dma.h"
   6#include "hw/boards.h"
   7#include "hw/ppc/spapr_drc.h"
   8#include "hw/mem/pc-dimm.h"
   9#include "hw/ppc/spapr_ovec.h"
  10#include "hw/ppc/spapr_irq.h"
  11#include "qom/object.h"
  12#include "hw/ppc/spapr_xive.h"  /* For SpaprXive */
  13#include "hw/ppc/xics.h"        /* For ICSState */
  14#include "hw/ppc/spapr_tpm_proxy.h"
  15#include "hw/ppc/vof.h"
  16
  17struct SpaprVioBus;
  18struct SpaprPhbState;
  19struct SpaprNvram;
  20
  21typedef struct SpaprEventLogEntry SpaprEventLogEntry;
  22typedef struct SpaprEventSource SpaprEventSource;
  23typedef struct SpaprPendingHpt SpaprPendingHpt;
  24
  25#define HPTE64_V_HPTE_DIRTY     0x0000000000000040ULL
  26#define SPAPR_ENTRY_POINT       0x100
  27
  28#define SPAPR_TIMEBASE_FREQ     512000000ULL
  29
  30#define TYPE_SPAPR_RTC "spapr-rtc"
  31
  32OBJECT_DECLARE_SIMPLE_TYPE(SpaprRtcState, SPAPR_RTC)
  33
  34struct SpaprRtcState {
  35    /*< private >*/
  36    DeviceState parent_obj;
  37    int64_t ns_offset;
  38};
  39
  40typedef struct SpaprDimmState SpaprDimmState;
  41
  42#define TYPE_SPAPR_MACHINE      "spapr-machine"
  43OBJECT_DECLARE_TYPE(SpaprMachineState, SpaprMachineClass, SPAPR_MACHINE)
  44
  45typedef enum {
  46    SPAPR_RESIZE_HPT_DEFAULT = 0,
  47    SPAPR_RESIZE_HPT_DISABLED,
  48    SPAPR_RESIZE_HPT_ENABLED,
  49    SPAPR_RESIZE_HPT_REQUIRED,
  50} SpaprResizeHpt;
  51
  52/**
  53 * Capabilities
  54 */
  55
  56/* Hardware Transactional Memory */
  57#define SPAPR_CAP_HTM                   0x00
  58/* Vector Scalar Extensions */
  59#define SPAPR_CAP_VSX                   0x01
  60/* Decimal Floating Point */
  61#define SPAPR_CAP_DFP                   0x02
  62/* Cache Flush on Privilege Change */
  63#define SPAPR_CAP_CFPC                  0x03
  64/* Speculation Barrier Bounds Checking */
  65#define SPAPR_CAP_SBBC                  0x04
  66/* Indirect Branch Serialisation */
  67#define SPAPR_CAP_IBS                   0x05
  68/* HPT Maximum Page Size (encoded as a shift) */
  69#define SPAPR_CAP_HPT_MAXPAGESIZE       0x06
  70/* Nested KVM-HV */
  71#define SPAPR_CAP_NESTED_KVM_HV         0x07
  72/* Large Decrementer */
  73#define SPAPR_CAP_LARGE_DECREMENTER     0x08
  74/* Count Cache Flush Assist HW Instruction */
  75#define SPAPR_CAP_CCF_ASSIST            0x09
  76/* Implements PAPR FWNMI option */
  77#define SPAPR_CAP_FWNMI                 0x0A
  78/* Support H_RPT_INVALIDATE */
  79#define SPAPR_CAP_RPT_INVALIDATE        0x0B
  80/* Num Caps */
  81#define SPAPR_CAP_NUM                   (SPAPR_CAP_RPT_INVALIDATE + 1)
  82
  83/*
  84 * Capability Values
  85 */
  86/* Bool Caps */
  87#define SPAPR_CAP_OFF                   0x00
  88#define SPAPR_CAP_ON                    0x01
  89
  90/* Custom Caps */
  91
  92/* Generic */
  93#define SPAPR_CAP_BROKEN                0x00
  94#define SPAPR_CAP_WORKAROUND            0x01
  95#define SPAPR_CAP_FIXED                 0x02
  96/* SPAPR_CAP_IBS (cap-ibs) */
  97#define SPAPR_CAP_FIXED_IBS             0x02
  98#define SPAPR_CAP_FIXED_CCD             0x03
  99#define SPAPR_CAP_FIXED_NA              0x10 /* Lets leave a bit of a gap... */
 100
 101#define FDT_MAX_SIZE                    0x200000
 102
 103/* Max number of GPUs per system */
 104#define NVGPU_MAX_NUM              6
 105
 106/* Max number of NUMA nodes */
 107#define NUMA_NODES_MAX_NUM         (MAX_NODES + NVGPU_MAX_NUM)
 108
 109/*
 110 * NUMA FORM1 macros. FORM1_DIST_REF_POINTS was taken from
 111 * MAX_DISTANCE_REF_POINTS in arch/powerpc/mm/numa.h from Linux
 112 * kernel source. It represents the amount of associativity domains
 113 * for non-CPU resources.
 114 *
 115 * FORM1_NUMA_ASSOC_SIZE is the base array size of an ibm,associativity
 116 * array for any non-CPU resource.
 117 */
 118#define FORM1_DIST_REF_POINTS            4
 119#define FORM1_NUMA_ASSOC_SIZE            (FORM1_DIST_REF_POINTS + 1)
 120
 121/*
 122 * FORM2 NUMA affinity has a single associativity domain, giving
 123 * us a assoc size of 2.
 124 */
 125#define FORM2_DIST_REF_POINTS            1
 126#define FORM2_NUMA_ASSOC_SIZE            (FORM2_DIST_REF_POINTS + 1)
 127
 128typedef struct SpaprCapabilities SpaprCapabilities;
 129struct SpaprCapabilities {
 130    uint8_t caps[SPAPR_CAP_NUM];
 131};
 132
 133/**
 134 * SpaprMachineClass:
 135 */
 136struct SpaprMachineClass {
 137    /*< private >*/
 138    MachineClass parent_class;
 139
 140    /*< public >*/
 141    bool dr_lmb_enabled;       /* enable dynamic-reconfig/hotplug of LMBs */
 142    bool dr_phb_enabled;       /* enable dynamic-reconfig/hotplug of PHBs */
 143    bool update_dt_enabled;    /* enable KVMPPC_H_UPDATE_DT */
 144    bool use_ohci_by_default;  /* use USB-OHCI instead of XHCI */
 145    bool pre_2_10_has_unused_icps;
 146    bool legacy_irq_allocation;
 147    uint32_t nr_xirqs;
 148    bool broken_host_serial_model; /* present real host info to the guest */
 149    bool pre_4_1_migration; /* don't migrate hpt-max-page-size */
 150    bool linux_pci_probe;
 151    bool smp_threads_vsmt; /* set VSMT to smp_threads by default */
 152    hwaddr rma_limit;          /* clamp the RMA to this size */
 153    bool pre_5_1_assoc_refpoints;
 154    bool pre_5_2_numa_associativity;
 155    bool pre_6_2_numa_affinity;
 156
 157    bool (*phb_placement)(SpaprMachineState *spapr, uint32_t index,
 158                          uint64_t *buid, hwaddr *pio,
 159                          hwaddr *mmio32, hwaddr *mmio64,
 160                          unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa,
 161                          hwaddr *nv2atsd, Error **errp);
 162    SpaprResizeHpt resize_hpt_default;
 163    SpaprCapabilities default_caps;
 164    SpaprIrq *irq;
 165};
 166
 167#define WDT_MAX_WATCHDOGS       4      /* Maximum number of watchdog devices */
 168
 169#define TYPE_SPAPR_WDT "spapr-wdt"
 170OBJECT_DECLARE_SIMPLE_TYPE(SpaprWatchdog, SPAPR_WDT)
 171
 172typedef struct SpaprWatchdog {
 173    /*< private >*/
 174    DeviceState parent_obj;
 175    /*< public >*/
 176
 177    QEMUTimer timer;
 178    uint8_t action;         /* One of PSERIES_WDTF_ACTION_xxx */
 179    uint8_t leave_others;   /* leaveOtherWatchdogsRunningOnTimeout */
 180} SpaprWatchdog;
 181
 182/**
 183 * SpaprMachineState:
 184 */
 185struct SpaprMachineState {
 186    /*< private >*/
 187    MachineState parent_obj;
 188
 189    struct SpaprVioBus *vio_bus;
 190    QLIST_HEAD(, SpaprPhbState) phbs;
 191    struct SpaprNvram *nvram;
 192    SpaprRtcState rtc;
 193
 194    SpaprResizeHpt resize_hpt;
 195    void *htab;
 196    uint32_t htab_shift;
 197    uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROC_TBL */
 198    SpaprPendingHpt *pending_hpt; /* in-progress resize */
 199
 200    hwaddr rma_size;
 201    uint32_t fdt_size;
 202    uint32_t fdt_initial_size;
 203    void *fdt_blob;
 204    long kernel_size;
 205    bool kernel_le;
 206    uint64_t kernel_addr;
 207    uint32_t initrd_base;
 208    long initrd_size;
 209    Vof *vof;
 210    uint64_t rtc_offset; /* Now used only during incoming migration */
 211    struct PPCTimebase tb;
 212    bool want_stdout_path;
 213    uint32_t vsmt;       /* Virtual SMT mode (KVM's "core stride") */
 214
 215    /* Nested HV support (TCG only) */
 216    uint64_t nested_ptcr;
 217
 218    Notifier epow_notifier;
 219    QTAILQ_HEAD(, SpaprEventLogEntry) pending_events;
 220    bool use_hotplug_event_source;
 221    SpaprEventSource *event_sources;
 222
 223    /* ibm,client-architecture-support option negotiation */
 224    bool cas_pre_isa3_guest;
 225    SpaprOptionVector *ov5;         /* QEMU-supported option vectors */
 226    SpaprOptionVector *ov5_cas;     /* negotiated (via CAS) option vectors */
 227    uint32_t max_compat_pvr;
 228
 229    /* Migration state */
 230    int htab_save_index;
 231    bool htab_first_pass;
 232    int htab_fd;
 233
 234    /* Pending DIMM unplug cache. It is populated when a LMB
 235     * unplug starts. It can be regenerated if a migration
 236     * occurs during the unplug process. */
 237    QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs;
 238
 239    /* State related to FWNMI option */
 240
 241    /* System Reset and Machine Check Notification Routine addresses
 242     * registered by "ibm,nmi-register" RTAS call.
 243     */
 244    target_ulong fwnmi_system_reset_addr;
 245    target_ulong fwnmi_machine_check_addr;
 246
 247    /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is
 248     * set to -1 if a FWNMI machine check is not in progress, else is set to
 249     * the CPU that was delivered the machine check, and is set back to -1
 250     * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used
 251     * to synchronize other CPUs.
 252     */
 253    int fwnmi_machine_check_interlock;
 254    QemuCond fwnmi_machine_check_interlock_cond;
 255
 256    /* Set by -boot */
 257    char *boot_device;
 258
 259    /*< public >*/
 260    char *kvm_type;
 261    char *host_model;
 262    char *host_serial;
 263
 264    int32_t irq_map_nr;
 265    unsigned long *irq_map;
 266    SpaprIrq *irq;
 267    qemu_irq *qirqs;
 268    SpaprInterruptController *active_intc;
 269    ICSState *ics;
 270    SpaprXive *xive;
 271
 272    bool cmd_line_caps[SPAPR_CAP_NUM];
 273    SpaprCapabilities def, eff, mig;
 274
 275    unsigned gpu_numa_id;
 276    SpaprTpmProxy *tpm_proxy;
 277
 278    uint32_t FORM1_assoc_array[NUMA_NODES_MAX_NUM][FORM1_NUMA_ASSOC_SIZE];
 279    uint32_t FORM2_assoc_array[NUMA_NODES_MAX_NUM][FORM2_NUMA_ASSOC_SIZE];
 280
 281    Error *fwnmi_migration_blocker;
 282
 283    SpaprWatchdog wds[WDT_MAX_WATCHDOGS];
 284};
 285
 286#define H_SUCCESS         0
 287#define H_BUSY            1        /* Hardware busy -- retry later */
 288#define H_CLOSED          2        /* Resource closed */
 289#define H_NOT_AVAILABLE   3
 290#define H_CONSTRAINED     4        /* Resource request constrained to max allowed */
 291#define H_PARTIAL         5
 292#define H_IN_PROGRESS     14       /* Kind of like busy */
 293#define H_PAGE_REGISTERED 15
 294#define H_PARTIAL_STORE   16
 295#define H_PENDING         17       /* returned from H_POLL_PENDING */
 296#define H_CONTINUE        18       /* Returned from H_Join on success */
 297#define H_LONG_BUSY_START_RANGE         9900  /* Start of long busy range */
 298#define H_LONG_BUSY_ORDER_1_MSEC        9900  /* Long busy, hint that 1msec \
 299                                                 is a good time to retry */
 300#define H_LONG_BUSY_ORDER_10_MSEC       9901  /* Long busy, hint that 10msec \
 301                                                 is a good time to retry */
 302#define H_LONG_BUSY_ORDER_100_MSEC      9902  /* Long busy, hint that 100msec \
 303                                                 is a good time to retry */
 304#define H_LONG_BUSY_ORDER_1_SEC         9903  /* Long busy, hint that 1sec \
 305                                                 is a good time to retry */
 306#define H_LONG_BUSY_ORDER_10_SEC        9904  /* Long busy, hint that 10sec \
 307                                                 is a good time to retry */
 308#define H_LONG_BUSY_ORDER_100_SEC       9905  /* Long busy, hint that 100sec \
 309                                                 is a good time to retry */
 310#define H_LONG_BUSY_END_RANGE           9905  /* End of long busy range */
 311#define H_HARDWARE        -1       /* Hardware error */
 312#define H_FUNCTION        -2       /* Function not supported */
 313#define H_PRIVILEGE       -3       /* Caller not privileged */
 314#define H_PARAMETER       -4       /* Parameter invalid, out-of-range or conflicting */
 315#define H_BAD_MODE        -5       /* Illegal msr value */
 316#define H_PTEG_FULL       -6       /* PTEG is full */
 317#define H_NOT_FOUND       -7       /* PTE was not found" */
 318#define H_RESERVED_DABR   -8       /* DABR address is reserved by the hypervisor on this processor" */
 319#define H_NO_MEM          -9
 320#define H_AUTHORITY       -10
 321#define H_PERMISSION      -11
 322#define H_DROPPED         -12
 323#define H_SOURCE_PARM     -13
 324#define H_DEST_PARM       -14
 325#define H_REMOTE_PARM     -15
 326#define H_RESOURCE        -16
 327#define H_ADAPTER_PARM    -17
 328#define H_RH_PARM         -18
 329#define H_RCQ_PARM        -19
 330#define H_SCQ_PARM        -20
 331#define H_EQ_PARM         -21
 332#define H_RT_PARM         -22
 333#define H_ST_PARM         -23
 334#define H_SIGT_PARM       -24
 335#define H_TOKEN_PARM      -25
 336#define H_MLENGTH_PARM    -27
 337#define H_MEM_PARM        -28
 338#define H_MEM_ACCESS_PARM -29
 339#define H_ATTR_PARM       -30
 340#define H_PORT_PARM       -31
 341#define H_MCG_PARM        -32
 342#define H_VL_PARM         -33
 343#define H_TSIZE_PARM      -34
 344#define H_TRACE_PARM      -35
 345
 346#define H_MASK_PARM       -37
 347#define H_MCG_FULL        -38
 348#define H_ALIAS_EXIST     -39
 349#define H_P_COUNTER       -40
 350#define H_TABLE_FULL      -41
 351#define H_ALT_TABLE       -42
 352#define H_MR_CONDITION    -43
 353#define H_NOT_ENOUGH_RESOURCES -44
 354#define H_R_STATE         -45
 355#define H_RESCINDEND      -46
 356#define H_P2              -55
 357#define H_P3              -56
 358#define H_P4              -57
 359#define H_P5              -58
 360#define H_P6              -59
 361#define H_P7              -60
 362#define H_P8              -61
 363#define H_P9              -62
 364#define H_NOOP            -63
 365#define H_UNSUPPORTED     -67
 366#define H_OVERLAP         -68
 367#define H_UNSUPPORTED_FLAG -256
 368#define H_MULTI_THREADS_ACTIVE -9005
 369
 370
 371/* Long Busy is a condition that can be returned by the firmware
 372 * when a call cannot be completed now, but the identical call
 373 * should be retried later.  This prevents calls blocking in the
 374 * firmware for long periods of time.  Annoyingly the firmware can return
 375 * a range of return codes, hinting at how long we should wait before
 376 * retrying.  If you don't care for the hint, the macro below is a good
 377 * way to check for the long_busy return codes
 378 */
 379#define H_IS_LONG_BUSY(x)  ((x >= H_LONG_BUSY_START_RANGE) \
 380                            && (x <= H_LONG_BUSY_END_RANGE))
 381
 382/* Flags */
 383#define H_LARGE_PAGE      (1ULL<<(63-16))
 384#define H_EXACT           (1ULL<<(63-24))       /* Use exact PTE or return H_PTEG_FULL */
 385#define H_R_XLATE         (1ULL<<(63-25))       /* include a valid logical page num in the pte if the valid bit is set */
 386#define H_READ_4          (1ULL<<(63-26))       /* Return 4 PTEs */
 387#define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
 388#define H_PAGE_UNUSED     ((1ULL<<(63-29)) | (1ULL<<(63-30)))
 389#define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
 390#define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
 391#define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
 392#define H_AVPN            (1ULL<<(63-32))       /* An avpn is provided as a sanity test */
 393#define H_ANDCOND         (1ULL<<(63-33))
 394#define H_ICACHE_INVALIDATE (1ULL<<(63-40))     /* icbi, etc.  (ignored for IO pages) */
 395#define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41))    /* dcbst, icbi, etc (ignored for IO pages */
 396#define H_ZERO_PAGE       (1ULL<<(63-48))       /* zero the page before mapping (ignored for IO pages) */
 397#define H_COPY_PAGE       (1ULL<<(63-49))
 398#define H_N               (1ULL<<(63-61))
 399#define H_PP1             (1ULL<<(63-62))
 400#define H_PP2             (1ULL<<(63-63))
 401
 402/* Values for 2nd argument to H_SET_MODE */
 403#define H_SET_MODE_RESOURCE_SET_CIABR           1
 404#define H_SET_MODE_RESOURCE_SET_DAWR0           2
 405#define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE     3
 406#define H_SET_MODE_RESOURCE_LE                  4
 407
 408/* Flags for H_SET_MODE_RESOURCE_LE */
 409#define H_SET_MODE_ENDIAN_BIG    0
 410#define H_SET_MODE_ENDIAN_LITTLE 1
 411
 412/* VASI States */
 413#define H_VASI_INVALID    0
 414#define H_VASI_ENABLED    1
 415#define H_VASI_ABORTED    2
 416#define H_VASI_SUSPENDING 3
 417#define H_VASI_SUSPENDED  4
 418#define H_VASI_RESUMED    5
 419#define H_VASI_COMPLETED  6
 420
 421/* DABRX flags */
 422#define H_DABRX_HYPERVISOR (1ULL<<(63-61))
 423#define H_DABRX_KERNEL     (1ULL<<(63-62))
 424#define H_DABRX_USER       (1ULL<<(63-63))
 425
 426/* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */
 427#define H_CPU_CHAR_SPEC_BAR_ORI31               PPC_BIT(0)
 428#define H_CPU_CHAR_BCCTRL_SERIALISED            PPC_BIT(1)
 429#define H_CPU_CHAR_L1D_FLUSH_ORI30              PPC_BIT(2)
 430#define H_CPU_CHAR_L1D_FLUSH_TRIG2              PPC_BIT(3)
 431#define H_CPU_CHAR_L1D_THREAD_PRIV              PPC_BIT(4)
 432#define H_CPU_CHAR_HON_BRANCH_HINTS             PPC_BIT(5)
 433#define H_CPU_CHAR_THR_RECONF_TRIG              PPC_BIT(6)
 434#define H_CPU_CHAR_CACHE_COUNT_DIS              PPC_BIT(7)
 435#define H_CPU_CHAR_BCCTR_FLUSH_ASSIST           PPC_BIT(9)
 436
 437#define H_CPU_BEHAV_FAVOUR_SECURITY             PPC_BIT(0)
 438#define H_CPU_BEHAV_L1D_FLUSH_PR                PPC_BIT(1)
 439#define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR           PPC_BIT(2)
 440#define H_CPU_BEHAV_FLUSH_COUNT_CACHE           PPC_BIT(5)
 441#define H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY          PPC_BIT(7)
 442#define H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS        PPC_BIT(8)
 443
 444/* Each control block has to be on a 4K boundary */
 445#define H_CB_ALIGNMENT     4096
 446
 447/* pSeries hypervisor opcodes */
 448#define H_REMOVE                0x04
 449#define H_ENTER                 0x08
 450#define H_READ                  0x0c
 451#define H_CLEAR_MOD             0x10
 452#define H_CLEAR_REF             0x14
 453#define H_PROTECT               0x18
 454#define H_GET_TCE               0x1c
 455#define H_PUT_TCE               0x20
 456#define H_SET_SPRG0             0x24
 457#define H_SET_DABR              0x28
 458#define H_PAGE_INIT             0x2c
 459#define H_SET_ASR               0x30
 460#define H_ASR_ON                0x34
 461#define H_ASR_OFF               0x38
 462#define H_LOGICAL_CI_LOAD       0x3c
 463#define H_LOGICAL_CI_STORE      0x40
 464#define H_LOGICAL_CACHE_LOAD    0x44
 465#define H_LOGICAL_CACHE_STORE   0x48
 466#define H_LOGICAL_ICBI          0x4c
 467#define H_LOGICAL_DCBF          0x50
 468#define H_GET_TERM_CHAR         0x54
 469#define H_PUT_TERM_CHAR         0x58
 470#define H_REAL_TO_LOGICAL       0x5c
 471#define H_HYPERVISOR_DATA       0x60
 472#define H_EOI                   0x64
 473#define H_CPPR                  0x68
 474#define H_IPI                   0x6c
 475#define H_IPOLL                 0x70
 476#define H_XIRR                  0x74
 477#define H_PERFMON               0x7c
 478#define H_MIGRATE_DMA           0x78
 479#define H_REGISTER_VPA          0xDC
 480#define H_CEDE                  0xE0
 481#define H_CONFER                0xE4
 482#define H_PROD                  0xE8
 483#define H_GET_PPP               0xEC
 484#define H_SET_PPP               0xF0
 485#define H_PURR                  0xF4
 486#define H_PIC                   0xF8
 487#define H_REG_CRQ               0xFC
 488#define H_FREE_CRQ              0x100
 489#define H_VIO_SIGNAL            0x104
 490#define H_SEND_CRQ              0x108
 491#define H_COPY_RDMA             0x110
 492#define H_REGISTER_LOGICAL_LAN  0x114
 493#define H_FREE_LOGICAL_LAN      0x118
 494#define H_ADD_LOGICAL_LAN_BUFFER 0x11C
 495#define H_SEND_LOGICAL_LAN      0x120
 496#define H_BULK_REMOVE           0x124
 497#define H_MULTICAST_CTRL        0x130
 498#define H_SET_XDABR             0x134
 499#define H_STUFF_TCE             0x138
 500#define H_PUT_TCE_INDIRECT      0x13C
 501#define H_CHANGE_LOGICAL_LAN_MAC 0x14C
 502#define H_VTERM_PARTNER_INFO    0x150
 503#define H_REGISTER_VTERM        0x154
 504#define H_FREE_VTERM            0x158
 505#define H_RESET_EVENTS          0x15C
 506#define H_ALLOC_RESOURCE        0x160
 507#define H_FREE_RESOURCE         0x164
 508#define H_MODIFY_QP             0x168
 509#define H_QUERY_QP              0x16C
 510#define H_REREGISTER_PMR        0x170
 511#define H_REGISTER_SMR          0x174
 512#define H_QUERY_MR              0x178
 513#define H_QUERY_MW              0x17C
 514#define H_QUERY_HCA             0x180
 515#define H_QUERY_PORT            0x184
 516#define H_MODIFY_PORT           0x188
 517#define H_DEFINE_AQP1           0x18C
 518#define H_GET_TRACE_BUFFER      0x190
 519#define H_DEFINE_AQP0           0x194
 520#define H_RESIZE_MR             0x198
 521#define H_ATTACH_MCQP           0x19C
 522#define H_DETACH_MCQP           0x1A0
 523#define H_CREATE_RPT            0x1A4
 524#define H_REMOVE_RPT            0x1A8
 525#define H_REGISTER_RPAGES       0x1AC
 526#define H_DISABLE_AND_GETC      0x1B0
 527#define H_ERROR_DATA            0x1B4
 528#define H_GET_HCA_INFO          0x1B8
 529#define H_GET_PERF_COUNT        0x1BC
 530#define H_MANAGE_TRACE          0x1C0
 531#define H_GET_CPU_CHARACTERISTICS 0x1C8
 532#define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
 533#define H_QUERY_INT_STATE       0x1E4
 534#define H_POLL_PENDING          0x1D8
 535#define H_ILLAN_ATTRIBUTES      0x244
 536#define H_MODIFY_HEA_QP         0x250
 537#define H_QUERY_HEA_QP          0x254
 538#define H_QUERY_HEA             0x258
 539#define H_QUERY_HEA_PORT        0x25C
 540#define H_MODIFY_HEA_PORT       0x260
 541#define H_REG_BCMC              0x264
 542#define H_DEREG_BCMC            0x268
 543#define H_REGISTER_HEA_RPAGES   0x26C
 544#define H_DISABLE_AND_GET_HEA   0x270
 545#define H_GET_HEA_INFO          0x274
 546#define H_ALLOC_HEA_RESOURCE    0x278
 547#define H_ADD_CONN              0x284
 548#define H_DEL_CONN              0x288
 549#define H_JOIN                  0x298
 550#define H_VASI_STATE            0x2A4
 551#define H_ENABLE_CRQ            0x2B0
 552#define H_GET_EM_PARMS          0x2B8
 553#define H_SET_MPP               0x2D0
 554#define H_GET_MPP               0x2D4
 555#define H_HOME_NODE_ASSOCIATIVITY 0x2EC
 556#define H_XIRR_X                0x2FC
 557#define H_RANDOM                0x300
 558#define H_SET_MODE              0x31C
 559#define H_RESIZE_HPT_PREPARE    0x36C
 560#define H_RESIZE_HPT_COMMIT     0x370
 561#define H_CLEAN_SLB             0x374
 562#define H_INVALIDATE_PID        0x378
 563#define H_REGISTER_PROC_TBL     0x37C
 564#define H_SIGNAL_SYS_RESET      0x380
 565
 566#define H_INT_GET_SOURCE_INFO   0x3A8
 567#define H_INT_SET_SOURCE_CONFIG 0x3AC
 568#define H_INT_GET_SOURCE_CONFIG 0x3B0
 569#define H_INT_GET_QUEUE_INFO    0x3B4
 570#define H_INT_SET_QUEUE_CONFIG  0x3B8
 571#define H_INT_GET_QUEUE_CONFIG  0x3BC
 572#define H_INT_SET_OS_REPORTING_LINE 0x3C0
 573#define H_INT_GET_OS_REPORTING_LINE 0x3C4
 574#define H_INT_ESB               0x3C8
 575#define H_INT_SYNC              0x3CC
 576#define H_INT_RESET             0x3D0
 577#define H_SCM_READ_METADATA     0x3E4
 578#define H_SCM_WRITE_METADATA    0x3E8
 579#define H_SCM_BIND_MEM          0x3EC
 580#define H_SCM_UNBIND_MEM        0x3F0
 581#define H_SCM_UNBIND_ALL        0x3FC
 582#define H_SCM_HEALTH            0x400
 583#define H_RPT_INVALIDATE        0x448
 584#define H_SCM_FLUSH             0x44C
 585#define H_WATCHDOG              0x45C
 586
 587#define MAX_HCALL_OPCODE        H_WATCHDOG
 588
 589/* The hcalls above are standardized in PAPR and implemented by pHyp
 590 * as well.
 591 *
 592 * We also need some hcalls which are specific to qemu / KVM-on-POWER.
 593 * We put those into the 0xf000-0xfffc range which is reserved by PAPR
 594 * for "platform-specific" hcalls.
 595 */
 596#define KVMPPC_HCALL_BASE       0xf000
 597#define KVMPPC_H_RTAS           (KVMPPC_HCALL_BASE + 0x0)
 598#define KVMPPC_H_LOGICAL_MEMOP  (KVMPPC_HCALL_BASE + 0x1)
 599/* Client Architecture support */
 600#define KVMPPC_H_CAS            (KVMPPC_HCALL_BASE + 0x2)
 601#define KVMPPC_H_UPDATE_DT      (KVMPPC_HCALL_BASE + 0x3)
 602/* 0x4 was used for KVMPPC_H_UPDATE_PHANDLE in SLOF */
 603#define KVMPPC_H_VOF_CLIENT     (KVMPPC_HCALL_BASE + 0x5)
 604
 605/* Platform-specific hcalls used for nested HV KVM */
 606#define KVMPPC_H_SET_PARTITION_TABLE   (KVMPPC_HCALL_BASE + 0x800)
 607#define KVMPPC_H_ENTER_NESTED          (KVMPPC_HCALL_BASE + 0x804)
 608#define KVMPPC_H_TLB_INVALIDATE        (KVMPPC_HCALL_BASE + 0x808)
 609#define KVMPPC_H_COPY_TOFROM_GUEST     (KVMPPC_HCALL_BASE + 0x80C)
 610
 611#define KVMPPC_HCALL_MAX        KVMPPC_H_COPY_TOFROM_GUEST
 612
 613/*
 614 * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating
 615 * Secure VM mode via an Ultravisor / Protected Execution Facility
 616 */
 617#define SVM_HCALL_BASE              0xEF00
 618#define SVM_H_TPM_COMM              0xEF10
 619#define SVM_HCALL_MAX               SVM_H_TPM_COMM
 620
 621/*
 622 * Register state for entering a nested guest with H_ENTER_NESTED.
 623 * New member must be added at the end.
 624 */
 625struct kvmppc_hv_guest_state {
 626    uint64_t version;      /* version of this structure layout, must be first */
 627    uint32_t lpid;
 628    uint32_t vcpu_token;
 629    /* These registers are hypervisor privileged (at least for writing) */
 630    uint64_t lpcr;
 631    uint64_t pcr;
 632    uint64_t amor;
 633    uint64_t dpdes;
 634    uint64_t hfscr;
 635    int64_t tb_offset;
 636    uint64_t dawr0;
 637    uint64_t dawrx0;
 638    uint64_t ciabr;
 639    uint64_t hdec_expiry;
 640    uint64_t purr;
 641    uint64_t spurr;
 642    uint64_t ic;
 643    uint64_t vtb;
 644    uint64_t hdar;
 645    uint64_t hdsisr;
 646    uint64_t heir;
 647    uint64_t asdr;
 648    /* These are OS privileged but need to be set late in guest entry */
 649    uint64_t srr0;
 650    uint64_t srr1;
 651    uint64_t sprg[4];
 652    uint64_t pidr;
 653    uint64_t cfar;
 654    uint64_t ppr;
 655    /* Version 1 ends here */
 656    uint64_t dawr1;
 657    uint64_t dawrx1;
 658    /* Version 2 ends here */
 659};
 660
 661/* Latest version of hv_guest_state structure */
 662#define HV_GUEST_STATE_VERSION  2
 663
 664/* Linux 64-bit powerpc pt_regs struct, used by nested HV */
 665struct kvmppc_pt_regs {
 666    uint64_t gpr[32];
 667    uint64_t nip;
 668    uint64_t msr;
 669    uint64_t orig_gpr3;    /* Used for restarting system calls */
 670    uint64_t ctr;
 671    uint64_t link;
 672    uint64_t xer;
 673    uint64_t ccr;
 674    uint64_t softe;        /* Soft enabled/disabled */
 675    uint64_t trap;         /* Reason for being here */
 676    uint64_t dar;          /* Fault registers */
 677    uint64_t dsisr;        /* on 4xx/Book-E used for ESR */
 678    uint64_t result;       /* Result of a system call */
 679};
 680
 681typedef struct SpaprDeviceTreeUpdateHeader {
 682    uint32_t version_id;
 683} SpaprDeviceTreeUpdateHeader;
 684
 685#define hcall_dprintf(fmt, ...) \
 686    do { \
 687        qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
 688    } while (0)
 689
 690typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
 691                                       target_ulong opcode,
 692                                       target_ulong *args);
 693
 694void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
 695target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
 696                             target_ulong *args);
 697
 698void spapr_exit_nested(PowerPCCPU *cpu, int excp);
 699
 700target_ulong softmmu_resize_hpt_prepare(PowerPCCPU *cpu, SpaprMachineState *spapr,
 701                                         target_ulong shift);
 702target_ulong softmmu_resize_hpt_commit(PowerPCCPU *cpu, SpaprMachineState *spapr,
 703                                        target_ulong flags, target_ulong shift);
 704bool is_ram_address(SpaprMachineState *spapr, hwaddr addr);
 705void push_sregs_to_kvm_pr(SpaprMachineState *spapr);
 706
 707/* Virtual Processor Area structure constants */
 708#define VPA_MIN_SIZE           640
 709#define VPA_SIZE_OFFSET        0x4
 710#define VPA_SHARED_PROC_OFFSET 0x9
 711#define VPA_SHARED_PROC_VAL    0x2
 712#define VPA_DISPATCH_COUNTER   0x100
 713
 714/* ibm,set-eeh-option */
 715#define RTAS_EEH_DISABLE                 0
 716#define RTAS_EEH_ENABLE                  1
 717#define RTAS_EEH_THAW_IO                 2
 718#define RTAS_EEH_THAW_DMA                3
 719
 720/* ibm,get-config-addr-info2 */
 721#define RTAS_GET_PE_ADDR                 0
 722#define RTAS_GET_PE_MODE                 1
 723#define RTAS_PE_MODE_NONE                0
 724#define RTAS_PE_MODE_NOT_SHARED          1
 725#define RTAS_PE_MODE_SHARED              2
 726
 727/* ibm,read-slot-reset-state2 */
 728#define RTAS_EEH_PE_STATE_NORMAL         0
 729#define RTAS_EEH_PE_STATE_RESET          1
 730#define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
 731#define RTAS_EEH_PE_STATE_STOPPED_DMA    4
 732#define RTAS_EEH_PE_STATE_UNAVAIL        5
 733#define RTAS_EEH_NOT_SUPPORT             0
 734#define RTAS_EEH_SUPPORT                 1
 735#define RTAS_EEH_PE_UNAVAIL_INFO         1000
 736#define RTAS_EEH_PE_RECOVER_INFO         0
 737
 738/* ibm,set-slot-reset */
 739#define RTAS_SLOT_RESET_DEACTIVATE       0
 740#define RTAS_SLOT_RESET_HOT              1
 741#define RTAS_SLOT_RESET_FUNDAMENTAL      3
 742
 743/* ibm,slot-error-detail */
 744#define RTAS_SLOT_TEMP_ERR_LOG           1
 745#define RTAS_SLOT_PERM_ERR_LOG           2
 746
 747/* RTAS return codes */
 748#define RTAS_OUT_SUCCESS                        0
 749#define RTAS_OUT_NO_ERRORS_FOUND                1
 750#define RTAS_OUT_HW_ERROR                       -1
 751#define RTAS_OUT_BUSY                           -2
 752#define RTAS_OUT_PARAM_ERROR                    -3
 753#define RTAS_OUT_NOT_SUPPORTED                  -3
 754#define RTAS_OUT_NO_SUCH_INDICATOR              -3
 755#define RTAS_OUT_NOT_AUTHORIZED                 -9002
 756#define RTAS_OUT_SYSPARM_PARAM_ERROR            -9999
 757
 758/* DDW pagesize mask values from ibm,query-pe-dma-window */
 759#define RTAS_DDW_PGSIZE_4K       0x01
 760#define RTAS_DDW_PGSIZE_64K      0x02
 761#define RTAS_DDW_PGSIZE_16M      0x04
 762#define RTAS_DDW_PGSIZE_32M      0x08
 763#define RTAS_DDW_PGSIZE_64M      0x10
 764#define RTAS_DDW_PGSIZE_128M     0x20
 765#define RTAS_DDW_PGSIZE_256M     0x40
 766#define RTAS_DDW_PGSIZE_16G      0x80
 767#define RTAS_DDW_PGSIZE_2M       0x100
 768
 769/* RTAS tokens */
 770#define RTAS_TOKEN_BASE      0x2000
 771
 772#define RTAS_DISPLAY_CHARACTER                  (RTAS_TOKEN_BASE + 0x00)
 773#define RTAS_GET_TIME_OF_DAY                    (RTAS_TOKEN_BASE + 0x01)
 774#define RTAS_SET_TIME_OF_DAY                    (RTAS_TOKEN_BASE + 0x02)
 775#define RTAS_POWER_OFF                          (RTAS_TOKEN_BASE + 0x03)
 776#define RTAS_SYSTEM_REBOOT                      (RTAS_TOKEN_BASE + 0x04)
 777#define RTAS_QUERY_CPU_STOPPED_STATE            (RTAS_TOKEN_BASE + 0x05)
 778#define RTAS_START_CPU                          (RTAS_TOKEN_BASE + 0x06)
 779#define RTAS_STOP_SELF                          (RTAS_TOKEN_BASE + 0x07)
 780#define RTAS_IBM_GET_SYSTEM_PARAMETER           (RTAS_TOKEN_BASE + 0x08)
 781#define RTAS_IBM_SET_SYSTEM_PARAMETER           (RTAS_TOKEN_BASE + 0x09)
 782#define RTAS_IBM_SET_XIVE                       (RTAS_TOKEN_BASE + 0x0A)
 783#define RTAS_IBM_GET_XIVE                       (RTAS_TOKEN_BASE + 0x0B)
 784#define RTAS_IBM_INT_OFF                        (RTAS_TOKEN_BASE + 0x0C)
 785#define RTAS_IBM_INT_ON                         (RTAS_TOKEN_BASE + 0x0D)
 786#define RTAS_CHECK_EXCEPTION                    (RTAS_TOKEN_BASE + 0x0E)
 787#define RTAS_EVENT_SCAN                         (RTAS_TOKEN_BASE + 0x0F)
 788#define RTAS_IBM_SET_TCE_BYPASS                 (RTAS_TOKEN_BASE + 0x10)
 789#define RTAS_QUIESCE                            (RTAS_TOKEN_BASE + 0x11)
 790#define RTAS_NVRAM_FETCH                        (RTAS_TOKEN_BASE + 0x12)
 791#define RTAS_NVRAM_STORE                        (RTAS_TOKEN_BASE + 0x13)
 792#define RTAS_READ_PCI_CONFIG                    (RTAS_TOKEN_BASE + 0x14)
 793#define RTAS_WRITE_PCI_CONFIG                   (RTAS_TOKEN_BASE + 0x15)
 794#define RTAS_IBM_READ_PCI_CONFIG                (RTAS_TOKEN_BASE + 0x16)
 795#define RTAS_IBM_WRITE_PCI_CONFIG               (RTAS_TOKEN_BASE + 0x17)
 796#define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER  (RTAS_TOKEN_BASE + 0x18)
 797#define RTAS_IBM_CHANGE_MSI                     (RTAS_TOKEN_BASE + 0x19)
 798#define RTAS_SET_INDICATOR                      (RTAS_TOKEN_BASE + 0x1A)
 799#define RTAS_SET_POWER_LEVEL                    (RTAS_TOKEN_BASE + 0x1B)
 800#define RTAS_GET_POWER_LEVEL                    (RTAS_TOKEN_BASE + 0x1C)
 801#define RTAS_GET_SENSOR_STATE                   (RTAS_TOKEN_BASE + 0x1D)
 802#define RTAS_IBM_CONFIGURE_CONNECTOR            (RTAS_TOKEN_BASE + 0x1E)
 803#define RTAS_IBM_OS_TERM                        (RTAS_TOKEN_BASE + 0x1F)
 804#define RTAS_IBM_SET_EEH_OPTION                 (RTAS_TOKEN_BASE + 0x20)
 805#define RTAS_IBM_GET_CONFIG_ADDR_INFO2          (RTAS_TOKEN_BASE + 0x21)
 806#define RTAS_IBM_READ_SLOT_RESET_STATE2         (RTAS_TOKEN_BASE + 0x22)
 807#define RTAS_IBM_SET_SLOT_RESET                 (RTAS_TOKEN_BASE + 0x23)
 808#define RTAS_IBM_CONFIGURE_PE                   (RTAS_TOKEN_BASE + 0x24)
 809#define RTAS_IBM_SLOT_ERROR_DETAIL              (RTAS_TOKEN_BASE + 0x25)
 810#define RTAS_IBM_QUERY_PE_DMA_WINDOW            (RTAS_TOKEN_BASE + 0x26)
 811#define RTAS_IBM_CREATE_PE_DMA_WINDOW           (RTAS_TOKEN_BASE + 0x27)
 812#define RTAS_IBM_REMOVE_PE_DMA_WINDOW           (RTAS_TOKEN_BASE + 0x28)
 813#define RTAS_IBM_RESET_PE_DMA_WINDOW            (RTAS_TOKEN_BASE + 0x29)
 814#define RTAS_IBM_SUSPEND_ME                     (RTAS_TOKEN_BASE + 0x2A)
 815#define RTAS_IBM_NMI_REGISTER                   (RTAS_TOKEN_BASE + 0x2B)
 816#define RTAS_IBM_NMI_INTERLOCK                  (RTAS_TOKEN_BASE + 0x2C)
 817
 818#define RTAS_TOKEN_MAX                          (RTAS_TOKEN_BASE + 0x2D)
 819
 820/* RTAS ibm,get-system-parameter token values */
 821#define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS      20
 822#define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE        42
 823#define RTAS_SYSPARM_UUID                        48
 824
 825/* RTAS indicator/sensor types
 826 *
 827 * as defined by PAPR+ 2.7 7.3.5.4, Table 41
 828 *
 829 * NOTE: currently only DR-related sensors are implemented here
 830 */
 831#define RTAS_SENSOR_TYPE_ISOLATION_STATE        9001
 832#define RTAS_SENSOR_TYPE_DR                     9002
 833#define RTAS_SENSOR_TYPE_ALLOCATION_STATE       9003
 834#define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
 835
 836/* Possible values for the platform-processor-diagnostics-run-mode parameter
 837 * of the RTAS ibm,get-system-parameter call.
 838 */
 839#define DIAGNOSTICS_RUN_MODE_DISABLED  0
 840#define DIAGNOSTICS_RUN_MODE_STAGGERED 1
 841#define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
 842#define DIAGNOSTICS_RUN_MODE_PERIODIC  3
 843
 844static inline uint64_t ppc64_phys_to_real(uint64_t addr)
 845{
 846    return addr & ~0xF000000000000000ULL;
 847}
 848
 849static inline uint32_t rtas_ld(target_ulong phys, int n)
 850{
 851    return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
 852}
 853
 854static inline uint64_t rtas_ldq(target_ulong phys, int n)
 855{
 856    return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
 857}
 858
 859static inline void rtas_st(target_ulong phys, int n, uint32_t val)
 860{
 861    stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
 862}
 863
 864typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
 865                              uint32_t token,
 866                              uint32_t nargs, target_ulong args,
 867                              uint32_t nret, target_ulong rets);
 868void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
 869target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm,
 870                             uint32_t token, uint32_t nargs, target_ulong args,
 871                             uint32_t nret, target_ulong rets);
 872void spapr_dt_rtas_tokens(void *fdt, int rtas);
 873void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr);
 874
 875#define SPAPR_TCE_PAGE_SHIFT   12
 876#define SPAPR_TCE_PAGE_SIZE    (1ULL << SPAPR_TCE_PAGE_SHIFT)
 877#define SPAPR_TCE_PAGE_MASK    (SPAPR_TCE_PAGE_SIZE - 1)
 878
 879#define SPAPR_VIO_BASE_LIOBN    0x00000000
 880#define SPAPR_VIO_LIOBN(reg)    (0x00000000 | (reg))
 881#define SPAPR_PCI_LIOBN(phb_index, window_num) \
 882    (0x80000000 | ((phb_index) << 8) | (window_num))
 883#define SPAPR_IS_PCI_LIOBN(liobn)   (!!((liobn) & 0x80000000))
 884#define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
 885
 886#define RTAS_MIN_SIZE           20 /* hv_rtas_size in SLOF */
 887#define RTAS_ERROR_LOG_MAX      2048
 888
 889/* Offset from rtas-base where error log is placed */
 890#define RTAS_ERROR_LOG_OFFSET       0x30
 891
 892#define RTAS_EVENT_SCAN_RATE    1
 893
 894/* This helper should be used to encode interrupt specifiers when the related
 895 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie,
 896 * VIO devices, RTAS event sources and PHBs).
 897 */
 898static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi)
 899{
 900    intspec[0] = cpu_to_be32(irq);
 901    intspec[1] = is_lsi ? cpu_to_be32(1) : 0;
 902}
 903
 904
 905#define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
 906OBJECT_DECLARE_SIMPLE_TYPE(SpaprTceTable, SPAPR_TCE_TABLE)
 907
 908#define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region"
 909DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, SPAPR_IOMMU_MEMORY_REGION,
 910                         TYPE_SPAPR_IOMMU_MEMORY_REGION)
 911
 912struct SpaprTceTable {
 913    DeviceState parent;
 914    uint32_t liobn;
 915    uint32_t nb_table;
 916    uint64_t bus_offset;
 917    uint32_t page_shift;
 918    uint64_t *table;
 919    uint32_t mig_nb_table;
 920    uint64_t *mig_table;
 921    bool bypass;
 922    bool need_vfio;
 923    bool skipping_replay;
 924    bool def_win;
 925    int fd;
 926    MemoryRegion root;
 927    IOMMUMemoryRegion iommu;
 928    struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */
 929    QLIST_ENTRY(SpaprTceTable) list;
 930};
 931
 932SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn);
 933
 934struct SpaprEventLogEntry {
 935    uint32_t summary;
 936    uint32_t extended_length;
 937    void *extended_log;
 938    QTAILQ_ENTRY(SpaprEventLogEntry) next;
 939};
 940
 941void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space);
 942void spapr_events_init(SpaprMachineState *sm);
 943void spapr_dt_events(SpaprMachineState *sm, void *fdt);
 944void close_htab_fd(SpaprMachineState *spapr);
 945void spapr_setup_hpt(SpaprMachineState *spapr);
 946void spapr_free_hpt(SpaprMachineState *spapr);
 947void spapr_check_mmu_mode(bool guest_radix);
 948SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
 949void spapr_tce_table_enable(SpaprTceTable *tcet,
 950                            uint32_t page_shift, uint64_t bus_offset,
 951                            uint32_t nb_table);
 952void spapr_tce_table_disable(SpaprTceTable *tcet);
 953void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio);
 954
 955MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet);
 956int spapr_dma_dt(void *fdt, int node_off, const char *propname,
 957                 uint32_t liobn, uint64_t window, uint32_t size);
 958int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
 959                      SpaprTceTable *tcet);
 960void spapr_pci_switch_vga(SpaprMachineState *spapr, bool big_endian);
 961void spapr_hotplug_req_add_by_index(SpaprDrc *drc);
 962void spapr_hotplug_req_remove_by_index(SpaprDrc *drc);
 963void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type,
 964                                       uint32_t count);
 965void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type,
 966                                          uint32_t count);
 967void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type,
 968                                            uint32_t count, uint32_t index);
 969void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type,
 970                                               uint32_t count, uint32_t index);
 971int spapr_hpt_shift_for_ramsize(uint64_t ramsize);
 972int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp);
 973void spapr_clear_pending_events(SpaprMachineState *spapr);
 974void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr);
 975void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev);
 976int spapr_max_server_number(SpaprMachineState *spapr);
 977void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
 978                      uint64_t pte0, uint64_t pte1);
 979void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered);
 980
 981/* DRC callbacks. */
 982void spapr_core_release(DeviceState *dev);
 983int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
 984                           void *fdt, int *fdt_start_offset, Error **errp);
 985void spapr_lmb_release(DeviceState *dev);
 986int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
 987                          void *fdt, int *fdt_start_offset, Error **errp);
 988void spapr_phb_release(DeviceState *dev);
 989int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
 990                          void *fdt, int *fdt_start_offset, Error **errp);
 991
 992void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns);
 993int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset);
 994
 995#define TYPE_SPAPR_RNG "spapr-rng"
 996
 997#define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */
 998
 999/*
1000 * This defines the maximum number of DIMM slots we can have for sPAPR

1001 * guest. This is not defined by sPAPR but we are defining it to 32 slots
1002 * based on default number of slots provided by PowerPC kernel.
1003 */
1004#define SPAPR_MAX_RAM_SLOTS     32
1005
1006/* 1GB alignment for hotplug memory region */
1007#define SPAPR_DEVICE_MEM_ALIGN (1 * GiB)
1008
1009/*
1010 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory
1011 * property under ibm,dynamic-reconfiguration-memory node.
1012 */
1013#define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
1014
1015/*
1016 * Defines for flag value in ibm,dynamic-memory property under
1017 * ibm,dynamic-reconfiguration-memory node.
1018 */
1019#define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
1020#define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
1021#define SPAPR_LMB_FLAGS_RESERVED 0x00000080
1022#define SPAPR_LMB_FLAGS_HOTREMOVABLE 0x00000100
1023
1024void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg);
1025
1026#define HTAB_SIZE(spapr)        (1ULL << ((spapr)->htab_shift))
1027
1028int spapr_get_vcpu_id(PowerPCCPU *cpu);
1029bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp);
1030PowerPCCPU *spapr_find_cpu(int vcpu_id);
1031
1032int spapr_caps_pre_load(void *opaque);
1033int spapr_caps_pre_save(void *opaque);
1034
1035/*
1036 * Handling of optional capabilities
1037 */
1038extern const VMStateDescription vmstate_spapr_cap_htm;
1039extern const VMStateDescription vmstate_spapr_cap_vsx;
1040extern const VMStateDescription vmstate_spapr_cap_dfp;
1041extern const VMStateDescription vmstate_spapr_cap_cfpc;
1042extern const VMStateDescription vmstate_spapr_cap_sbbc;
1043extern const VMStateDescription vmstate_spapr_cap_ibs;
1044extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize;
1045extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv;
1046extern const VMStateDescription vmstate_spapr_cap_large_decr;
1047extern const VMStateDescription vmstate_spapr_cap_ccf_assist;
1048extern const VMStateDescription vmstate_spapr_cap_fwnmi;
1049extern const VMStateDescription vmstate_spapr_cap_rpt_invalidate;
1050extern const VMStateDescription vmstate_spapr_wdt;
1051
1052static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap)
1053{
1054    return spapr->eff.caps[cap];
1055}
1056
1057void spapr_caps_init(SpaprMachineState *spapr);
1058void spapr_caps_apply(SpaprMachineState *spapr);
1059void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu);
1060void spapr_caps_add_properties(SpaprMachineClass *smc);
1061int spapr_caps_post_migration(SpaprMachineState *spapr);
1062
1063bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize,
1064                          Error **errp);
1065/*
1066 * XIVE definitions
1067 */
1068#define SPAPR_OV5_XIVE_LEGACY   0x0
1069#define SPAPR_OV5_XIVE_EXPLOIT  0x40
1070#define SPAPR_OV5_XIVE_BOTH     0x80 /* Only to advertise on the platform */
1071
1072void spapr_set_all_lpcrs(target_ulong value, target_ulong mask);
1073hwaddr spapr_get_rtas_addr(void);
1074bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr);
1075
1076void spapr_vof_reset(SpaprMachineState *spapr, void *fdt, Error **errp);
1077void spapr_vof_quiesce(MachineState *ms);
1078bool spapr_vof_setprop(MachineState *ms, const char *path, const char *propname,
1079                       void *val, int vallen);
1080target_ulong spapr_h_vof_client(PowerPCCPU *cpu, SpaprMachineState *spapr,
1081                                target_ulong opcode, target_ulong *args);
1082target_ulong spapr_vof_client_architecture_support(MachineState *ms,
1083                                                   CPUState *cs,
1084                                                   target_ulong ovec_addr);
1085void spapr_vof_client_dt_finalize(SpaprMachineState *spapr, void *fdt);
1086
1087/* H_WATCHDOG */
1088void spapr_watchdog_init(SpaprMachineState *spapr);
1089
1090#endif /* HW_SPAPR_H */
1091