LXR qemu/include/hw/ppc/spapr

   1#ifndef HW_SPAPR_VIO_H
   2#define HW_SPAPR_VIO_H
   3
   4/*
   5 * QEMU sPAPR VIO bus definitions
   6 *
   7 * Copyright (c) 2010 David Gibson, IBM Corporation <david@gibson.dropbear.id.au>
   8 * Based on the s390 virtio bus definitions:
   9 * Copyright (c) 2009 Alexander Graf <agraf@suse.de>
  10 *
  11 * This library is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU Lesser General Public
  13 * License as published by the Free Software Foundation; either
  14 * version 2.1 of the License, or (at your option) any later version.
  15 *
  16 * This library is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19 * Lesser General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU Lesser General Public
  22 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  23 */
  24
  25#include "hw/ppc/spapr.h"
  26#include "sysemu/dma.h"
  27#include "hw/irq.h"
  28#include "qom/object.h"
  29
  30#define TYPE_VIO_SPAPR_DEVICE "vio-spapr-device"
  31OBJECT_DECLARE_TYPE(SpaprVioDevice, SpaprVioDeviceClass,
  32                    VIO_SPAPR_DEVICE)
  33
  34#define TYPE_SPAPR_VIO_BUS "spapr-vio-bus"
  35OBJECT_DECLARE_SIMPLE_TYPE(SpaprVioBus, SPAPR_VIO_BUS)
  36
  37#define TYPE_SPAPR_VIO_BRIDGE "spapr-vio-bridge"
  38
  39typedef struct SpaprVioCrq {
  40    uint64_t qladdr;
  41    uint32_t qsize;
  42    uint32_t qnext;
  43    int(*SendFunc)(struct SpaprVioDevice *vdev, uint8_t *crq);
  44} SpaprVioCrq;
  45
  46
  47struct SpaprVioDeviceClass {
  48    DeviceClass parent_class;
  49
  50    const char *dt_name, *dt_type, *dt_compatible;
  51    target_ulong signal_mask;
  52    uint32_t rtce_window_size;
  53    void (*realize)(SpaprVioDevice *dev, Error **errp);
  54    void (*reset)(SpaprVioDevice *dev);
  55    int (*devnode)(SpaprVioDevice *dev, void *fdt, int node_off);
  56    const char *(*get_dt_compatible)(SpaprVioDevice *dev);
  57};
  58
  59struct SpaprVioDevice {
  60    DeviceState qdev;
  61    uint32_t reg;
  62    uint32_t irq;
  63    uint64_t signal_state;
  64    SpaprVioCrq crq;
  65    AddressSpace as;
  66    MemoryRegion mrroot;
  67    MemoryRegion mrbypass;
  68    SpaprTceTable *tcet;
  69};
  70
  71#define DEFINE_SPAPR_PROPERTIES(type, field)           \
  72        DEFINE_PROP_UINT32("reg", type, field.reg, -1)
  73
  74struct SpaprVioBus {
  75    BusState bus;
  76    uint32_t next_reg;
  77};
  78
  79SpaprVioBus *spapr_vio_bus_init(void);
  80SpaprVioDevice *spapr_vio_find_by_reg(SpaprVioBus *bus, uint32_t reg);
  81void spapr_dt_vdevice(SpaprVioBus *bus, void *fdt);
  82gchar *spapr_vio_stdout_path(SpaprVioBus *bus);
  83
  84static inline void spapr_vio_irq_pulse(SpaprVioDevice *dev)
  85{
  86    SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
  87
  88    qemu_irq_pulse(spapr_qirq(spapr, dev->irq));
  89}
  90
  91static inline bool spapr_vio_dma_valid(SpaprVioDevice *dev, uint64_t taddr,
  92                                       uint32_t size, DMADirection dir)
  93{
  94    return dma_memory_valid(&dev->as, taddr, size, dir, MEMTXATTRS_UNSPECIFIED);
  95}
  96
  97static inline int spapr_vio_dma_read(SpaprVioDevice *dev, uint64_t taddr,
  98                                     void *buf, uint32_t size)
  99{
 100    return (dma_memory_read(&dev->as, taddr,
 101                            buf, size, MEMTXATTRS_UNSPECIFIED) != 0) ?
 102        H_DEST_PARM : H_SUCCESS;
 103}
 104
 105static inline int spapr_vio_dma_write(SpaprVioDevice *dev, uint64_t taddr,
 106                                      const void *buf, uint32_t size)
 107{
 108    return (dma_memory_write(&dev->as, taddr,
 109                             buf, size, MEMTXATTRS_UNSPECIFIED) != 0) ?
 110        H_DEST_PARM : H_SUCCESS;
 111}
 112
 113static inline int spapr_vio_dma_set(SpaprVioDevice *dev, uint64_t taddr,
 114                                    uint8_t c, uint32_t size)
 115{
 116    return (dma_memory_set(&dev->as, taddr,
 117                           c, size, MEMTXATTRS_UNSPECIFIED) != 0) ?
 118        H_DEST_PARM : H_SUCCESS;
 119}
 120
 121#define vio_stb(_dev, _addr, _val) \
 122        (stb_dma(&(_dev)->as, (_addr), (_val), MEMTXATTRS_UNSPECIFIED))
 123#define vio_sth(_dev, _addr, _val) \
 124        (stw_be_dma(&(_dev)->as, (_addr), (_val), MEMTXATTRS_UNSPECIFIED))
 125#define vio_stl(_dev, _addr, _val) \
 126        (stl_be_dma(&(_dev)->as, (_addr), (_val), MEMTXATTRS_UNSPECIFIED))
 127#define vio_stq(_dev, _addr, _val) \
 128        (stq_be_dma(&(_dev)->as, (_addr), (_val), MEMTXATTRS_UNSPECIFIED))
 129#define vio_ldq(_dev, _addr) \
 130        ({ \
 131            uint64_t _val; \
 132            ldq_be_dma(&(_dev)->as, (_addr), &_val, MEMTXATTRS_UNSPECIFIED); \
 133            _val; \
 134        })
 135
 136int spapr_vio_send_crq(SpaprVioDevice *dev, uint8_t *crq);
 137
 138SpaprVioDevice *vty_lookup(SpaprMachineState *spapr, target_ulong reg);
 139void vty_putchars(SpaprVioDevice *sdev, uint8_t *buf, int len);
 140void spapr_vty_create(SpaprVioBus *bus, Chardev *chardev);
 141void spapr_vlan_create(SpaprVioBus *bus, NICInfo *nd);
 142void spapr_vscsi_create(SpaprVioBus *bus);
 143
 144SpaprVioDevice *spapr_vty_get_default(SpaprVioBus *bus);
 145
 146extern const VMStateDescription vmstate_spapr_vio;
 147
 148#define VMSTATE_SPAPR_VIO(_f, _s) \
 149    VMSTATE_STRUCT(_f, _s, 0, vmstate_spapr_vio, SpaprVioDevice)
 150
 151void spapr_vio_set_bypass(SpaprVioDevice *dev, bool bypass);
 152
 153#endif /* HW_SPAPR_VIO_H */
 154