1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46#ifndef __PVRDMA_VERBS_H__
47#define __PVRDMA_VERBS_H__
48
49#include "standard-headers/linux/types.h"
50
51union pvrdma_gid {
52 uint8_t raw[16];
53 struct {
54 uint64_t subnet_prefix;
55 uint64_t interface_id;
56 } global;
57};
58
59enum pvrdma_link_layer {
60 PVRDMA_LINK_LAYER_UNSPECIFIED,
61 PVRDMA_LINK_LAYER_INFINIBAND,
62 PVRDMA_LINK_LAYER_ETHERNET,
63};
64
65enum pvrdma_mtu {
66 PVRDMA_MTU_256 = 1,
67 PVRDMA_MTU_512 = 2,
68 PVRDMA_MTU_1024 = 3,
69 PVRDMA_MTU_2048 = 4,
70 PVRDMA_MTU_4096 = 5,
71};
72
73enum pvrdma_port_state {
74 PVRDMA_PORT_NOP = 0,
75 PVRDMA_PORT_DOWN = 1,
76 PVRDMA_PORT_INIT = 2,
77 PVRDMA_PORT_ARMED = 3,
78 PVRDMA_PORT_ACTIVE = 4,
79 PVRDMA_PORT_ACTIVE_DEFER = 5,
80};
81
82enum pvrdma_port_cap_flags {
83 PVRDMA_PORT_SM = 1 << 1,
84 PVRDMA_PORT_NOTICE_SUP = 1 << 2,
85 PVRDMA_PORT_TRAP_SUP = 1 << 3,
86 PVRDMA_PORT_OPT_IPD_SUP = 1 << 4,
87 PVRDMA_PORT_AUTO_MIGR_SUP = 1 << 5,
88 PVRDMA_PORT_SL_MAP_SUP = 1 << 6,
89 PVRDMA_PORT_MKEY_NVRAM = 1 << 7,
90 PVRDMA_PORT_PKEY_NVRAM = 1 << 8,
91 PVRDMA_PORT_LED_INFO_SUP = 1 << 9,
92 PVRDMA_PORT_SM_DISABLED = 1 << 10,
93 PVRDMA_PORT_SYS_IMAGE_GUID_SUP = 1 << 11,
94 PVRDMA_PORT_PKEY_SW_EXT_PORT_TRAP_SUP = 1 << 12,
95 PVRDMA_PORT_EXTENDED_SPEEDS_SUP = 1 << 14,
96 PVRDMA_PORT_CM_SUP = 1 << 16,
97 PVRDMA_PORT_SNMP_TUNNEL_SUP = 1 << 17,
98 PVRDMA_PORT_REINIT_SUP = 1 << 18,
99 PVRDMA_PORT_DEVICE_MGMT_SUP = 1 << 19,
100 PVRDMA_PORT_VENDOR_CLASS_SUP = 1 << 20,
101 PVRDMA_PORT_DR_NOTICE_SUP = 1 << 21,
102 PVRDMA_PORT_CAP_MASK_NOTICE_SUP = 1 << 22,
103 PVRDMA_PORT_BOOT_MGMT_SUP = 1 << 23,
104 PVRDMA_PORT_LINK_LATENCY_SUP = 1 << 24,
105 PVRDMA_PORT_CLIENT_REG_SUP = 1 << 25,
106 PVRDMA_PORT_IP_BASED_GIDS = 1 << 26,
107 PVRDMA_PORT_CAP_FLAGS_MAX = PVRDMA_PORT_IP_BASED_GIDS,
108};
109
110enum pvrdma_port_width {
111 PVRDMA_WIDTH_1X = 1,
112 PVRDMA_WIDTH_4X = 2,
113 PVRDMA_WIDTH_8X = 4,
114 PVRDMA_WIDTH_12X = 8,
115};
116
117enum pvrdma_port_speed {
118 PVRDMA_SPEED_SDR = 1,
119 PVRDMA_SPEED_DDR = 2,
120 PVRDMA_SPEED_QDR = 4,
121 PVRDMA_SPEED_FDR10 = 8,
122 PVRDMA_SPEED_FDR = 16,
123 PVRDMA_SPEED_EDR = 32,
124};
125
126struct pvrdma_port_attr {
127 enum pvrdma_port_state state;
128 enum pvrdma_mtu max_mtu;
129 enum pvrdma_mtu active_mtu;
130 uint32_t gid_tbl_len;
131 uint32_t port_cap_flags;
132 uint32_t max_msg_sz;
133 uint32_t bad_pkey_cntr;
134 uint32_t qkey_viol_cntr;
135 uint16_t pkey_tbl_len;
136 uint16_t lid;
137 uint16_t sm_lid;
138 uint8_t lmc;
139 uint8_t max_vl_num;
140 uint8_t sm_sl;
141 uint8_t subnet_timeout;
142 uint8_t init_type_reply;
143 uint8_t active_width;
144 uint8_t active_speed;
145 uint8_t phys_state;
146 uint8_t reserved[2];
147};
148
149struct pvrdma_global_route {
150 union pvrdma_gid dgid;
151 uint32_t flow_label;
152 uint8_t sgid_index;
153 uint8_t hop_limit;
154 uint8_t traffic_class;
155 uint8_t reserved;
156};
157
158struct pvrdma_grh {
159 uint32_t version_tclass_flow;
160 uint16_t paylen;
161 uint8_t next_hdr;
162 uint8_t hop_limit;
163 union pvrdma_gid sgid;
164 union pvrdma_gid dgid;
165};
166
167enum pvrdma_ah_flags {
168 PVRDMA_AH_GRH = 1,
169};
170
171enum pvrdma_rate {
172 PVRDMA_RATE_PORT_CURRENT = 0,
173 PVRDMA_RATE_2_5_GBPS = 2,
174 PVRDMA_RATE_5_GBPS = 5,
175 PVRDMA_RATE_10_GBPS = 3,
176 PVRDMA_RATE_20_GBPS = 6,
177 PVRDMA_RATE_30_GBPS = 4,
178 PVRDMA_RATE_40_GBPS = 7,
179 PVRDMA_RATE_60_GBPS = 8,
180 PVRDMA_RATE_80_GBPS = 9,
181 PVRDMA_RATE_120_GBPS = 10,
182 PVRDMA_RATE_14_GBPS = 11,
183 PVRDMA_RATE_56_GBPS = 12,
184 PVRDMA_RATE_112_GBPS = 13,
185 PVRDMA_RATE_168_GBPS = 14,
186 PVRDMA_RATE_25_GBPS = 15,
187 PVRDMA_RATE_100_GBPS = 16,
188 PVRDMA_RATE_200_GBPS = 17,
189 PVRDMA_RATE_300_GBPS = 18,
190};
191
192struct pvrdma_ah_attr {
193 struct pvrdma_global_route grh;
194 uint16_t dlid;
195 uint16_t vlan_id;
196 uint8_t sl;
197 uint8_t src_path_bits;
198 uint8_t static_rate;
199 uint8_t ah_flags;
200 uint8_t port_num;
201 uint8_t dmac[6];
202 uint8_t reserved;
203};
204
205enum pvrdma_cq_notify_flags {
206 PVRDMA_CQ_SOLICITED = 1 << 0,
207 PVRDMA_CQ_NEXT_COMP = 1 << 1,
208 PVRDMA_CQ_SOLICITED_MASK = PVRDMA_CQ_SOLICITED |
209 PVRDMA_CQ_NEXT_COMP,
210 PVRDMA_CQ_REPORT_MISSED_EVENTS = 1 << 2,
211};
212
213struct pvrdma_qp_cap {
214 uint32_t max_send_wr;
215 uint32_t max_recv_wr;
216 uint32_t max_send_sge;
217 uint32_t max_recv_sge;
218 uint32_t max_inline_data;
219 uint32_t reserved;
220};
221
222enum pvrdma_sig_type {
223 PVRDMA_SIGNAL_ALL_WR,
224 PVRDMA_SIGNAL_REQ_WR,
225};
226
227enum pvrdma_qp_type {
228 PVRDMA_QPT_SMI,
229 PVRDMA_QPT_GSI,
230 PVRDMA_QPT_RC,
231 PVRDMA_QPT_UC,
232 PVRDMA_QPT_UD,
233 PVRDMA_QPT_RAW_IPV6,
234 PVRDMA_QPT_RAW_ETHERTYPE,
235 PVRDMA_QPT_RAW_PACKET = 8,
236 PVRDMA_QPT_XRC_INI = 9,
237 PVRDMA_QPT_XRC_TGT,
238 PVRDMA_QPT_MAX,
239};
240
241enum pvrdma_qp_create_flags {
242 PVRDMA_QP_CREATE_IPOPVRDMA_UD_LSO = 1 << 0,
243 PVRDMA_QP_CREATE_BLOCK_MULTICAST_LOOPBACK = 1 << 1,
244};
245
246enum pvrdma_qp_attr_mask {
247 PVRDMA_QP_STATE = 1 << 0,
248 PVRDMA_QP_CUR_STATE = 1 << 1,
249 PVRDMA_QP_EN_SQD_ASYNC_NOTIFY = 1 << 2,
250 PVRDMA_QP_ACCESS_FLAGS = 1 << 3,
251 PVRDMA_QP_PKEY_INDEX = 1 << 4,
252 PVRDMA_QP_PORT = 1 << 5,
253 PVRDMA_QP_QKEY = 1 << 6,
254 PVRDMA_QP_AV = 1 << 7,
255 PVRDMA_QP_PATH_MTU = 1 << 8,
256 PVRDMA_QP_TIMEOUT = 1 << 9,
257 PVRDMA_QP_RETRY_CNT = 1 << 10,
258 PVRDMA_QP_RNR_RETRY = 1 << 11,
259 PVRDMA_QP_RQ_PSN = 1 << 12,
260 PVRDMA_QP_MAX_QP_RD_ATOMIC = 1 << 13,
261 PVRDMA_QP_ALT_PATH = 1 << 14,
262 PVRDMA_QP_MIN_RNR_TIMER = 1 << 15,
263 PVRDMA_QP_SQ_PSN = 1 << 16,
264 PVRDMA_QP_MAX_DEST_RD_ATOMIC = 1 << 17,
265 PVRDMA_QP_PATH_MIG_STATE = 1 << 18,
266 PVRDMA_QP_CAP = 1 << 19,
267 PVRDMA_QP_DEST_QPN = 1 << 20,
268 PVRDMA_QP_ATTR_MASK_MAX = PVRDMA_QP_DEST_QPN,
269};
270
271enum pvrdma_qp_state {
272 PVRDMA_QPS_RESET,
273 PVRDMA_QPS_INIT,
274 PVRDMA_QPS_RTR,
275 PVRDMA_QPS_RTS,
276 PVRDMA_QPS_SQD,
277 PVRDMA_QPS_SQE,
278 PVRDMA_QPS_ERR,
279};
280
281enum pvrdma_mig_state {
282 PVRDMA_MIG_MIGRATED,
283 PVRDMA_MIG_REARM,
284 PVRDMA_MIG_ARMED,
285};
286
287enum pvrdma_mw_type {
288 PVRDMA_MW_TYPE_1 = 1,
289 PVRDMA_MW_TYPE_2 = 2,
290};
291
292struct pvrdma_srq_attr {
293 uint32_t max_wr;
294 uint32_t max_sge;
295 uint32_t srq_limit;
296 uint32_t reserved;
297};
298
299struct pvrdma_qp_attr {
300 enum pvrdma_qp_state qp_state;
301 enum pvrdma_qp_state cur_qp_state;
302 enum pvrdma_mtu path_mtu;
303 enum pvrdma_mig_state path_mig_state;
304 uint32_t qkey;
305 uint32_t rq_psn;
306 uint32_t sq_psn;
307 uint32_t dest_qp_num;
308 uint32_t qp_access_flags;
309 uint16_t pkey_index;
310 uint16_t alt_pkey_index;
311 uint8_t en_sqd_async_notify;
312 uint8_t sq_draining;
313 uint8_t max_rd_atomic;
314 uint8_t max_dest_rd_atomic;
315 uint8_t min_rnr_timer;
316 uint8_t port_num;
317 uint8_t timeout;
318 uint8_t retry_cnt;
319 uint8_t rnr_retry;
320 uint8_t alt_port_num;
321 uint8_t alt_timeout;
322 uint8_t reserved[5];
323 struct pvrdma_qp_cap cap;
324 struct pvrdma_ah_attr ah_attr;
325 struct pvrdma_ah_attr alt_ah_attr;
326};
327
328enum pvrdma_send_flags {
329 PVRDMA_SEND_FENCE = 1 << 0,
330 PVRDMA_SEND_SIGNALED = 1 << 1,
331 PVRDMA_SEND_SOLICITED = 1 << 2,
332 PVRDMA_SEND_INLINE = 1 << 3,
333 PVRDMA_SEND_IP_CSUM = 1 << 4,
334 PVRDMA_SEND_FLAGS_MAX = PVRDMA_SEND_IP_CSUM,
335};
336
337enum pvrdma_access_flags {
338 PVRDMA_ACCESS_LOCAL_WRITE = 1 << 0,
339 PVRDMA_ACCESS_REMOTE_WRITE = 1 << 1,
340 PVRDMA_ACCESS_REMOTE_READ = 1 << 2,
341 PVRDMA_ACCESS_REMOTE_ATOMIC = 1 << 3,
342 PVRDMA_ACCESS_MW_BIND = 1 << 4,
343 PVRDMA_ZERO_BASED = 1 << 5,
344 PVRDMA_ACCESS_ON_DEMAND = 1 << 6,
345 PVRDMA_ACCESS_FLAGS_MAX = PVRDMA_ACCESS_ON_DEMAND,
346};
347
348#endif
349
