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10#ifndef DMA_H
11#define DMA_H
12
13#include "exec/memory.h"
14#include "exec/address-spaces.h"
15#include "block/block.h"
16#include "block/accounting.h"
17
18typedef enum {
19 DMA_DIRECTION_TO_DEVICE = 0,
20 DMA_DIRECTION_FROM_DEVICE = 1,
21} DMADirection;
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30typedef uint64_t dma_addr_t;
31
32#define DMA_ADDR_BITS 64
33#define DMA_ADDR_FMT "%" PRIx64
34
35typedef struct ScatterGatherEntry ScatterGatherEntry;
36
37struct QEMUSGList {
38 ScatterGatherEntry *sg;
39 int nsg;
40 int nalloc;
41 dma_addr_t size;
42 DeviceState *dev;
43 AddressSpace *as;
44};
45
46static inline void dma_barrier(AddressSpace *as, DMADirection dir)
47{
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66 smp_mb();
67}
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72static inline bool dma_memory_valid(AddressSpace *as,
73 dma_addr_t addr, dma_addr_t len,
74 DMADirection dir, MemTxAttrs attrs)
75{
76 return address_space_access_valid(as, addr, len,
77 dir == DMA_DIRECTION_FROM_DEVICE,
78 attrs);
79}
80
81static inline MemTxResult dma_memory_rw_relaxed(AddressSpace *as,
82 dma_addr_t addr,
83 void *buf, dma_addr_t len,
84 DMADirection dir,
85 MemTxAttrs attrs)
86{
87 return address_space_rw(as, addr, attrs,
88 buf, len, dir == DMA_DIRECTION_FROM_DEVICE);
89}
90
91static inline MemTxResult dma_memory_read_relaxed(AddressSpace *as,
92 dma_addr_t addr,
93 void *buf, dma_addr_t len)
94{
95 return dma_memory_rw_relaxed(as, addr, buf, len,
96 DMA_DIRECTION_TO_DEVICE,
97 MEMTXATTRS_UNSPECIFIED);
98}
99
100static inline MemTxResult dma_memory_write_relaxed(AddressSpace *as,
101 dma_addr_t addr,
102 const void *buf,
103 dma_addr_t len)
104{
105 return dma_memory_rw_relaxed(as, addr, (void *)buf, len,
106 DMA_DIRECTION_FROM_DEVICE,
107 MEMTXATTRS_UNSPECIFIED);
108}
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124static inline MemTxResult dma_memory_rw(AddressSpace *as, dma_addr_t addr,
125 void *buf, dma_addr_t len,
126 DMADirection dir, MemTxAttrs attrs)
127{
128 dma_barrier(as, dir);
129
130 return dma_memory_rw_relaxed(as, addr, buf, len, dir, attrs);
131}
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146static inline MemTxResult dma_memory_read(AddressSpace *as, dma_addr_t addr,
147 void *buf, dma_addr_t len,
148 MemTxAttrs attrs)
149{
150 return dma_memory_rw(as, addr, buf, len,
151 DMA_DIRECTION_TO_DEVICE, attrs);
152}
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167static inline MemTxResult dma_memory_write(AddressSpace *as, dma_addr_t addr,
168 const void *buf, dma_addr_t len,
169 MemTxAttrs attrs)
170{
171 return dma_memory_rw(as, addr, (void *)buf, len,
172 DMA_DIRECTION_FROM_DEVICE, attrs);
173}
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188MemTxResult dma_memory_set(AddressSpace *as, dma_addr_t addr,
189 uint8_t c, dma_addr_t len, MemTxAttrs attrs);
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205static inline void *dma_memory_map(AddressSpace *as,
206 dma_addr_t addr, dma_addr_t *len,
207 DMADirection dir, MemTxAttrs attrs)
208{
209 hwaddr xlen = *len;
210 void *p;
211
212 p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE,
213 attrs);
214 *len = xlen;
215 return p;
216}
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232static inline void dma_memory_unmap(AddressSpace *as,
233 void *buffer, dma_addr_t len,
234 DMADirection dir, dma_addr_t access_len)
235{
236 address_space_unmap(as, buffer, (hwaddr)len,
237 dir == DMA_DIRECTION_FROM_DEVICE, access_len);
238}
239
240#define DEFINE_LDST_DMA(_lname, _sname, _bits, _end) \
241 static inline MemTxResult ld##_lname##_##_end##_dma(AddressSpace *as, \
242 dma_addr_t addr, \
243 uint##_bits##_t *pval, \
244 MemTxAttrs attrs) \
245 { \
246 MemTxResult res = dma_memory_read(as, addr, pval, (_bits) / 8, attrs); \
247 _end##_bits##_to_cpus(pval); \
248 return res; \
249 } \
250 static inline MemTxResult st##_sname##_##_end##_dma(AddressSpace *as, \
251 dma_addr_t addr, \
252 uint##_bits##_t val, \
253 MemTxAttrs attrs) \
254 { \
255 val = cpu_to_##_end##_bits(val); \
256 return dma_memory_write(as, addr, &val, (_bits) / 8, attrs); \
257 }
258
259static inline MemTxResult ldub_dma(AddressSpace *as, dma_addr_t addr,
260 uint8_t *val, MemTxAttrs attrs)
261{
262 return dma_memory_read(as, addr, val, 1, attrs);
263}
264
265static inline MemTxResult stb_dma(AddressSpace *as, dma_addr_t addr,
266 uint8_t val, MemTxAttrs attrs)
267{
268 return dma_memory_write(as, addr, &val, 1, attrs);
269}
270
271DEFINE_LDST_DMA(uw, w, 16, le);
272DEFINE_LDST_DMA(l, l, 32, le);
273DEFINE_LDST_DMA(q, q, 64, le);
274DEFINE_LDST_DMA(uw, w, 16, be);
275DEFINE_LDST_DMA(l, l, 32, be);
276DEFINE_LDST_DMA(q, q, 64, be);
277
278#undef DEFINE_LDST_DMA
279
280struct ScatterGatherEntry {
281 dma_addr_t base;
282 dma_addr_t len;
283};
284
285void qemu_sglist_init(QEMUSGList *qsg, DeviceState *dev, int alloc_hint,
286 AddressSpace *as);
287void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len);
288void qemu_sglist_destroy(QEMUSGList *qsg);
289
290typedef BlockAIOCB *DMAIOFunc(int64_t offset, QEMUIOVector *iov,
291 BlockCompletionFunc *cb, void *cb_opaque,
292 void *opaque);
293
294BlockAIOCB *dma_blk_io(AioContext *ctx,
295 QEMUSGList *sg, uint64_t offset, uint32_t align,
296 DMAIOFunc *io_func, void *io_func_opaque,
297 BlockCompletionFunc *cb, void *opaque, DMADirection dir);
298BlockAIOCB *dma_blk_read(BlockBackend *blk,
299 QEMUSGList *sg, uint64_t offset, uint32_t align,
300 BlockCompletionFunc *cb, void *opaque);
301BlockAIOCB *dma_blk_write(BlockBackend *blk,
302 QEMUSGList *sg, uint64_t offset, uint32_t align,
303 BlockCompletionFunc *cb, void *opaque);
304MemTxResult dma_buf_read(void *ptr, dma_addr_t len, dma_addr_t *residual,
305 QEMUSGList *sg, MemTxAttrs attrs);
306MemTxResult dma_buf_write(void *ptr, dma_addr_t len, dma_addr_t *residual,
307 QEMUSGList *sg, MemTxAttrs attrs);
308
309void dma_acct_start(BlockBackend *blk, BlockAcctCookie *cookie,
310 QEMUSGList *sg, enum BlockAcctType type);
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321uint64_t dma_aligned_pow2_mask(uint64_t start, uint64_t end,
322 int max_addr_bits);
323
324#endif
325