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21#include "qemu/osdep.h"
22#include "qemu/qemu-print.h"
23#include "qemu/timer.h"
24#include "qemu/log.h"
25#include "exec/page-vary.h"
26#include "target/arm/idau.h"
27#include "qemu/module.h"
28#include "qapi/error.h"
29#include "qapi/visitor.h"
30#include "cpu.h"
31#ifdef CONFIG_TCG
32#include "hw/core/tcg-cpu-ops.h"
33#endif
34#include "internals.h"
35#include "exec/exec-all.h"
36#include "hw/qdev-properties.h"
37#if !defined(CONFIG_USER_ONLY)
38#include "hw/loader.h"
39#include "hw/boards.h"
40#endif
41#include "sysemu/tcg.h"
42#include "sysemu/qtest.h"
43#include "sysemu/hw_accel.h"
44#include "kvm_arm.h"
45#include "disas/capstone.h"
46#include "fpu/softfloat.h"
47#include "cpregs.h"
48
49static void arm_cpu_set_pc(CPUState *cs, vaddr value)
50{
51 ARMCPU *cpu = ARM_CPU(cs);
52 CPUARMState *env = &cpu->env;
53
54 if (is_a64(env)) {
55 env->pc = value;
56 env->thumb = false;
57 } else {
58 env->regs[15] = value & ~1;
59 env->thumb = value & 1;
60 }
61}
62
63#ifdef CONFIG_TCG
64void arm_cpu_synchronize_from_tb(CPUState *cs,
65 const TranslationBlock *tb)
66{
67 ARMCPU *cpu = ARM_CPU(cs);
68 CPUARMState *env = &cpu->env;
69
70
71
72
73
74 if (is_a64(env)) {
75 env->pc = tb->pc;
76 } else {
77 env->regs[15] = tb->pc;
78 }
79}
80#endif
81
82static bool arm_cpu_has_work(CPUState *cs)
83{
84 ARMCPU *cpu = ARM_CPU(cs);
85
86 return (cpu->power_state != PSCI_OFF)
87 && cs->interrupt_request &
88 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
89 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR
90 | CPU_INTERRUPT_EXITTB);
91}
92
93void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
94 void *opaque)
95{
96 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
97
98 entry->hook = hook;
99 entry->opaque = opaque;
100
101 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node);
102}
103
104void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
105 void *opaque)
106{
107 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
108
109 entry->hook = hook;
110 entry->opaque = opaque;
111
112 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);
113}
114
115static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
116{
117
118 ARMCPRegInfo *ri = value;
119 ARMCPU *cpu = opaque;
120
121 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) {
122 return;
123 }
124
125 if (ri->resetfn) {
126 ri->resetfn(&cpu->env, ri);
127 return;
128 }
129
130
131
132
133
134
135 if (!ri->fieldoffset) {
136 return;
137 }
138
139 if (cpreg_field_is_64bit(ri)) {
140 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
141 } else {
142 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
143 }
144}
145
146static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
147{
148
149
150
151
152
153 ARMCPRegInfo *ri = value;
154 ARMCPU *cpu = opaque;
155 uint64_t oldvalue, newvalue;
156
157 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
158 return;
159 }
160
161 oldvalue = read_raw_cp_reg(&cpu->env, ri);
162 cp_reg_reset(key, value, opaque);
163 newvalue = read_raw_cp_reg(&cpu->env, ri);
164 assert(oldvalue == newvalue);
165}
166
167static void arm_cpu_reset(DeviceState *dev)
168{
169 CPUState *s = CPU(dev);
170 ARMCPU *cpu = ARM_CPU(s);
171 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
172 CPUARMState *env = &cpu->env;
173
174 acc->parent_reset(dev);
175
176 memset(env, 0, offsetof(CPUARMState, end_reset_fields));
177
178 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
179 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
180
181 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
182 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0;
183 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;
184 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;
185
186 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON;
187
188 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
189 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
190 }
191
192 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
193
194 env->aarch64 = true;
195#if defined(CONFIG_USER_ONLY)
196 env->pstate = PSTATE_MODE_EL0t;
197
198 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
199
200 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
201 SCTLR_EnDA | SCTLR_EnDB);
202
203 env->cp15.sctlr_el[1] |= SCTLR_BT0;
204
205 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
206 CPACR_EL1, FPEN, 3);
207
208 if (cpu_isar_feature(aa64_sve, cpu)) {
209 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
210 CPACR_EL1, ZEN, 3);
211 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1;
212 }
213
214 if (cpu_isar_feature(aa64_sme, cpu)) {
215 env->cp15.sctlr_el[1] |= SCTLR_EnTP2;
216 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
217 CPACR_EL1, SMEN, 3);
218 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1;
219 if (cpu_isar_feature(aa64_sme_fa64, cpu)) {
220 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1],
221 SMCR, FA64, 1);
222 }
223 }
224
225
226
227
228
229 env->cp15.tcr_el[1] = 5 | (1ULL << 37);
230
231
232 if (cpu_isar_feature(aa64_mte, cpu)) {
233
234 env->cp15.sctlr_el[1] |= SCTLR_ATA0;
235
236
237
238
239
240
241
242
243 env->cp15.gcr_el1 = 0x1ffff;
244 }
245
246
247
248
249 env->cp15.sctlr_el[1] |= SCTLR_TSCXT;
250#else
251
252 if (arm_feature(env, ARM_FEATURE_EL3)) {
253 env->pstate = PSTATE_MODE_EL3h;
254 } else if (arm_feature(env, ARM_FEATURE_EL2)) {
255 env->pstate = PSTATE_MODE_EL2h;
256 } else {
257 env->pstate = PSTATE_MODE_EL1h;
258 }
259
260
261 env->cp15.rvbar = cpu->rvbar_prop;
262 env->pc = env->cp15.rvbar;
263#endif
264 } else {
265#if defined(CONFIG_USER_ONLY)
266
267 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
268 CPACR, CP10, 3);
269 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
270 CPACR, CP11, 3);
271#endif
272 }
273
274#if defined(CONFIG_USER_ONLY)
275 env->uncached_cpsr = ARM_CPU_MODE_USR;
276
277 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
278 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
279 env->cp15.c15_cpar = 3;
280 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
281 env->cp15.c15_cpar = 1;
282 }
283#else
284
285
286
287
288
289
290 if (arm_feature(env, ARM_FEATURE_EL2) &&
291 !arm_feature(env, ARM_FEATURE_EL3)) {
292 env->uncached_cpsr = ARM_CPU_MODE_HYP;
293 } else {
294 env->uncached_cpsr = ARM_CPU_MODE_SVC;
295 }
296 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
297
298
299
300
301
302 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
303 env->regs[15] = 0xFFFF0000;
304 }
305
306 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
307#endif
308
309 if (arm_feature(env, ARM_FEATURE_M)) {
310#ifndef CONFIG_USER_ONLY
311 uint32_t initial_msp;
312 uint32_t initial_pc;
313 uint8_t *rom;
314 uint32_t vecbase;
315#endif
316
317 if (cpu_isar_feature(aa32_lob, cpu)) {
318
319
320
321
322
323 env->v7m.ltpsize = 4;
324
325 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT;
326 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT;
327 }
328
329 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
330 env->v7m.secure = true;
331 } else {
332
333
334
335
336
337 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
338
339
340
341
342
343
344
345 env->v7m.nsacr = 0xcff;
346 }
347
348
349
350
351
352 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK;
353 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK;
354 if (arm_feature(env, ARM_FEATURE_V8)) {
355
356 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
357 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
358 }
359 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
360 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK;
361 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
362 }
363
364 if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
365 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
366 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
367 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
368 }
369
370#ifndef CONFIG_USER_ONLY
371
372 env->regs[14] = 0xffffffff;
373
374 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80;
375 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80;
376
377
378 vecbase = env->v7m.vecbase[env->v7m.secure];
379 rom = rom_ptr_for_as(s->as, vecbase, 8);
380 if (rom) {
381
382
383
384 initial_msp = ldl_p(rom);
385 initial_pc = ldl_p(rom + 4);
386 } else {
387
388
389
390
391
392 initial_msp = ldl_phys(s->as, vecbase);
393 initial_pc = ldl_phys(s->as, vecbase + 4);
394 }
395
396 qemu_log_mask(CPU_LOG_INT,
397 "Loaded reset SP 0x%x PC 0x%x from vector table\n",
398 initial_msp, initial_pc);
399
400 env->regs[13] = initial_msp & 0xFFFFFFFC;
401 env->regs[15] = initial_pc & ~1;
402 env->thumb = initial_pc & 1;
403#else
404
405
406
407
408
409 env->v7m.secure = false;
410 env->v7m.nsacr = 0xcff;
411 env->v7m.cpacr[M_REG_NS] = 0xf0ffff;
412 env->v7m.fpccr[M_REG_S] &=
413 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK);
414 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK;
415#endif
416 }
417
418
419
420
421
422 arm_clear_exclusive(env);
423
424 if (arm_feature(env, ARM_FEATURE_PMSA)) {
425 if (cpu->pmsav7_dregion > 0) {
426 if (arm_feature(env, ARM_FEATURE_V8)) {
427 memset(env->pmsav8.rbar[M_REG_NS], 0,
428 sizeof(*env->pmsav8.rbar[M_REG_NS])
429 * cpu->pmsav7_dregion);
430 memset(env->pmsav8.rlar[M_REG_NS], 0,
431 sizeof(*env->pmsav8.rlar[M_REG_NS])
432 * cpu->pmsav7_dregion);
433 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
434 memset(env->pmsav8.rbar[M_REG_S], 0,
435 sizeof(*env->pmsav8.rbar[M_REG_S])
436 * cpu->pmsav7_dregion);
437 memset(env->pmsav8.rlar[M_REG_S], 0,
438 sizeof(*env->pmsav8.rlar[M_REG_S])
439 * cpu->pmsav7_dregion);
440 }
441 } else if (arm_feature(env, ARM_FEATURE_V7)) {
442 memset(env->pmsav7.drbar, 0,
443 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
444 memset(env->pmsav7.drsr, 0,
445 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
446 memset(env->pmsav7.dracr, 0,
447 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
448 }
449 }
450 env->pmsav7.rnr[M_REG_NS] = 0;
451 env->pmsav7.rnr[M_REG_S] = 0;
452 env->pmsav8.mair0[M_REG_NS] = 0;
453 env->pmsav8.mair0[M_REG_S] = 0;
454 env->pmsav8.mair1[M_REG_NS] = 0;
455 env->pmsav8.mair1[M_REG_S] = 0;
456 }
457
458 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
459 if (cpu->sau_sregion > 0) {
460 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion);
461 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion);
462 }
463 env->sau.rnr = 0;
464
465
466
467 env->sau.ctrl = 0;
468 }
469
470 set_flush_to_zero(1, &env->vfp.standard_fp_status);
471 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
472 set_default_nan_mode(1, &env->vfp.standard_fp_status);
473 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16);
474 set_float_detect_tininess(float_tininess_before_rounding,
475 &env->vfp.fp_status);
476 set_float_detect_tininess(float_tininess_before_rounding,
477 &env->vfp.standard_fp_status);
478 set_float_detect_tininess(float_tininess_before_rounding,
479 &env->vfp.fp_status_f16);
480 set_float_detect_tininess(float_tininess_before_rounding,
481 &env->vfp.standard_fp_status_f16);
482#ifndef CONFIG_USER_ONLY
483 if (kvm_enabled()) {
484 kvm_arm_reset_vcpu(cpu);
485 }
486#endif
487
488 hw_breakpoint_update_all(cpu);
489 hw_watchpoint_update_all(cpu);
490 arm_rebuild_hflags(env);
491}
492
493#ifndef CONFIG_USER_ONLY
494
495static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
496 unsigned int target_el,
497 unsigned int cur_el, bool secure,
498 uint64_t hcr_el2)
499{
500 CPUARMState *env = cs->env_ptr;
501 bool pstate_unmasked;
502 bool unmasked = false;
503
504
505
506
507
508
509 if (cur_el > target_el) {
510 return false;
511 }
512
513 switch (excp_idx) {
514 case EXCP_FIQ:
515 pstate_unmasked = !(env->daif & PSTATE_F);
516 break;
517
518 case EXCP_IRQ:
519 pstate_unmasked = !(env->daif & PSTATE_I);
520 break;
521
522 case EXCP_VFIQ:
523 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
524
525 return false;
526 }
527 return !(env->daif & PSTATE_F);
528 case EXCP_VIRQ:
529 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
530
531 return false;
532 }
533 return !(env->daif & PSTATE_I);
534 case EXCP_VSERR:
535 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) {
536
537 return false;
538 }
539 return !(env->daif & PSTATE_A);
540 default:
541 g_assert_not_reached();
542 }
543
544
545
546
547
548
549 if ((target_el > cur_el) && (target_el != 1)) {
550
551 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
552
553
554
555
556
557
558 if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) {
559 unmasked = true;
560 }
561 } else {
562
563
564
565
566
567 bool hcr, scr;
568
569 switch (excp_idx) {
570 case EXCP_FIQ:
571
572
573
574
575
576
577
578 hcr = hcr_el2 & HCR_FMO;
579 scr = (env->cp15.scr_el3 & SCR_FIQ);
580
581
582
583
584
585
586
587 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
588 break;
589 case EXCP_IRQ:
590
591
592
593
594
595
596
597 hcr = hcr_el2 & HCR_IMO;
598 scr = false;
599 break;
600 default:
601 g_assert_not_reached();
602 }
603
604 if ((scr || hcr) && !secure) {
605 unmasked = true;
606 }
607 }
608 }
609
610
611
612
613
614 return unmasked || pstate_unmasked;
615}
616
617static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
618{
619 CPUClass *cc = CPU_GET_CLASS(cs);
620 CPUARMState *env = cs->env_ptr;
621 uint32_t cur_el = arm_current_el(env);
622 bool secure = arm_is_secure(env);
623 uint64_t hcr_el2 = arm_hcr_el2_eff(env);
624 uint32_t target_el;
625 uint32_t excp_idx;
626
627
628
629 if (interrupt_request & CPU_INTERRUPT_FIQ) {
630 excp_idx = EXCP_FIQ;
631 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
632 if (arm_excp_unmasked(cs, excp_idx, target_el,
633 cur_el, secure, hcr_el2)) {
634 goto found;
635 }
636 }
637 if (interrupt_request & CPU_INTERRUPT_HARD) {
638 excp_idx = EXCP_IRQ;
639 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
640 if (arm_excp_unmasked(cs, excp_idx, target_el,
641 cur_el, secure, hcr_el2)) {
642 goto found;
643 }
644 }
645 if (interrupt_request & CPU_INTERRUPT_VIRQ) {
646 excp_idx = EXCP_VIRQ;
647 target_el = 1;
648 if (arm_excp_unmasked(cs, excp_idx, target_el,
649 cur_el, secure, hcr_el2)) {
650 goto found;
651 }
652 }
653 if (interrupt_request & CPU_INTERRUPT_VFIQ) {
654 excp_idx = EXCP_VFIQ;
655 target_el = 1;
656 if (arm_excp_unmasked(cs, excp_idx, target_el,
657 cur_el, secure, hcr_el2)) {
658 goto found;
659 }
660 }
661 if (interrupt_request & CPU_INTERRUPT_VSERR) {
662 excp_idx = EXCP_VSERR;
663 target_el = 1;
664 if (arm_excp_unmasked(cs, excp_idx, target_el,
665 cur_el, secure, hcr_el2)) {
666
667 env->cp15.hcr_el2 &= ~HCR_VSE;
668 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
669 goto found;
670 }
671 }
672 return false;
673
674 found:
675 cs->exception_index = excp_idx;
676 env->exception.target_el = target_el;
677 cc->tcg_ops->do_interrupt(cs);
678 return true;
679}
680#endif
681
682void arm_cpu_update_virq(ARMCPU *cpu)
683{
684
685
686
687
688 CPUARMState *env = &cpu->env;
689 CPUState *cs = CPU(cpu);
690
691 bool new_state = (env->cp15.hcr_el2 & HCR_VI) ||
692 (env->irq_line_state & CPU_INTERRUPT_VIRQ);
693
694 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) {
695 if (new_state) {
696 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ);
697 } else {
698 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ);
699 }
700 }
701}
702
703void arm_cpu_update_vfiq(ARMCPU *cpu)
704{
705
706
707
708
709 CPUARMState *env = &cpu->env;
710 CPUState *cs = CPU(cpu);
711
712 bool new_state = (env->cp15.hcr_el2 & HCR_VF) ||
713 (env->irq_line_state & CPU_INTERRUPT_VFIQ);
714
715 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) {
716 if (new_state) {
717 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ);
718 } else {
719 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ);
720 }
721 }
722}
723
724void arm_cpu_update_vserr(ARMCPU *cpu)
725{
726
727
728
729 CPUARMState *env = &cpu->env;
730 CPUState *cs = CPU(cpu);
731
732 bool new_state = env->cp15.hcr_el2 & HCR_VSE;
733
734 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) {
735 if (new_state) {
736 cpu_interrupt(cs, CPU_INTERRUPT_VSERR);
737 } else {
738 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
739 }
740 }
741}
742
743#ifndef CONFIG_USER_ONLY
744static void arm_cpu_set_irq(void *opaque, int irq, int level)
745{
746 ARMCPU *cpu = opaque;
747 CPUARMState *env = &cpu->env;
748 CPUState *cs = CPU(cpu);
749 static const int mask[] = {
750 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
751 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
752 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
753 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
754 };
755
756 if (!arm_feature(env, ARM_FEATURE_EL2) &&
757 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) {
758
759
760
761
762
763 return;
764 }
765
766 if (level) {
767 env->irq_line_state |= mask[irq];
768 } else {
769 env->irq_line_state &= ~mask[irq];
770 }
771
772 switch (irq) {
773 case ARM_CPU_VIRQ:
774 arm_cpu_update_virq(cpu);
775 break;
776 case ARM_CPU_VFIQ:
777 arm_cpu_update_vfiq(cpu);
778 break;
779 case ARM_CPU_IRQ:
780 case ARM_CPU_FIQ:
781 if (level) {
782 cpu_interrupt(cs, mask[irq]);
783 } else {
784 cpu_reset_interrupt(cs, mask[irq]);
785 }
786 break;
787 default:
788 g_assert_not_reached();
789 }
790}
791
792static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
793{
794#ifdef CONFIG_KVM
795 ARMCPU *cpu = opaque;
796 CPUARMState *env = &cpu->env;
797 CPUState *cs = CPU(cpu);
798 uint32_t linestate_bit;
799 int irq_id;
800
801 switch (irq) {
802 case ARM_CPU_IRQ:
803 irq_id = KVM_ARM_IRQ_CPU_IRQ;
804 linestate_bit = CPU_INTERRUPT_HARD;
805 break;
806 case ARM_CPU_FIQ:
807 irq_id = KVM_ARM_IRQ_CPU_FIQ;
808 linestate_bit = CPU_INTERRUPT_FIQ;
809 break;
810 default:
811 g_assert_not_reached();
812 }
813
814 if (level) {
815 env->irq_line_state |= linestate_bit;
816 } else {
817 env->irq_line_state &= ~linestate_bit;
818 }
819 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level);
820#endif
821}
822
823static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
824{
825 ARMCPU *cpu = ARM_CPU(cs);
826 CPUARMState *env = &cpu->env;
827
828 cpu_synchronize_state(cs);
829 return arm_cpu_data_is_big_endian(env);
830}
831
832#endif
833
834static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
835{
836 ARMCPU *ac = ARM_CPU(cpu);
837 CPUARMState *env = &ac->env;
838 bool sctlr_b;
839
840 if (is_a64(env)) {
841 info->cap_arch = CS_ARCH_ARM64;
842 info->cap_insn_unit = 4;
843 info->cap_insn_split = 4;
844 } else {
845 int cap_mode;
846 if (env->thumb) {
847 info->cap_insn_unit = 2;
848 info->cap_insn_split = 4;
849 cap_mode = CS_MODE_THUMB;
850 } else {
851 info->cap_insn_unit = 4;
852 info->cap_insn_split = 4;
853 cap_mode = CS_MODE_ARM;
854 }
855 if (arm_feature(env, ARM_FEATURE_V8)) {
856 cap_mode |= CS_MODE_V8;
857 }
858 if (arm_feature(env, ARM_FEATURE_M)) {
859 cap_mode |= CS_MODE_MCLASS;
860 }
861 info->cap_arch = CS_ARCH_ARM;
862 info->cap_mode = cap_mode;
863 }
864
865 sctlr_b = arm_sctlr_b(env);
866 if (bswap_code(sctlr_b)) {
867#if TARGET_BIG_ENDIAN
868 info->endian = BFD_ENDIAN_LITTLE;
869#else
870 info->endian = BFD_ENDIAN_BIG;
871#endif
872 }
873 info->flags &= ~INSN_ARM_BE32;
874#ifndef CONFIG_USER_ONLY
875 if (sctlr_b) {
876 info->flags |= INSN_ARM_BE32;
877 }
878#endif
879}
880
881#ifdef TARGET_AARCH64
882
883static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
884{
885 ARMCPU *cpu = ARM_CPU(cs);
886 CPUARMState *env = &cpu->env;
887 uint32_t psr = pstate_read(env);
888 int i;
889 int el = arm_current_el(env);
890 const char *ns_status;
891 bool sve;
892
893 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
894 for (i = 0; i < 32; i++) {
895 if (i == 31) {
896 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
897 } else {
898 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
899 (i + 2) % 3 ? " " : "\n");
900 }
901 }
902
903 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
904 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
905 } else {
906 ns_status = "";
907 }
908 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
909 psr,
910 psr & PSTATE_N ? 'N' : '-',
911 psr & PSTATE_Z ? 'Z' : '-',
912 psr & PSTATE_C ? 'C' : '-',
913 psr & PSTATE_V ? 'V' : '-',
914 ns_status,
915 el,
916 psr & PSTATE_SP ? 'h' : 't');
917
918 if (cpu_isar_feature(aa64_sme, cpu)) {
919 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c",
920 env->svcr,
921 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'),
922 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-'));
923 }
924 if (cpu_isar_feature(aa64_bti, cpu)) {
925 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
926 }
927 if (!(flags & CPU_DUMP_FPU)) {
928 qemu_fprintf(f, "\n");
929 return;
930 }
931 if (fp_exception_el(env, el) != 0) {
932 qemu_fprintf(f, " FPU disabled\n");
933 return;
934 }
935 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
936 vfp_get_fpcr(env), vfp_get_fpsr(env));
937
938 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) {
939 sve = sme_exception_el(env, el) == 0;
940 } else if (cpu_isar_feature(aa64_sve, cpu)) {
941 sve = sve_exception_el(env, el) == 0;
942 } else {
943 sve = false;
944 }
945
946 if (sve) {
947 int j, zcr_len = sve_vqm1_for_el(env, el);
948
949 for (i = 0; i <= FFR_PRED_NUM; i++) {
950 bool eol;
951 if (i == FFR_PRED_NUM) {
952 qemu_fprintf(f, "FFR=");
953
954 eol = true;
955 } else {
956 qemu_fprintf(f, "P%02d=", i);
957 switch (zcr_len) {
958 case 0:
959 eol = i % 8 == 7;
960 break;
961 case 1:
962 eol = i % 6 == 5;
963 break;
964 case 2:
965 case 3:
966 eol = i % 3 == 2;
967 break;
968 default:
969
970 eol = true;
971 break;
972 }
973 }
974 for (j = zcr_len / 4; j >= 0; j--) {
975 int digits;
976 if (j * 4 + 4 <= zcr_len + 1) {
977 digits = 16;
978 } else {
979 digits = (zcr_len % 4 + 1) * 4;
980 }
981 qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
982 env->vfp.pregs[i].p[j],
983 j ? ":" : eol ? "\n" : " ");
984 }
985 }
986
987 for (i = 0; i < 32; i++) {
988 if (zcr_len == 0) {
989 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
990 i, env->vfp.zregs[i].d[1],
991 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
992 } else if (zcr_len == 1) {
993 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
994 ":%016" PRIx64 ":%016" PRIx64 "\n",
995 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
996 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
997 } else {
998 for (j = zcr_len; j >= 0; j--) {
999 bool odd = (zcr_len - j) % 2 != 0;
1000 if (j == zcr_len) {
1001 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
1002 } else if (!odd) {
1003 if (j > 0) {
1004 qemu_fprintf(f, " [%x-%x]=", j, j - 1);
1005 } else {
1006 qemu_fprintf(f, " [%x]=", j);
1007 }
1008 }
1009 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
1010 env->vfp.zregs[i].d[j * 2 + 1],
1011 env->vfp.zregs[i].d[j * 2],
1012 odd || j == 0 ? "\n" : ":");
1013 }
1014 }
1015 }
1016 } else {
1017 for (i = 0; i < 32; i++) {
1018 uint64_t *q = aa64_vfp_qreg(env, i);
1019 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
1020 i, q[1], q[0], (i & 1 ? "\n" : " "));
1021 }
1022 }
1023}
1024
1025#else
1026
1027static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
1028{
1029 g_assert_not_reached();
1030}
1031
1032#endif
1033
1034static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
1035{
1036 ARMCPU *cpu = ARM_CPU(cs);
1037 CPUARMState *env = &cpu->env;
1038 int i;
1039
1040 if (is_a64(env)) {
1041 aarch64_cpu_dump_state(cs, f, flags);
1042 return;
1043 }
1044
1045 for (i = 0; i < 16; i++) {
1046 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
1047 if ((i % 4) == 3) {
1048 qemu_fprintf(f, "\n");
1049 } else {
1050 qemu_fprintf(f, " ");
1051 }
1052 }
1053
1054 if (arm_feature(env, ARM_FEATURE_M)) {
1055 uint32_t xpsr = xpsr_read(env);
1056 const char *mode;
1057 const char *ns_status = "";
1058
1059 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1060 ns_status = env->v7m.secure ? "S " : "NS ";
1061 }
1062
1063 if (xpsr & XPSR_EXCP) {
1064 mode = "handler";
1065 } else {
1066 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
1067 mode = "unpriv-thread";
1068 } else {
1069 mode = "priv-thread";
1070 }
1071 }
1072
1073 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
1074 xpsr,
1075 xpsr & XPSR_N ? 'N' : '-',
1076 xpsr & XPSR_Z ? 'Z' : '-',
1077 xpsr & XPSR_C ? 'C' : '-',
1078 xpsr & XPSR_V ? 'V' : '-',
1079 xpsr & XPSR_T ? 'T' : 'A',
1080 ns_status,
1081 mode);
1082 } else {
1083 uint32_t psr = cpsr_read(env);
1084 const char *ns_status = "";
1085
1086 if (arm_feature(env, ARM_FEATURE_EL3) &&
1087 (psr & CPSR_M) != ARM_CPU_MODE_MON) {
1088 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
1089 }
1090
1091 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
1092 psr,
1093 psr & CPSR_N ? 'N' : '-',
1094 psr & CPSR_Z ? 'Z' : '-',
1095 psr & CPSR_C ? 'C' : '-',
1096 psr & CPSR_V ? 'V' : '-',
1097 psr & CPSR_T ? 'T' : 'A',
1098 ns_status,
1099 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
1100 }
1101
1102 if (flags & CPU_DUMP_FPU) {
1103 int numvfpregs = 0;
1104 if (cpu_isar_feature(aa32_simd_r32, cpu)) {
1105 numvfpregs = 32;
1106 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
1107 numvfpregs = 16;
1108 }
1109 for (i = 0; i < numvfpregs; i++) {
1110 uint64_t v = *aa32_vfp_dreg(env, i);
1111 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
1112 i * 2, (uint32_t)v,
1113 i * 2 + 1, (uint32_t)(v >> 32),
1114 i, v);
1115 }
1116 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
1117 if (cpu_isar_feature(aa32_mve, cpu)) {
1118 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr);
1119 }
1120 }
1121}
1122
1123uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
1124{
1125 uint32_t Aff1 = idx / clustersz;
1126 uint32_t Aff0 = idx % clustersz;
1127 return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
1128}
1129
1130static void arm_cpu_initfn(Object *obj)
1131{
1132 ARMCPU *cpu = ARM_CPU(obj);
1133
1134 cpu_set_cpustate_pointers(cpu);
1135 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal,
1136 NULL, g_free);
1137
1138 QLIST_INIT(&cpu->pre_el_change_hooks);
1139 QLIST_INIT(&cpu->el_change_hooks);
1140
1141#ifdef CONFIG_USER_ONLY
1142# ifdef TARGET_AARCH64
1143
1144
1145
1146
1147
1148
1149 cpu->sve_default_vq = 4;
1150 cpu->sme_default_vq = 2;
1151# endif
1152#else
1153
1154 if (kvm_enabled()) {
1155
1156
1157
1158 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
1159 } else {
1160 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
1161 }
1162
1163 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
1164 ARRAY_SIZE(cpu->gt_timer_outputs));
1165
1166 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
1167 "gicv3-maintenance-interrupt", 1);
1168 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
1169 "pmu-interrupt", 1);
1170#endif
1171
1172
1173
1174
1175
1176 cpu->dtb_compatible = "qemu,unknown";
1177 cpu->psci_version = QEMU_PSCI_VERSION_0_1;
1178 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
1179
1180 if (tcg_enabled() || hvf_enabled()) {
1181
1182 cpu->psci_version = QEMU_PSCI_VERSION_1_1;
1183 }
1184}
1185
1186static Property arm_cpu_gt_cntfrq_property =
1187 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz,
1188 NANOSECONDS_PER_SECOND / GTIMER_SCALE);
1189
1190static Property arm_cpu_reset_cbar_property =
1191 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
1192
1193static Property arm_cpu_reset_hivecs_property =
1194 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
1195
1196#ifndef CONFIG_USER_ONLY
1197static Property arm_cpu_has_el2_property =
1198 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
1199
1200static Property arm_cpu_has_el3_property =
1201 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
1202#endif
1203
1204static Property arm_cpu_cfgend_property =
1205 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
1206
1207static Property arm_cpu_has_vfp_property =
1208 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
1209
1210static Property arm_cpu_has_neon_property =
1211 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true);
1212
1213static Property arm_cpu_has_dsp_property =
1214 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true);
1215
1216static Property arm_cpu_has_mpu_property =
1217 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
1218
1219
1220
1221
1222
1223
1224static Property arm_cpu_pmsav7_dregion_property =
1225 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
1226 pmsav7_dregion,
1227 qdev_prop_uint32, uint32_t);
1228
1229static bool arm_get_pmu(Object *obj, Error **errp)
1230{
1231 ARMCPU *cpu = ARM_CPU(obj);
1232
1233 return cpu->has_pmu;
1234}
1235
1236static void arm_set_pmu(Object *obj, bool value, Error **errp)
1237{
1238 ARMCPU *cpu = ARM_CPU(obj);
1239
1240 if (value) {
1241 if (kvm_enabled() && !kvm_arm_pmu_supported()) {
1242 error_setg(errp, "'pmu' feature not supported by KVM on this host");
1243 return;
1244 }
1245 set_feature(&cpu->env, ARM_FEATURE_PMU);
1246 } else {
1247 unset_feature(&cpu->env, ARM_FEATURE_PMU);
1248 }
1249 cpu->has_pmu = value;
1250}
1251
1252unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
1253{
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ?
1273 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
1274}
1275
1276void arm_cpu_post_init(Object *obj)
1277{
1278 ARMCPU *cpu = ARM_CPU(obj);
1279
1280
1281
1282
1283
1284 if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
1285 set_feature(&cpu->env, ARM_FEATURE_PMSA);
1286 }
1287
1288 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
1289 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
1290 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property);
1291 }
1292
1293 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
1294 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property);
1295 }
1296
1297 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1298 object_property_add_uint64_ptr(obj, "rvbar",
1299 &cpu->rvbar_prop,
1300 OBJ_PROP_FLAG_READWRITE);
1301 }
1302
1303#ifndef CONFIG_USER_ONLY
1304 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1305
1306
1307
1308 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property);
1309
1310 object_property_add_link(obj, "secure-memory",
1311 TYPE_MEMORY_REGION,
1312 (Object **)&cpu->secure_memory,
1313 qdev_prop_allow_set_link_before_realize,
1314 OBJ_PROP_LINK_STRONG);
1315 }
1316
1317 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
1318 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property);
1319 }
1320#endif
1321
1322 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
1323 cpu->has_pmu = true;
1324 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu);
1325 }
1326
1327
1328
1329
1330
1331
1332 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)
1333 ? cpu_isar_feature(aa64_fp_simd, cpu)
1334 : cpu_isar_feature(aa32_vfp, cpu)) {
1335 cpu->has_vfp = true;
1336 if (!kvm_enabled()) {
1337 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property);
1338 }
1339 }
1340
1341 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
1342 cpu->has_neon = true;
1343 if (!kvm_enabled()) {
1344 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property);
1345 }
1346 }
1347
1348 if (arm_feature(&cpu->env, ARM_FEATURE_M) &&
1349 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) {
1350 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property);
1351 }
1352
1353 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
1354 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property);
1355 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1356 qdev_property_add_static(DEVICE(obj),
1357 &arm_cpu_pmsav7_dregion_property);
1358 }
1359 }
1360
1361 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) {
1362 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau,
1363 qdev_prop_allow_set_link_before_realize,
1364 OBJ_PROP_LINK_STRONG);
1365
1366
1367
1368
1369
1370 object_property_add_uint32_ptr(obj, "init-svtor",
1371 &cpu->init_svtor,
1372 OBJ_PROP_FLAG_READWRITE);
1373 }
1374 if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
1375
1376
1377
1378
1379 object_property_add_uint32_ptr(obj, "init-nsvtor",
1380 &cpu->init_nsvtor,
1381 OBJ_PROP_FLAG_READWRITE);
1382 }
1383
1384
1385 object_property_add_uint32_ptr(obj, "psci-conduit",
1386 &cpu->psci_conduit,
1387 OBJ_PROP_FLAG_READWRITE);
1388
1389 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property);
1390
1391 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) {
1392 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property);
1393 }
1394
1395 if (kvm_enabled()) {
1396 kvm_arm_add_vcpu_properties(obj);
1397 }
1398
1399#ifndef CONFIG_USER_ONLY
1400 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) &&
1401 cpu_isar_feature(aa64_mte, cpu)) {
1402 object_property_add_link(obj, "tag-memory",
1403 TYPE_MEMORY_REGION,
1404 (Object **)&cpu->tag_memory,
1405 qdev_prop_allow_set_link_before_realize,
1406 OBJ_PROP_LINK_STRONG);
1407
1408 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1409 object_property_add_link(obj, "secure-tag-memory",
1410 TYPE_MEMORY_REGION,
1411 (Object **)&cpu->secure_tag_memory,
1412 qdev_prop_allow_set_link_before_realize,
1413 OBJ_PROP_LINK_STRONG);
1414 }
1415 }
1416#endif
1417}
1418
1419static void arm_cpu_finalizefn(Object *obj)
1420{
1421 ARMCPU *cpu = ARM_CPU(obj);
1422 ARMELChangeHook *hook, *next;
1423
1424 g_hash_table_destroy(cpu->cp_regs);
1425
1426 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
1427 QLIST_REMOVE(hook, node);
1428 g_free(hook);
1429 }
1430 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
1431 QLIST_REMOVE(hook, node);
1432 g_free(hook);
1433 }
1434#ifndef CONFIG_USER_ONLY
1435 if (cpu->pmu_timer) {
1436 timer_free(cpu->pmu_timer);
1437 }
1438#endif
1439}
1440
1441void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
1442{
1443 Error *local_err = NULL;
1444
1445#ifdef TARGET_AARCH64
1446 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1447 arm_cpu_sve_finalize(cpu, &local_err);
1448 if (local_err != NULL) {
1449 error_propagate(errp, local_err);
1450 return;
1451 }
1452
1453 arm_cpu_sme_finalize(cpu, &local_err);
1454 if (local_err != NULL) {
1455 error_propagate(errp, local_err);
1456 return;
1457 }
1458
1459 arm_cpu_pauth_finalize(cpu, &local_err);
1460 if (local_err != NULL) {
1461 error_propagate(errp, local_err);
1462 return;
1463 }
1464
1465 arm_cpu_lpa2_finalize(cpu, &local_err);
1466 if (local_err != NULL) {
1467 error_propagate(errp, local_err);
1468 return;
1469 }
1470 }
1471#endif
1472
1473 if (kvm_enabled()) {
1474 kvm_arm_steal_time_finalize(cpu, &local_err);
1475 if (local_err != NULL) {
1476 error_propagate(errp, local_err);
1477 return;
1478 }
1479 }
1480}
1481
1482static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
1483{
1484 CPUState *cs = CPU(dev);
1485 ARMCPU *cpu = ARM_CPU(dev);
1486 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
1487 CPUARMState *env = &cpu->env;
1488 int pagebits;
1489 Error *local_err = NULL;
1490 bool no_aa32 = false;
1491
1492
1493
1494
1495
1496 if (cpu->host_cpu_probe_failed) {
1497 if (!kvm_enabled() && !hvf_enabled()) {
1498 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF");
1499 } else {
1500 error_setg(errp, "Failed to retrieve host CPU features");
1501 }
1502 return;
1503 }
1504
1505#ifndef CONFIG_USER_ONLY
1506
1507
1508
1509
1510 if (arm_feature(env, ARM_FEATURE_M)) {
1511 if (!env->nvic) {
1512 error_setg(errp, "This board cannot be used with Cortex-M CPUs");
1513 return;
1514 }
1515 } else {
1516 if (env->nvic) {
1517 error_setg(errp, "This board can only be used with Cortex-M CPUs");
1518 return;
1519 }
1520 }
1521
1522 if (!tcg_enabled() && !qtest_enabled()) {
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532 if (arm_feature(env, ARM_FEATURE_M)) {
1533 error_setg(errp,
1534 "Cannot enable %s when using an M-profile guest CPU",
1535 current_accel_name());
1536 return;
1537 }
1538 if (cpu->has_el3) {
1539 error_setg(errp,
1540 "Cannot enable %s when guest CPU has EL3 enabled",
1541 current_accel_name());
1542 return;
1543 }
1544 if (cpu->tag_memory) {
1545 error_setg(errp,
1546 "Cannot enable %s when guest CPUs has MTE enabled",
1547 current_accel_name());
1548 return;
1549 }
1550 }
1551
1552 {
1553 uint64_t scale;
1554
1555 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1556 if (!cpu->gt_cntfrq_hz) {
1557 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz",
1558 cpu->gt_cntfrq_hz);
1559 return;
1560 }
1561 scale = gt_cntfrq_period_ns(cpu);
1562 } else {
1563 scale = GTIMER_SCALE;
1564 }
1565
1566 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1567 arm_gt_ptimer_cb, cpu);
1568 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1569 arm_gt_vtimer_cb, cpu);
1570 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1571 arm_gt_htimer_cb, cpu);
1572 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1573 arm_gt_stimer_cb, cpu);
1574 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1575 arm_gt_hvtimer_cb, cpu);
1576 }
1577#endif
1578
1579 cpu_exec_realizefn(cs, &local_err);
1580 if (local_err != NULL) {
1581 error_propagate(errp, local_err);
1582 return;
1583 }
1584
1585 arm_cpu_finalize_features(cpu, &local_err);
1586 if (local_err != NULL) {
1587 error_propagate(errp, local_err);
1588 return;
1589 }
1590
1591 if (arm_feature(env, ARM_FEATURE_AARCH64) &&
1592 cpu->has_vfp != cpu->has_neon) {
1593
1594
1595
1596
1597 error_setg(errp,
1598 "AArch64 CPUs must have both VFP and Neon or neither");
1599 return;
1600 }
1601
1602 if (!cpu->has_vfp) {
1603 uint64_t t;
1604 uint32_t u;
1605
1606 t = cpu->isar.id_aa64isar1;
1607 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0);
1608 cpu->isar.id_aa64isar1 = t;
1609
1610 t = cpu->isar.id_aa64pfr0;
1611 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf);
1612 cpu->isar.id_aa64pfr0 = t;
1613
1614 u = cpu->isar.id_isar6;
1615 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);
1616 u = FIELD_DP32(u, ID_ISAR6, BF16, 0);
1617 cpu->isar.id_isar6 = u;
1618
1619 u = cpu->isar.mvfr0;
1620 u = FIELD_DP32(u, MVFR0, FPSP, 0);
1621 u = FIELD_DP32(u, MVFR0, FPDP, 0);
1622 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0);
1623 u = FIELD_DP32(u, MVFR0, FPSQRT, 0);
1624 u = FIELD_DP32(u, MVFR0, FPROUND, 0);
1625 if (!arm_feature(env, ARM_FEATURE_M)) {
1626 u = FIELD_DP32(u, MVFR0, FPTRAP, 0);
1627 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0);
1628 }
1629 cpu->isar.mvfr0 = u;
1630
1631 u = cpu->isar.mvfr1;
1632 u = FIELD_DP32(u, MVFR1, FPFTZ, 0);
1633 u = FIELD_DP32(u, MVFR1, FPDNAN, 0);
1634 u = FIELD_DP32(u, MVFR1, FPHP, 0);
1635 if (arm_feature(env, ARM_FEATURE_M)) {
1636 u = FIELD_DP32(u, MVFR1, FP16, 0);
1637 }
1638 cpu->isar.mvfr1 = u;
1639
1640 u = cpu->isar.mvfr2;
1641 u = FIELD_DP32(u, MVFR2, FPMISC, 0);
1642 cpu->isar.mvfr2 = u;
1643 }
1644
1645 if (!cpu->has_neon) {
1646 uint64_t t;
1647 uint32_t u;
1648
1649 unset_feature(env, ARM_FEATURE_NEON);
1650
1651 t = cpu->isar.id_aa64isar0;
1652 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0);
1653 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0);
1654 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0);
1655 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0);
1656 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0);
1657 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0);
1658 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
1659 cpu->isar.id_aa64isar0 = t;
1660
1661 t = cpu->isar.id_aa64isar1;
1662 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0);
1663 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0);
1664 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0);
1665 cpu->isar.id_aa64isar1 = t;
1666
1667 t = cpu->isar.id_aa64pfr0;
1668 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf);
1669 cpu->isar.id_aa64pfr0 = t;
1670
1671 u = cpu->isar.id_isar5;
1672 u = FIELD_DP32(u, ID_ISAR5, AES, 0);
1673 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0);
1674 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0);
1675 u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
1676 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
1677 cpu->isar.id_isar5 = u;
1678
1679 u = cpu->isar.id_isar6;
1680 u = FIELD_DP32(u, ID_ISAR6, DP, 0);
1681 u = FIELD_DP32(u, ID_ISAR6, FHM, 0);
1682 u = FIELD_DP32(u, ID_ISAR6, BF16, 0);
1683 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0);
1684 cpu->isar.id_isar6 = u;
1685
1686 if (!arm_feature(env, ARM_FEATURE_M)) {
1687 u = cpu->isar.mvfr1;
1688 u = FIELD_DP32(u, MVFR1, SIMDLS, 0);
1689 u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
1690 u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
1691 u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
1692 cpu->isar.mvfr1 = u;
1693
1694 u = cpu->isar.mvfr2;
1695 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0);
1696 cpu->isar.mvfr2 = u;
1697 }
1698 }
1699
1700 if (!cpu->has_neon && !cpu->has_vfp) {
1701 uint64_t t;
1702 uint32_t u;
1703
1704 t = cpu->isar.id_aa64isar0;
1705 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0);
1706 cpu->isar.id_aa64isar0 = t;
1707
1708 t = cpu->isar.id_aa64isar1;
1709 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0);
1710 cpu->isar.id_aa64isar1 = t;
1711
1712 u = cpu->isar.mvfr0;
1713 u = FIELD_DP32(u, MVFR0, SIMDREG, 0);
1714 cpu->isar.mvfr0 = u;
1715
1716
1717 u = cpu->isar.mvfr1;
1718 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
1719 cpu->isar.mvfr1 = u;
1720 }
1721
1722 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) {
1723 uint32_t u;
1724
1725 unset_feature(env, ARM_FEATURE_THUMB_DSP);
1726
1727 u = cpu->isar.id_isar1;
1728 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1);
1729 cpu->isar.id_isar1 = u;
1730
1731 u = cpu->isar.id_isar2;
1732 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1);
1733 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1);
1734 cpu->isar.id_isar2 = u;
1735
1736 u = cpu->isar.id_isar3;
1737 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1);
1738 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0);
1739 cpu->isar.id_isar3 = u;
1740 }
1741
1742
1743 if (arm_feature(env, ARM_FEATURE_V8)) {
1744 if (arm_feature(env, ARM_FEATURE_M)) {
1745 set_feature(env, ARM_FEATURE_V7);
1746 } else {
1747 set_feature(env, ARM_FEATURE_V7VE);
1748 }
1749 }
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1760 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
1761 }
1762
1763 if (arm_feature(env, ARM_FEATURE_V7VE)) {
1764
1765
1766
1767
1768
1769
1770
1771
1772 assert(!tcg_enabled() || no_aa32 ||
1773 cpu_isar_feature(aa32_arm_div, cpu));
1774 set_feature(env, ARM_FEATURE_LPAE);
1775 set_feature(env, ARM_FEATURE_V7);
1776 }
1777 if (arm_feature(env, ARM_FEATURE_V7)) {
1778 set_feature(env, ARM_FEATURE_VAPA);
1779 set_feature(env, ARM_FEATURE_THUMB2);
1780 set_feature(env, ARM_FEATURE_MPIDR);
1781 if (!arm_feature(env, ARM_FEATURE_M)) {
1782 set_feature(env, ARM_FEATURE_V6K);
1783 } else {
1784 set_feature(env, ARM_FEATURE_V6);
1785 }
1786
1787
1788
1789
1790 set_feature(env, ARM_FEATURE_VBAR);
1791 }
1792 if (arm_feature(env, ARM_FEATURE_V6K)) {
1793 set_feature(env, ARM_FEATURE_V6);
1794 set_feature(env, ARM_FEATURE_MVFR);
1795 }
1796 if (arm_feature(env, ARM_FEATURE_V6)) {
1797 set_feature(env, ARM_FEATURE_V5);
1798 if (!arm_feature(env, ARM_FEATURE_M)) {
1799 assert(!tcg_enabled() || no_aa32 ||
1800 cpu_isar_feature(aa32_jazelle, cpu));
1801 set_feature(env, ARM_FEATURE_AUXCR);
1802 }
1803 }
1804 if (arm_feature(env, ARM_FEATURE_V5)) {
1805 set_feature(env, ARM_FEATURE_V4T);
1806 }
1807 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1808 set_feature(env, ARM_FEATURE_V7MP);
1809 }
1810 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
1811 set_feature(env, ARM_FEATURE_CBAR);
1812 }
1813 if (arm_feature(env, ARM_FEATURE_THUMB2) &&
1814 !arm_feature(env, ARM_FEATURE_M)) {
1815 set_feature(env, ARM_FEATURE_THUMB_DSP);
1816 }
1817
1818
1819
1820
1821
1822 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) ||
1823 !cpu_isar_feature(aa32_vfp_simd, cpu) ||
1824 !arm_feature(env, ARM_FEATURE_XSCALE));
1825
1826 if (arm_feature(env, ARM_FEATURE_V7) &&
1827 !arm_feature(env, ARM_FEATURE_M) &&
1828 !arm_feature(env, ARM_FEATURE_PMSA)) {
1829
1830
1831
1832 pagebits = 12;
1833 } else {
1834
1835
1836
1837 pagebits = 10;
1838 }
1839 if (!set_preferred_target_page_bits(pagebits)) {
1840
1841
1842
1843
1844 error_setg(errp, "This CPU requires a smaller page size than the "
1845 "system is using");
1846 return;
1847 }
1848
1849
1850
1851
1852
1853
1854 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
1855 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index,
1856 ARM_DEFAULT_CPUS_PER_CLUSTER);
1857 }
1858
1859 if (cpu->reset_hivecs) {
1860 cpu->reset_sctlr |= (1 << 13);
1861 }
1862
1863 if (cpu->cfgend) {
1864 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1865 cpu->reset_sctlr |= SCTLR_EE;
1866 } else {
1867 cpu->reset_sctlr |= SCTLR_B;
1868 }
1869 }
1870
1871 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) {
1872
1873
1874
1875 unset_feature(env, ARM_FEATURE_EL3);
1876
1877
1878
1879
1880
1881 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
1882 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
1883 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
1884 ID_AA64PFR0, EL3, 0);
1885 }
1886
1887 if (!cpu->has_el2) {
1888 unset_feature(env, ARM_FEATURE_EL2);
1889 }
1890
1891 if (!cpu->has_pmu) {
1892 unset_feature(env, ARM_FEATURE_PMU);
1893 }
1894 if (arm_feature(env, ARM_FEATURE_PMU)) {
1895 pmu_init(cpu);
1896
1897 if (!kvm_enabled()) {
1898 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
1899 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
1900 }
1901
1902#ifndef CONFIG_USER_ONLY
1903 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb,
1904 cpu);
1905#endif
1906 } else {
1907 cpu->isar.id_aa64dfr0 =
1908 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
1909 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0);
1910 cpu->pmceid0 = 0;
1911 cpu->pmceid1 = 0;
1912 }
1913
1914 if (!arm_feature(env, ARM_FEATURE_EL2)) {
1915
1916
1917
1918
1919 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
1920 ID_AA64PFR0, EL2, 0);
1921 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
1922 ID_PFR1, VIRTUALIZATION, 0);
1923 }
1924
1925#ifndef CONFIG_USER_ONLY
1926 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {
1927
1928
1929
1930
1931 cpu->isar.id_aa64pfr1 =
1932 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
1933 }
1934#endif
1935
1936 if (tcg_enabled()) {
1937
1938
1939
1940
1941
1942
1943 cpu->isar.id_aa64dfr0 =
1944 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
1945 }
1946
1947
1948
1949
1950 if (!cpu->has_mpu) {
1951 cpu->pmsav7_dregion = 0;
1952 }
1953 if (cpu->pmsav7_dregion == 0) {
1954 cpu->has_mpu = false;
1955 }
1956
1957 if (arm_feature(env, ARM_FEATURE_PMSA) &&
1958 arm_feature(env, ARM_FEATURE_V7)) {
1959 uint32_t nr = cpu->pmsav7_dregion;
1960
1961 if (nr > 0xff) {
1962 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
1963 return;
1964 }
1965
1966 if (nr) {
1967 if (arm_feature(env, ARM_FEATURE_V8)) {
1968
1969 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
1970 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
1971 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1972 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
1973 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
1974 }
1975 } else {
1976 env->pmsav7.drbar = g_new0(uint32_t, nr);
1977 env->pmsav7.drsr = g_new0(uint32_t, nr);
1978 env->pmsav7.dracr = g_new0(uint32_t, nr);
1979 }
1980 }
1981 }
1982
1983 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1984 uint32_t nr = cpu->sau_sregion;
1985
1986 if (nr > 0xff) {
1987 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
1988 return;
1989 }
1990
1991 if (nr) {
1992 env->sau.rbar = g_new0(uint32_t, nr);
1993 env->sau.rlar = g_new0(uint32_t, nr);
1994 }
1995 }
1996
1997 if (arm_feature(env, ARM_FEATURE_EL3)) {
1998 set_feature(env, ARM_FEATURE_VBAR);
1999 }
2000
2001 register_cp_regs_for_features(cpu);
2002 arm_cpu_register_gdb_regs_for_features(cpu);
2003
2004 init_cpreg_list(cpu);
2005
2006#ifndef CONFIG_USER_ONLY
2007 MachineState *ms = MACHINE(qdev_get_machine());
2008 unsigned int smp_cpus = ms->smp.cpus;
2009 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY);
2010
2011
2012
2013
2014
2015 if (cpu->tag_memory != NULL) {
2016 cs->num_ases = 3 + has_secure;
2017 } else {
2018 cs->num_ases = 1 + has_secure;
2019 }
2020
2021 if (has_secure) {
2022 if (!cpu->secure_memory) {
2023 cpu->secure_memory = cs->memory;
2024 }
2025 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory",
2026 cpu->secure_memory);
2027 }
2028
2029 if (cpu->tag_memory != NULL) {
2030 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory",
2031 cpu->tag_memory);
2032 if (has_secure) {
2033 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory",
2034 cpu->secure_tag_memory);
2035 }
2036 }
2037
2038 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
2039
2040
2041 if (cpu->core_count == -1) {
2042 cpu->core_count = smp_cpus;
2043 }
2044#endif
2045
2046 if (tcg_enabled()) {
2047 int dcz_blocklen = 4 << cpu->dcz_blocksize;
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058 assert(dcz_blocklen <= TARGET_PAGE_SIZE);
2059
2060
2061
2062
2063
2064
2065 if (cpu_isar_feature(aa64_mte, cpu)) {
2066 assert(dcz_blocklen >= 2 * TAG_GRANULE);
2067 }
2068 }
2069
2070 qemu_init_vcpu(cs);
2071 cpu_reset(cs);
2072
2073 acc->parent_realize(dev, errp);
2074}
2075
2076static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
2077{
2078 ObjectClass *oc;
2079 char *typename;
2080 char **cpuname;
2081 const char *cpunamestr;
2082
2083 cpuname = g_strsplit(cpu_model, ",", 1);
2084 cpunamestr = cpuname[0];
2085#ifdef CONFIG_USER_ONLY
2086
2087
2088
2089 if (!strcmp(cpunamestr, "any")) {
2090 cpunamestr = "max";
2091 }
2092#endif
2093 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);
2094 oc = object_class_by_name(typename);
2095 g_strfreev(cpuname);
2096 g_free(typename);
2097 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
2098 object_class_is_abstract(oc)) {
2099 return NULL;
2100 }
2101 return oc;
2102}
2103
2104static Property arm_cpu_properties[] = {
2105 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0),
2106 DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
2107 mp_affinity, ARM64_AFFINITY_INVALID),
2108 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
2109 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
2110 DEFINE_PROP_END_OF_LIST()
2111};
2112
2113static gchar *arm_gdb_arch_name(CPUState *cs)
2114{
2115 ARMCPU *cpu = ARM_CPU(cs);
2116 CPUARMState *env = &cpu->env;
2117
2118 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
2119 return g_strdup("iwmmxt");
2120 }
2121 return g_strdup("arm");
2122}
2123
2124#ifndef CONFIG_USER_ONLY
2125#include "hw/core/sysemu-cpu-ops.h"
2126
2127static const struct SysemuCPUOps arm_sysemu_ops = {
2128 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug,
2129 .asidx_from_attrs = arm_asidx_from_attrs,
2130 .write_elf32_note = arm_cpu_write_elf32_note,
2131 .write_elf64_note = arm_cpu_write_elf64_note,
2132 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
2133 .legacy_vmsd = &vmstate_arm_cpu,
2134};
2135#endif
2136
2137#ifdef CONFIG_TCG
2138static const struct TCGCPUOps arm_tcg_ops = {
2139 .initialize = arm_translate_init,
2140 .synchronize_from_tb = arm_cpu_synchronize_from_tb,
2141 .debug_excp_handler = arm_debug_excp_handler,
2142
2143#ifdef CONFIG_USER_ONLY
2144 .record_sigsegv = arm_cpu_record_sigsegv,
2145 .record_sigbus = arm_cpu_record_sigbus,
2146#else
2147 .tlb_fill = arm_cpu_tlb_fill,
2148 .cpu_exec_interrupt = arm_cpu_exec_interrupt,
2149 .do_interrupt = arm_cpu_do_interrupt,
2150 .do_transaction_failed = arm_cpu_do_transaction_failed,
2151 .do_unaligned_access = arm_cpu_do_unaligned_access,
2152 .adjust_watchpoint_address = arm_adjust_watchpoint_address,
2153 .debug_check_watchpoint = arm_debug_check_watchpoint,
2154 .debug_check_breakpoint = arm_debug_check_breakpoint,
2155#endif
2156};
2157#endif
2158
2159static void arm_cpu_class_init(ObjectClass *oc, void *data)
2160{
2161 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2162 CPUClass *cc = CPU_CLASS(acc);
2163 DeviceClass *dc = DEVICE_CLASS(oc);
2164
2165 device_class_set_parent_realize(dc, arm_cpu_realizefn,
2166 &acc->parent_realize);
2167
2168 device_class_set_props(dc, arm_cpu_properties);
2169 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset);
2170
2171 cc->class_by_name = arm_cpu_class_by_name;
2172 cc->has_work = arm_cpu_has_work;
2173 cc->dump_state = arm_cpu_dump_state;
2174 cc->set_pc = arm_cpu_set_pc;
2175 cc->gdb_read_register = arm_cpu_gdb_read_register;
2176 cc->gdb_write_register = arm_cpu_gdb_write_register;
2177#ifndef CONFIG_USER_ONLY
2178 cc->sysemu_ops = &arm_sysemu_ops;
2179#endif
2180 cc->gdb_num_core_regs = 26;
2181 cc->gdb_core_xml_file = "arm-core.xml";
2182 cc->gdb_arch_name = arm_gdb_arch_name;
2183 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;
2184 cc->gdb_stop_before_watchpoint = true;
2185 cc->disas_set_info = arm_disas_set_info;
2186
2187#ifdef CONFIG_TCG
2188 cc->tcg_ops = &arm_tcg_ops;
2189#endif
2190}
2191
2192static void arm_cpu_instance_init(Object *obj)
2193{
2194 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
2195
2196 acc->info->initfn(obj);
2197 arm_cpu_post_init(obj);
2198}
2199
2200static void cpu_register_class_init(ObjectClass *oc, void *data)
2201{
2202 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2203
2204 acc->info = data;
2205}
2206
2207void arm_cpu_register(const ARMCPUInfo *info)
2208{
2209 TypeInfo type_info = {
2210 .parent = TYPE_ARM_CPU,
2211 .instance_size = sizeof(ARMCPU),
2212 .instance_align = __alignof__(ARMCPU),
2213 .instance_init = arm_cpu_instance_init,
2214 .class_size = sizeof(ARMCPUClass),
2215 .class_init = info->class_init ?: cpu_register_class_init,
2216 .class_data = (void *)info,
2217 };
2218
2219 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
2220 type_register(&type_info);
2221 g_free((void *)type_info.name);
2222}
2223
2224static const TypeInfo arm_cpu_type_info = {
2225 .name = TYPE_ARM_CPU,
2226 .parent = TYPE_CPU,
2227 .instance_size = sizeof(ARMCPU),
2228 .instance_align = __alignof__(ARMCPU),
2229 .instance_init = arm_cpu_initfn,
2230 .instance_finalize = arm_cpu_finalizefn,
2231 .abstract = true,
2232 .class_size = sizeof(ARMCPUClass),
2233 .class_init = arm_cpu_class_init,
2234};
2235
2236static void arm_cpu_register_types(void)
2237{
2238 type_register_static(&arm_cpu_type_info);
2239}
2240
2241type_init(arm_cpu_register_types)
2242