1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#ifndef ARM_CPU_H
21#define ARM_CPU_H
22
23#include "kvm-consts.h"
24#include "qemu/cpu-float.h"
25#include "hw/registerfields.h"
26#include "cpu-qom.h"
27#include "exec/cpu-defs.h"
28#include "qapi/qapi-types-common.h"
29
30
31#define TCG_GUEST_DEFAULT_MO (0)
32
33#ifdef TARGET_AARCH64
34#define KVM_HAVE_MCE_INJECTION 1
35#endif
36
37#define EXCP_UDEF 1
38#define EXCP_SWI 2
39#define EXCP_PREFETCH_ABORT 3
40#define EXCP_DATA_ABORT 4
41#define EXCP_IRQ 5
42#define EXCP_FIQ 6
43#define EXCP_BKPT 7
44#define EXCP_EXCEPTION_EXIT 8
45#define EXCP_KERNEL_TRAP 9
46#define EXCP_HVC 11
47#define EXCP_HYP_TRAP 12
48#define EXCP_SMC 13
49#define EXCP_VIRQ 14
50#define EXCP_VFIQ 15
51#define EXCP_SEMIHOST 16
52#define EXCP_NOCP 17
53#define EXCP_INVSTATE 18
54#define EXCP_STKOF 19
55#define EXCP_LAZYFP 20
56#define EXCP_LSERR 21
57#define EXCP_UNALIGNED 22
58#define EXCP_DIVBYZERO 23
59#define EXCP_VSERR 24
60
61
62#define ARMV7M_EXCP_RESET 1
63#define ARMV7M_EXCP_NMI 2
64#define ARMV7M_EXCP_HARD 3
65#define ARMV7M_EXCP_MEM 4
66#define ARMV7M_EXCP_BUS 5
67#define ARMV7M_EXCP_USAGE 6
68#define ARMV7M_EXCP_SECURE 7
69#define ARMV7M_EXCP_SVC 11
70#define ARMV7M_EXCP_DEBUG 12
71#define ARMV7M_EXCP_PENDSV 14
72#define ARMV7M_EXCP_SYSTICK 15
73
74
75
76
77
78
79
80
81
82
83enum {
84 M_REG_NS = 0,
85 M_REG_S = 1,
86 M_REG_NUM_BANKS = 2,
87};
88
89
90#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
91#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
92#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
93#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0
94
95
96
97
98
99
100
101#if HOST_BIG_ENDIAN
102#define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
103#define offsetofhigh32(S, M) offsetof(S, M)
104#else
105#define offsetoflow32(S, M) offsetof(S, M)
106#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
107#endif
108
109
110#define ARM_CPU_IRQ 0
111#define ARM_CPU_FIQ 1
112#define ARM_CPU_VIRQ 2
113#define ARM_CPU_VFIQ 3
114
115
116
117
118
119#define TARGET_INSN_START_EXTRA_WORDS 2
120
121
122
123
124
125
126#define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
127#define ARM_INSN_START_WORD2_SHIFT 14
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146typedef struct DynamicGDBXMLInfo {
147 char *desc;
148 int num;
149 union {
150 struct {
151 uint32_t *keys;
152 } cpregs;
153 } data;
154} DynamicGDBXMLInfo;
155
156
157typedef struct ARMGenericTimer {
158 uint64_t cval;
159 uint64_t ctl;
160} ARMGenericTimer;
161
162#define GTIMER_PHYS 0
163#define GTIMER_VIRT 1
164#define GTIMER_HYP 2
165#define GTIMER_SEC 3
166#define GTIMER_HYPVIRT 4
167#define NUM_GTIMERS 5
168
169#define VTCR_NSW (1u << 29)
170#define VTCR_NSA (1u << 30)
171#define VSTCR_SW VTCR_NSW
172#define VSTCR_SA VTCR_NSA
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200#ifdef TARGET_AARCH64
201# define ARM_MAX_VQ 16
202#else
203# define ARM_MAX_VQ 1
204#endif
205
206typedef struct ARMVectorReg {
207 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
208} ARMVectorReg;
209
210#ifdef TARGET_AARCH64
211
212typedef struct ARMPredicateReg {
213 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
214} ARMPredicateReg;
215
216
217typedef struct ARMPACKey {
218 uint64_t lo, hi;
219} ARMPACKey;
220#endif
221
222
223typedef struct CPUARMTBFlags {
224 uint32_t flags;
225 target_ulong flags2;
226} CPUARMTBFlags;
227
228typedef struct CPUArchState {
229
230 uint32_t regs[16];
231
232
233
234
235
236
237 uint64_t xregs[32];
238 uint64_t pc;
239
240
241
242
243
244
245
246
247
248
249
250
251
252 uint32_t pstate;
253 bool aarch64;
254 bool thumb;
255
256
257 CPUARMTBFlags hflags;
258
259
260
261
262 uint32_t uncached_cpsr;
263 uint32_t spsr;
264
265
266 uint64_t banked_spsr[8];
267 uint32_t banked_r13[8];
268 uint32_t banked_r14[8];
269
270
271 uint32_t usr_regs[5];
272 uint32_t fiq_regs[5];
273
274
275 uint32_t CF;
276 uint32_t VF;
277 uint32_t NF;
278 uint32_t ZF;
279 uint32_t QF;
280 uint32_t GE;
281 uint32_t condexec_bits;
282 uint32_t btype;
283 uint64_t daif;
284 uint64_t svcr;
285
286 uint64_t elr_el[4];
287 uint64_t sp_el[4];
288
289
290 struct {
291 uint32_t c0_cpuid;
292 union {
293 struct {
294 uint64_t _unused_csselr0;
295 uint64_t csselr_ns;
296 uint64_t _unused_csselr1;
297 uint64_t csselr_s;
298 };
299 uint64_t csselr_el[4];
300 };
301 union {
302 struct {
303 uint64_t _unused_sctlr;
304 uint64_t sctlr_ns;
305 uint64_t hsctlr;
306 uint64_t sctlr_s;
307 };
308 uint64_t sctlr_el[4];
309 };
310 uint64_t cpacr_el1;
311 uint64_t cptr_el[4];
312 uint32_t c1_xscaleauxcr;
313 uint64_t sder;
314 uint32_t nsacr;
315 union {
316 struct {
317 uint64_t _unused_ttbr0_0;
318 uint64_t ttbr0_ns;
319 uint64_t _unused_ttbr0_1;
320 uint64_t ttbr0_s;
321 };
322 uint64_t ttbr0_el[4];
323 };
324 union {
325 struct {
326 uint64_t _unused_ttbr1_0;
327 uint64_t ttbr1_ns;
328 uint64_t _unused_ttbr1_1;
329 uint64_t ttbr1_s;
330 };
331 uint64_t ttbr1_el[4];
332 };
333 uint64_t vttbr_el2;
334 uint64_t vsttbr_el2;
335
336 uint64_t tcr_el[4];
337 uint64_t vtcr_el2;
338 uint64_t vstcr_el2;
339 uint32_t c2_data;
340 uint32_t c2_insn;
341 union {
342
343
344 struct {
345 uint64_t dacr_ns;
346 uint64_t dacr_s;
347 };
348 struct {
349 uint64_t dacr32_el2;
350 };
351 };
352 uint32_t pmsav5_data_ap;
353 uint32_t pmsav5_insn_ap;
354 uint64_t hcr_el2;
355 uint64_t hcrx_el2;
356 uint64_t scr_el3;
357 union {
358 struct {
359 uint64_t ifsr_ns;
360 uint64_t ifsr_s;
361 };
362 struct {
363 uint64_t ifsr32_el2;
364 };
365 };
366 union {
367 struct {
368 uint64_t _unused_dfsr;
369 uint64_t dfsr_ns;
370 uint64_t hsr;
371 uint64_t dfsr_s;
372 };
373 uint64_t esr_el[4];
374 };
375 uint32_t c6_region[8];
376 union {
377 struct {
378 uint64_t _unused_far0;
379#if HOST_BIG_ENDIAN
380 uint32_t ifar_ns;
381 uint32_t dfar_ns;
382 uint32_t ifar_s;
383 uint32_t dfar_s;
384#else
385 uint32_t dfar_ns;
386 uint32_t ifar_ns;
387 uint32_t dfar_s;
388 uint32_t ifar_s;
389#endif
390 uint64_t _unused_far3;
391 };
392 uint64_t far_el[4];
393 };
394 uint64_t hpfar_el2;
395 uint64_t hstr_el2;
396 union {
397 struct {
398 uint64_t _unused_par_0;
399 uint64_t par_ns;
400 uint64_t _unused_par_1;
401 uint64_t par_s;
402 };
403 uint64_t par_el[4];
404 };
405
406 uint32_t c9_insn;
407 uint32_t c9_data;
408 uint64_t c9_pmcr;
409 uint64_t c9_pmcnten;
410 uint64_t c9_pmovsr;
411 uint64_t c9_pmuserenr;
412 uint64_t c9_pmselr;
413 uint64_t c9_pminten;
414 union {
415 struct {
416#if HOST_BIG_ENDIAN
417 uint64_t _unused_mair_0;
418 uint32_t mair1_ns;
419 uint32_t mair0_ns;
420 uint64_t _unused_mair_1;
421 uint32_t mair1_s;
422 uint32_t mair0_s;
423#else
424 uint64_t _unused_mair_0;
425 uint32_t mair0_ns;
426 uint32_t mair1_ns;
427 uint64_t _unused_mair_1;
428 uint32_t mair0_s;
429 uint32_t mair1_s;
430#endif
431 };
432 uint64_t mair_el[4];
433 };
434 union {
435 struct {
436 uint64_t _unused_vbar;
437 uint64_t vbar_ns;
438 uint64_t hvbar;
439 uint64_t vbar_s;
440 };
441 uint64_t vbar_el[4];
442 };
443 uint32_t mvbar;
444 uint64_t rvbar;
445 struct {
446 uint32_t fcseidr_ns;
447 uint32_t fcseidr_s;
448 };
449 union {
450 struct {
451 uint64_t _unused_contextidr_0;
452 uint64_t contextidr_ns;
453 uint64_t _unused_contextidr_1;
454 uint64_t contextidr_s;
455 };
456 uint64_t contextidr_el[4];
457 };
458 union {
459 struct {
460 uint64_t tpidrurw_ns;
461 uint64_t tpidrprw_ns;
462 uint64_t htpidr;
463 uint64_t _tpidr_el3;
464 };
465 uint64_t tpidr_el[4];
466 };
467 uint64_t tpidr2_el0;
468
469 uint64_t tpidrurw_s;
470 uint64_t tpidrprw_s;
471 uint64_t tpidruro_s;
472
473 union {
474 uint64_t tpidruro_ns;
475 uint64_t tpidrro_el[1];
476 };
477 uint64_t c14_cntfrq;
478 uint64_t c14_cntkctl;
479 uint32_t cnthctl_el2;
480 uint64_t cntvoff_el2;
481 ARMGenericTimer c14_timer[NUM_GTIMERS];
482 uint32_t c15_cpar;
483 uint32_t c15_ticonfig;
484 uint32_t c15_i_max;
485 uint32_t c15_i_min;
486 uint32_t c15_threadid;
487 uint32_t c15_config_base_address;
488 uint32_t c15_diagnostic;
489 uint32_t c15_power_diagnostic;
490 uint32_t c15_power_control;
491 uint64_t dbgbvr[16];
492 uint64_t dbgbcr[16];
493 uint64_t dbgwvr[16];
494 uint64_t dbgwcr[16];
495 uint64_t mdscr_el1;
496 uint64_t oslsr_el1;
497 uint64_t osdlr_el1;
498 uint64_t mdcr_el2;
499 uint64_t mdcr_el3;
500
501
502
503
504
505 uint64_t c15_ccnt;
506
507
508
509
510
511
512
513 uint64_t c15_ccnt_delta;
514 uint64_t c14_pmevcntr[31];
515 uint64_t c14_pmevcntr_delta[31];
516 uint64_t c14_pmevtyper[31];
517 uint64_t pmccfiltr_el0;
518 uint64_t vpidr_el2;
519 uint64_t vmpidr_el2;
520 uint64_t tfsr_el[4];
521 uint64_t gcr_el1;
522 uint64_t rgsr_el1;
523
524
525 uint64_t disr_el1;
526 uint64_t vdisr_el2;
527 uint64_t vsesr_el2;
528 } cp15;
529
530 struct {
531
532
533
534
535
536
537
538
539
540
541
542 uint32_t other_sp;
543 uint32_t other_ss_msp;
544 uint32_t other_ss_psp;
545 uint32_t vecbase[M_REG_NUM_BANKS];
546 uint32_t basepri[M_REG_NUM_BANKS];
547 uint32_t control[M_REG_NUM_BANKS];
548 uint32_t ccr[M_REG_NUM_BANKS];
549 uint32_t cfsr[M_REG_NUM_BANKS];
550 uint32_t hfsr;
551 uint32_t dfsr;
552 uint32_t sfsr;
553 uint32_t mmfar[M_REG_NUM_BANKS];
554 uint32_t bfar;
555 uint32_t sfar;
556 unsigned mpu_ctrl[M_REG_NUM_BANKS];
557 int exception;
558 uint32_t primask[M_REG_NUM_BANKS];
559 uint32_t faultmask[M_REG_NUM_BANKS];
560 uint32_t aircr;
561 uint32_t secure;
562 uint32_t csselr[M_REG_NUM_BANKS];
563 uint32_t scr[M_REG_NUM_BANKS];
564 uint32_t msplim[M_REG_NUM_BANKS];
565 uint32_t psplim[M_REG_NUM_BANKS];
566 uint32_t fpcar[M_REG_NUM_BANKS];
567 uint32_t fpccr[M_REG_NUM_BANKS];
568 uint32_t fpdscr[M_REG_NUM_BANKS];
569 uint32_t cpacr[M_REG_NUM_BANKS];
570 uint32_t nsacr;
571 uint32_t ltpsize;
572 uint32_t vpr;
573 } v7m;
574
575
576
577
578
579
580
581 struct {
582 uint32_t syndrome;
583 uint32_t fsr;
584 uint64_t vaddress;
585 uint32_t target_el;
586
587
588
589 } exception;
590
591
592 struct {
593 uint8_t pending;
594 uint8_t has_esr;
595 uint64_t esr;
596 } serror;
597
598 uint8_t ext_dabt_raised;
599
600
601 uint32_t irq_line_state;
602
603
604 uint32_t teecr;
605 uint32_t teehbr;
606
607
608 struct {
609 ARMVectorReg zregs[32];
610
611#ifdef TARGET_AARCH64
612
613#define FFR_PRED_NUM 16
614 ARMPredicateReg pregs[17];
615
616 ARMPredicateReg preg_tmp;
617#endif
618
619
620 uint32_t qc[4] QEMU_ALIGNED(16);
621 int vec_len;
622 int vec_stride;
623
624 uint32_t xregs[16];
625
626
627 uint32_t scratch[8];
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656 float_status fp_status;
657 float_status fp_status_f16;
658 float_status standard_fp_status;
659 float_status standard_fp_status_f16;
660
661 uint64_t zcr_el[4];
662 uint64_t smcr_el[4];
663 } vfp;
664 uint64_t exclusive_addr;
665 uint64_t exclusive_val;
666 uint64_t exclusive_high;
667
668
669 struct {
670 uint64_t regs[16];
671 uint64_t val;
672
673 uint32_t cregs[16];
674 } iwmmxt;
675
676#ifdef TARGET_AARCH64
677 struct {
678 ARMPACKey apia;
679 ARMPACKey apib;
680 ARMPACKey apda;
681 ARMPACKey apdb;
682 ARMPACKey apga;
683 } keys;
684
685 uint64_t scxtnum_el[4];
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707 ARMVectorReg zarray[ARM_MAX_VQ * 16];
708#endif
709
710#if defined(CONFIG_USER_ONLY)
711
712 int eabi;
713#endif
714
715 struct CPUBreakpoint *cpu_breakpoint[16];
716 struct CPUWatchpoint *cpu_watchpoint[16];
717
718
719 struct {} end_reset_fields;
720
721
722
723
724 uint64_t features;
725
726
727 struct {
728 uint32_t *drbar;
729 uint32_t *drsr;
730 uint32_t *dracr;
731 uint32_t rnr[M_REG_NUM_BANKS];
732 } pmsav7;
733
734
735 struct {
736
737
738
739
740
741 uint32_t *rbar[M_REG_NUM_BANKS];
742 uint32_t *rlar[M_REG_NUM_BANKS];
743 uint32_t mair0[M_REG_NUM_BANKS];
744 uint32_t mair1[M_REG_NUM_BANKS];
745 } pmsav8;
746
747
748 struct {
749 uint32_t *rbar;
750 uint32_t *rlar;
751 uint32_t rnr;
752 uint32_t ctrl;
753 } sau;
754
755 void *nvic;
756 const struct arm_boot_info *boot_info;
757
758 void *gicv3state;
759
760#ifdef TARGET_TAGGED_ADDRESSES
761
762 bool tagged_addr_enable;
763#endif
764} CPUARMState;
765
766static inline void set_feature(CPUARMState *env, int feature)
767{
768 env->features |= 1ULL << feature;
769}
770
771static inline void unset_feature(CPUARMState *env, int feature)
772{
773 env->features &= ~(1ULL << feature);
774}
775
776
777
778
779
780
781typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
782typedef struct ARMELChangeHook ARMELChangeHook;
783struct ARMELChangeHook {
784 ARMELChangeHookFn *hook;
785 void *opaque;
786 QLIST_ENTRY(ARMELChangeHook) node;
787};
788
789
790
791typedef enum ARMPSCIState {
792 PSCI_ON = 0,
793 PSCI_OFF = 1,
794 PSCI_ON_PENDING = 2
795} ARMPSCIState;
796
797typedef struct ARMISARegisters ARMISARegisters;
798
799
800
801
802
803
804
805
806
807
808typedef struct {
809 uint32_t map, init, supported;
810} ARMVQMap;
811
812
813
814
815
816
817
818struct ArchCPU {
819
820 CPUState parent_obj;
821
822
823 CPUNegativeOffsetState neg;
824 CPUARMState env;
825
826
827 GHashTable *cp_regs;
828
829
830
831
832
833
834
835 uint64_t *cpreg_indexes;
836
837 uint64_t *cpreg_values;
838
839 int32_t cpreg_array_len;
840
841
842
843
844 uint64_t *cpreg_vmstate_indexes;
845 uint64_t *cpreg_vmstate_values;
846 int32_t cpreg_vmstate_array_len;
847
848 DynamicGDBXMLInfo dyn_sysreg_xml;
849 DynamicGDBXMLInfo dyn_svereg_xml;
850
851
852 QEMUTimer *gt_timer[NUM_GTIMERS];
853
854
855
856
857 QEMUTimer *pmu_timer;
858
859 qemu_irq gt_timer_outputs[NUM_GTIMERS];
860
861 qemu_irq gicv3_maintenance_interrupt;
862
863 qemu_irq pmu_interrupt;
864
865
866 MemoryRegion *secure_memory;
867
868
869 MemoryRegion *tag_memory;
870 MemoryRegion *secure_tag_memory;
871
872
873 Object *idau;
874
875
876 const char *dtb_compatible;
877
878
879
880
881
882 uint32_t psci_version;
883
884
885 ARMPSCIState power_state;
886
887
888 bool has_el2;
889
890 bool has_el3;
891
892 bool has_pmu;
893
894 bool has_vfp;
895
896 bool has_neon;
897
898 bool has_dsp;
899
900
901 bool has_mpu;
902
903 uint32_t pmsav7_dregion;
904
905 uint32_t sau_sregion;
906
907
908
909
910 uint32_t psci_conduit;
911
912
913 uint32_t init_svtor;
914
915 uint32_t init_nsvtor;
916
917
918
919
920 uint32_t kvm_target;
921
922
923 uint32_t kvm_init_features[7];
924
925
926
927
928 bool kvm_adjvtime;
929 bool kvm_vtime_dirty;
930 uint64_t kvm_vtime;
931
932
933 OnOffAuto kvm_steal_time;
934
935
936 bool mp_is_up;
937
938
939
940
941 bool host_cpu_probe_failed;
942
943
944
945
946 int32_t core_count;
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965 struct ARMISARegisters {
966 uint32_t id_isar0;
967 uint32_t id_isar1;
968 uint32_t id_isar2;
969 uint32_t id_isar3;
970 uint32_t id_isar4;
971 uint32_t id_isar5;
972 uint32_t id_isar6;
973 uint32_t id_mmfr0;
974 uint32_t id_mmfr1;
975 uint32_t id_mmfr2;
976 uint32_t id_mmfr3;
977 uint32_t id_mmfr4;
978 uint32_t id_pfr0;
979 uint32_t id_pfr1;
980 uint32_t id_pfr2;
981 uint32_t mvfr0;
982 uint32_t mvfr1;
983 uint32_t mvfr2;
984 uint32_t id_dfr0;
985 uint32_t dbgdidr;
986 uint32_t dbgdevid;
987 uint32_t dbgdevid1;
988 uint64_t id_aa64isar0;
989 uint64_t id_aa64isar1;
990 uint64_t id_aa64pfr0;
991 uint64_t id_aa64pfr1;
992 uint64_t id_aa64mmfr0;
993 uint64_t id_aa64mmfr1;
994 uint64_t id_aa64mmfr2;
995 uint64_t id_aa64dfr0;
996 uint64_t id_aa64dfr1;
997 uint64_t id_aa64zfr0;
998 uint64_t id_aa64smfr0;
999 uint64_t reset_pmcr_el0;
1000 } isar;
1001 uint64_t midr;
1002 uint32_t revidr;
1003 uint32_t reset_fpsid;
1004 uint64_t ctr;
1005 uint32_t reset_sctlr;
1006 uint64_t pmceid0;
1007 uint64_t pmceid1;
1008 uint32_t id_afr0;
1009 uint64_t id_aa64afr0;
1010 uint64_t id_aa64afr1;
1011 uint64_t clidr;
1012 uint64_t mp_affinity;
1013
1014
1015
1016 uint64_t ccsidr[16];
1017 uint64_t reset_cbar;
1018 uint32_t reset_auxcr;
1019 bool reset_hivecs;
1020
1021
1022
1023
1024
1025 bool prop_pauth;
1026 bool prop_pauth_impdef;
1027 bool prop_lpa2;
1028
1029
1030 uint32_t dcz_blocksize;
1031 uint64_t rvbar_prop;
1032
1033
1034 int gic_num_lrs;
1035 int gic_vpribits;
1036 int gic_vprebits;
1037 int gic_pribits;
1038
1039
1040
1041
1042
1043
1044 bool cfgend;
1045
1046 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
1047 QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
1048
1049 int32_t node_id;
1050
1051
1052 uint8_t device_irq_level;
1053
1054
1055 uint32_t sve_max_vq;
1056
1057#ifdef CONFIG_USER_ONLY
1058
1059 uint32_t sve_default_vq;
1060 uint32_t sme_default_vq;
1061#endif
1062
1063 ARMVQMap sve_vq;
1064 ARMVQMap sme_vq;
1065
1066
1067 uint64_t gt_cntfrq_hz;
1068};
1069
1070unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
1071
1072void arm_cpu_post_init(Object *obj);
1073
1074uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
1075
1076#ifndef CONFIG_USER_ONLY
1077extern const VMStateDescription vmstate_arm_cpu;
1078
1079void arm_cpu_do_interrupt(CPUState *cpu);
1080void arm_v7m_cpu_do_interrupt(CPUState *cpu);
1081#endif
1082
1083hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
1084 MemTxAttrs *attrs);
1085
1086int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1087int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1088
1089
1090
1091
1092
1093int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
1094int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
1095
1096
1097
1098
1099
1100const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname);
1101
1102int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1103 int cpuid, void *opaque);
1104int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1105 int cpuid, void *opaque);
1106
1107#ifdef TARGET_AARCH64
1108int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1109int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1110void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
1111void aarch64_sve_change_el(CPUARMState *env, int old_el,
1112 int new_el, bool el0_a64);
1113void arm_reset_sve_state(CPUARMState *env);
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
1125{
1126#if HOST_BIG_ENDIAN
1127 int i;
1128
1129 for (i = 0; i < nr; ++i) {
1130 dst[i] = bswap64(src[i]);
1131 }
1132
1133 return dst;
1134#else
1135 return src;
1136#endif
1137}
1138
1139#else
1140static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
1141static inline void aarch64_sve_change_el(CPUARMState *env, int o,
1142 int n, bool a)
1143{ }
1144#endif
1145
1146void aarch64_sync_32_to_64(CPUARMState *env);
1147void aarch64_sync_64_to_32(CPUARMState *env);
1148
1149int fp_exception_el(CPUARMState *env, int cur_el);
1150int sve_exception_el(CPUARMState *env, int cur_el);
1151int sme_exception_el(CPUARMState *env, int cur_el);
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm);
1164
1165
1166uint32_t sve_vqm1_for_el(CPUARMState *env, int el);
1167
1168static inline bool is_a64(CPUARMState *env)
1169{
1170 return env->aarch64;
1171}
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181void pmu_op_start(CPUARMState *env);
1182void pmu_op_finish(CPUARMState *env);
1183
1184
1185
1186
1187void arm_pmu_timer_cb(void *opaque);
1188
1189
1190
1191
1192void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
1193void pmu_post_el_change(ARMCPU *cpu, void *ignored);
1194
1195
1196
1197
1198
1199
1200
1201
1202void pmu_init(ARMCPU *cpu);
1203
1204
1205
1206
1207
1208
1209
1210#define SCTLR_M (1U << 0)
1211#define SCTLR_A (1U << 1)
1212#define SCTLR_C (1U << 2)
1213#define SCTLR_W (1U << 3)
1214#define SCTLR_nTLSMD_32 (1U << 3)
1215#define SCTLR_SA (1U << 3)
1216#define SCTLR_P (1U << 4)
1217#define SCTLR_LSMAOE_32 (1U << 4)
1218#define SCTLR_SA0 (1U << 4)
1219#define SCTLR_D (1U << 5)
1220#define SCTLR_CP15BEN (1U << 5)
1221#define SCTLR_L (1U << 6)
1222#define SCTLR_nAA (1U << 6)
1223#define SCTLR_B (1U << 7)
1224#define SCTLR_ITD (1U << 7)
1225#define SCTLR_S (1U << 8)
1226#define SCTLR_SED (1U << 8)
1227#define SCTLR_R (1U << 9)
1228#define SCTLR_UMA (1U << 9)
1229#define SCTLR_F (1U << 10)
1230#define SCTLR_SW (1U << 10)
1231#define SCTLR_EnRCTX (1U << 10)
1232#define SCTLR_Z (1U << 11)
1233#define SCTLR_EOS (1U << 11)
1234#define SCTLR_I (1U << 12)
1235#define SCTLR_V (1U << 13)
1236#define SCTLR_EnDB (1U << 13)
1237#define SCTLR_RR (1U << 14)
1238#define SCTLR_DZE (1U << 14)
1239#define SCTLR_L4 (1U << 15)
1240#define SCTLR_UCT (1U << 15)
1241#define SCTLR_DT (1U << 16)
1242#define SCTLR_nTWI (1U << 16)
1243#define SCTLR_HA (1U << 17)
1244#define SCTLR_BR (1U << 17)
1245#define SCTLR_IT (1U << 18)
1246#define SCTLR_nTWE (1U << 18)
1247#define SCTLR_WXN (1U << 19)
1248#define SCTLR_ST (1U << 20)
1249#define SCTLR_UWXN (1U << 20)
1250#define SCTLR_TSCXT (1U << 20)
1251#define SCTLR_FI (1U << 21)
1252#define SCTLR_IESB (1U << 21)
1253#define SCTLR_U (1U << 22)
1254#define SCTLR_EIS (1U << 22)
1255#define SCTLR_XP (1U << 23)
1256#define SCTLR_SPAN (1U << 23)
1257#define SCTLR_VE (1U << 24)
1258#define SCTLR_E0E (1U << 24)
1259#define SCTLR_EE (1U << 25)
1260#define SCTLR_L2 (1U << 26)
1261#define SCTLR_UCI (1U << 26)
1262#define SCTLR_NMFI (1U << 27)
1263#define SCTLR_EnDA (1U << 27)
1264#define SCTLR_TRE (1U << 28)
1265#define SCTLR_nTLSMD_64 (1U << 28)
1266#define SCTLR_AFE (1U << 29)
1267#define SCTLR_LSMAOE_64 (1U << 29)
1268#define SCTLR_TE (1U << 30)
1269#define SCTLR_EnIB (1U << 30)
1270#define SCTLR_EnIA (1U << 31)
1271#define SCTLR_DSSBS_32 (1U << 31)
1272#define SCTLR_BT0 (1ULL << 35)
1273#define SCTLR_BT1 (1ULL << 36)
1274#define SCTLR_ITFSB (1ULL << 37)
1275#define SCTLR_TCF0 (3ULL << 38)
1276#define SCTLR_TCF (3ULL << 40)
1277#define SCTLR_ATA0 (1ULL << 42)
1278#define SCTLR_ATA (1ULL << 43)
1279#define SCTLR_DSSBS_64 (1ULL << 44)
1280#define SCTLR_TWEDEn (1ULL << 45)
1281#define SCTLR_TWEDEL MAKE_64_MASK(46, 4)
1282#define SCTLR_TMT0 (1ULL << 50)
1283#define SCTLR_TMT (1ULL << 51)
1284#define SCTLR_TME0 (1ULL << 52)
1285#define SCTLR_TME (1ULL << 53)
1286#define SCTLR_EnASR (1ULL << 54)
1287#define SCTLR_EnAS0 (1ULL << 55)
1288#define SCTLR_EnALS (1ULL << 56)
1289#define SCTLR_EPAN (1ULL << 57)
1290#define SCTLR_EnTP2 (1ULL << 60)
1291#define SCTLR_NMI (1ULL << 61)
1292#define SCTLR_SPINTMASK (1ULL << 62)
1293#define SCTLR_TIDCP (1ULL << 63)
1294
1295
1296FIELD(CPACR, CP10, 20, 2)
1297FIELD(CPACR, CP11, 22, 2)
1298FIELD(CPACR, TRCDIS, 28, 1)
1299FIELD(CPACR, D32DIS, 30, 1)
1300FIELD(CPACR, ASEDIS, 31, 1)
1301
1302
1303FIELD(CPACR_EL1, ZEN, 16, 2)
1304FIELD(CPACR_EL1, FPEN, 20, 2)
1305FIELD(CPACR_EL1, SMEN, 24, 2)
1306FIELD(CPACR_EL1, TTA, 28, 1)
1307
1308
1309FIELD(HCPTR, TCP10, 10, 1)
1310FIELD(HCPTR, TCP11, 11, 1)
1311FIELD(HCPTR, TASE, 15, 1)
1312FIELD(HCPTR, TTA, 20, 1)
1313FIELD(HCPTR, TAM, 30, 1)
1314FIELD(HCPTR, TCPAC, 31, 1)
1315
1316
1317FIELD(CPTR_EL2, TZ, 8, 1)
1318FIELD(CPTR_EL2, TFP, 10, 1)
1319FIELD(CPTR_EL2, TSM, 12, 1)
1320FIELD(CPTR_EL2, ZEN, 16, 2)
1321FIELD(CPTR_EL2, FPEN, 20, 2)
1322FIELD(CPTR_EL2, SMEN, 24, 2)
1323FIELD(CPTR_EL2, TTA, 28, 1)
1324FIELD(CPTR_EL2, TAM, 30, 1)
1325FIELD(CPTR_EL2, TCPAC, 31, 1)
1326
1327
1328FIELD(CPTR_EL3, EZ, 8, 1)
1329FIELD(CPTR_EL3, TFP, 10, 1)
1330FIELD(CPTR_EL3, ESM, 12, 1)
1331FIELD(CPTR_EL3, TTA, 20, 1)
1332FIELD(CPTR_EL3, TAM, 30, 1)
1333FIELD(CPTR_EL3, TCPAC, 31, 1)
1334
1335#define MDCR_EPMAD (1U << 21)
1336#define MDCR_EDAD (1U << 20)
1337#define MDCR_SPME (1U << 17)
1338#define MDCR_HPMD (1U << 17)
1339#define MDCR_SDD (1U << 16)
1340#define MDCR_SPD (3U << 14)
1341#define MDCR_TDRA (1U << 11)
1342#define MDCR_TDOSA (1U << 10)
1343#define MDCR_TDA (1U << 9)
1344#define MDCR_TDE (1U << 8)
1345#define MDCR_HPME (1U << 7)
1346#define MDCR_TPM (1U << 6)
1347#define MDCR_TPMCR (1U << 5)
1348#define MDCR_HPMN (0x1fU)
1349
1350
1351#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
1352
1353#define CPSR_M (0x1fU)
1354#define CPSR_T (1U << 5)
1355#define CPSR_F (1U << 6)
1356#define CPSR_I (1U << 7)
1357#define CPSR_A (1U << 8)
1358#define CPSR_E (1U << 9)
1359#define CPSR_IT_2_7 (0xfc00U)
1360#define CPSR_GE (0xfU << 16)
1361#define CPSR_IL (1U << 20)
1362#define CPSR_DIT (1U << 21)
1363#define CPSR_PAN (1U << 22)
1364#define CPSR_SSBS (1U << 23)
1365#define CPSR_J (1U << 24)
1366#define CPSR_IT_0_1 (3U << 25)
1367#define CPSR_Q (1U << 27)
1368#define CPSR_V (1U << 28)
1369#define CPSR_C (1U << 29)
1370#define CPSR_Z (1U << 30)
1371#define CPSR_N (1U << 31)
1372#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1373#define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
1374
1375#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1376#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1377 | CPSR_NZCV)
1378
1379#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
1380
1381#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
1382
1383
1384#define XPSR_EXCP 0x1ffU
1385#define XPSR_SPREALIGN (1U << 9)
1386#define XPSR_IT_2_7 CPSR_IT_2_7
1387#define XPSR_GE CPSR_GE
1388#define XPSR_SFPA (1U << 20)
1389#define XPSR_T (1U << 24)
1390#define XPSR_IT_0_1 CPSR_IT_0_1
1391#define XPSR_Q CPSR_Q
1392#define XPSR_V CPSR_V
1393#define XPSR_C CPSR_C
1394#define XPSR_Z CPSR_Z
1395#define XPSR_N CPSR_N
1396#define XPSR_NZCV CPSR_NZCV
1397#define XPSR_IT CPSR_IT
1398
1399#define TTBCR_N (7U << 0)
1400#define TTBCR_T0SZ (7U << 0)
1401#define TTBCR_PD0 (1U << 4)
1402#define TTBCR_PD1 (1U << 5)
1403#define TTBCR_EPD0 (1U << 7)
1404#define TTBCR_IRGN0 (3U << 8)
1405#define TTBCR_ORGN0 (3U << 10)
1406#define TTBCR_SH0 (3U << 12)
1407#define TTBCR_T1SZ (3U << 16)
1408#define TTBCR_A1 (1U << 22)
1409#define TTBCR_EPD1 (1U << 23)
1410#define TTBCR_IRGN1 (3U << 24)
1411#define TTBCR_ORGN1 (3U << 26)
1412#define TTBCR_SH1 (1U << 28)
1413#define TTBCR_EAE (1U << 31)
1414
1415FIELD(VTCR, T0SZ, 0, 6)
1416FIELD(VTCR, SL0, 6, 2)
1417FIELD(VTCR, IRGN0, 8, 2)
1418FIELD(VTCR, ORGN0, 10, 2)
1419FIELD(VTCR, SH0, 12, 2)
1420FIELD(VTCR, TG0, 14, 2)
1421FIELD(VTCR, PS, 16, 3)
1422FIELD(VTCR, VS, 19, 1)
1423FIELD(VTCR, HA, 21, 1)
1424FIELD(VTCR, HD, 22, 1)
1425FIELD(VTCR, HWU59, 25, 1)
1426FIELD(VTCR, HWU60, 26, 1)
1427FIELD(VTCR, HWU61, 27, 1)
1428FIELD(VTCR, HWU62, 28, 1)
1429FIELD(VTCR, NSW, 29, 1)
1430FIELD(VTCR, NSA, 30, 1)
1431FIELD(VTCR, DS, 32, 1)
1432FIELD(VTCR, SL2, 33, 1)
1433
1434
1435
1436
1437
1438#define PSTATE_SP (1U)
1439#define PSTATE_M (0xFU)
1440#define PSTATE_nRW (1U << 4)
1441#define PSTATE_F (1U << 6)
1442#define PSTATE_I (1U << 7)
1443#define PSTATE_A (1U << 8)
1444#define PSTATE_D (1U << 9)
1445#define PSTATE_BTYPE (3U << 10)
1446#define PSTATE_SSBS (1U << 12)
1447#define PSTATE_IL (1U << 20)
1448#define PSTATE_SS (1U << 21)
1449#define PSTATE_PAN (1U << 22)
1450#define PSTATE_UAO (1U << 23)
1451#define PSTATE_DIT (1U << 24)
1452#define PSTATE_TCO (1U << 25)
1453#define PSTATE_V (1U << 28)
1454#define PSTATE_C (1U << 29)
1455#define PSTATE_Z (1U << 30)
1456#define PSTATE_N (1U << 31)
1457#define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1458#define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1459#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE)
1460
1461#define PSTATE_MODE_EL3h 13
1462#define PSTATE_MODE_EL3t 12
1463#define PSTATE_MODE_EL2h 9
1464#define PSTATE_MODE_EL2t 8
1465#define PSTATE_MODE_EL1h 5
1466#define PSTATE_MODE_EL1t 4
1467#define PSTATE_MODE_EL0t 0
1468
1469
1470FIELD(SVCR, SM, 0, 1)
1471FIELD(SVCR, ZA, 1, 1)
1472
1473
1474FIELD(SMCR, LEN, 0, 4)
1475FIELD(SMCR, FA64, 31, 1)
1476
1477
1478
1479
1480void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1481
1482
1483static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1484{
1485 return (el << 2) | handler;
1486}
1487
1488
1489
1490
1491
1492static inline uint32_t pstate_read(CPUARMState *env)
1493{
1494 int ZF;
1495
1496 ZF = (env->ZF == 0);
1497 return (env->NF & 0x80000000) | (ZF << 30)
1498 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
1499 | env->pstate | env->daif | (env->btype << 10);
1500}
1501
1502static inline void pstate_write(CPUARMState *env, uint32_t val)
1503{
1504 env->ZF = (~val) & PSTATE_Z;
1505 env->NF = val;
1506 env->CF = (val >> 29) & 1;
1507 env->VF = (val << 3) & 0x80000000;
1508 env->daif = val & PSTATE_DAIF;
1509 env->btype = (val >> 10) & 3;
1510 env->pstate = val & ~CACHED_PSTATE_BITS;
1511}
1512
1513
1514uint32_t cpsr_read(CPUARMState *env);
1515
1516typedef enum CPSRWriteType {
1517 CPSRWriteByInstr = 0,
1518 CPSRWriteExceptionReturn = 1,
1519 CPSRWriteRaw = 2,
1520
1521 CPSRWriteByGDBStub = 3,
1522} CPSRWriteType;
1523
1524
1525
1526
1527
1528
1529
1530void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1531 CPSRWriteType write_type);
1532
1533
1534static inline uint32_t xpsr_read(CPUARMState *env)
1535{
1536 int ZF;
1537 ZF = (env->ZF == 0);
1538 return (env->NF & 0x80000000) | (ZF << 30)
1539 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1540 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1541 | ((env->condexec_bits & 0xfc) << 8)
1542 | (env->GE << 16)
1543 | env->v7m.exception;
1544}
1545
1546
1547static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1548{
1549 if (mask & XPSR_NZCV) {
1550 env->ZF = (~val) & XPSR_Z;
1551 env->NF = val;
1552 env->CF = (val >> 29) & 1;
1553 env->VF = (val << 3) & 0x80000000;
1554 }
1555 if (mask & XPSR_Q) {
1556 env->QF = ((val & XPSR_Q) != 0);
1557 }
1558 if (mask & XPSR_GE) {
1559 env->GE = (val & XPSR_GE) >> 16;
1560 }
1561#ifndef CONFIG_USER_ONLY
1562 if (mask & XPSR_T) {
1563 env->thumb = ((val & XPSR_T) != 0);
1564 }
1565 if (mask & XPSR_IT_0_1) {
1566 env->condexec_bits &= ~3;
1567 env->condexec_bits |= (val >> 25) & 3;
1568 }
1569 if (mask & XPSR_IT_2_7) {
1570 env->condexec_bits &= 3;
1571 env->condexec_bits |= (val >> 8) & 0xfc;
1572 }
1573 if (mask & XPSR_EXCP) {
1574
1575 write_v7m_exception(env, val & XPSR_EXCP);
1576 }
1577#endif
1578}
1579
1580#define HCR_VM (1ULL << 0)
1581#define HCR_SWIO (1ULL << 1)
1582#define HCR_PTW (1ULL << 2)
1583#define HCR_FMO (1ULL << 3)
1584#define HCR_IMO (1ULL << 4)
1585#define HCR_AMO (1ULL << 5)
1586#define HCR_VF (1ULL << 6)
1587#define HCR_VI (1ULL << 7)
1588#define HCR_VSE (1ULL << 8)
1589#define HCR_FB (1ULL << 9)
1590#define HCR_BSU_MASK (3ULL << 10)
1591#define HCR_DC (1ULL << 12)
1592#define HCR_TWI (1ULL << 13)
1593#define HCR_TWE (1ULL << 14)
1594#define HCR_TID0 (1ULL << 15)
1595#define HCR_TID1 (1ULL << 16)
1596#define HCR_TID2 (1ULL << 17)
1597#define HCR_TID3 (1ULL << 18)
1598#define HCR_TSC (1ULL << 19)
1599#define HCR_TIDCP (1ULL << 20)
1600#define HCR_TACR (1ULL << 21)
1601#define HCR_TSW (1ULL << 22)
1602#define HCR_TPCP (1ULL << 23)
1603#define HCR_TPU (1ULL << 24)
1604#define HCR_TTLB (1ULL << 25)
1605#define HCR_TVM (1ULL << 26)
1606#define HCR_TGE (1ULL << 27)
1607#define HCR_TDZ (1ULL << 28)
1608#define HCR_HCD (1ULL << 29)
1609#define HCR_TRVM (1ULL << 30)
1610#define HCR_RW (1ULL << 31)
1611#define HCR_CD (1ULL << 32)
1612#define HCR_ID (1ULL << 33)
1613#define HCR_E2H (1ULL << 34)
1614#define HCR_TLOR (1ULL << 35)
1615#define HCR_TERR (1ULL << 36)
1616#define HCR_TEA (1ULL << 37)
1617#define HCR_MIOCNCE (1ULL << 38)
1618
1619#define HCR_APK (1ULL << 40)
1620#define HCR_API (1ULL << 41)
1621#define HCR_NV (1ULL << 42)
1622#define HCR_NV1 (1ULL << 43)
1623#define HCR_AT (1ULL << 44)
1624#define HCR_NV2 (1ULL << 45)
1625#define HCR_FWB (1ULL << 46)
1626#define HCR_FIEN (1ULL << 47)
1627
1628#define HCR_TID4 (1ULL << 49)
1629#define HCR_TICAB (1ULL << 50)
1630#define HCR_AMVOFFEN (1ULL << 51)
1631#define HCR_TOCU (1ULL << 52)
1632#define HCR_ENSCXT (1ULL << 53)
1633#define HCR_TTLBIS (1ULL << 54)
1634#define HCR_TTLBOS (1ULL << 55)
1635#define HCR_ATA (1ULL << 56)
1636#define HCR_DCT (1ULL << 57)
1637#define HCR_TID5 (1ULL << 58)
1638#define HCR_TWEDEN (1ULL << 59)
1639#define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
1640
1641#define HCRX_ENAS0 (1ULL << 0)
1642#define HCRX_ENALS (1ULL << 1)
1643#define HCRX_ENASR (1ULL << 2)
1644#define HCRX_FNXS (1ULL << 3)
1645#define HCRX_FGTNXS (1ULL << 4)
1646#define HCRX_SMPME (1ULL << 5)
1647#define HCRX_TALLINT (1ULL << 6)
1648#define HCRX_VINMI (1ULL << 7)
1649#define HCRX_VFNMI (1ULL << 8)
1650#define HCRX_CMOW (1ULL << 9)
1651#define HCRX_MCE2 (1ULL << 10)
1652#define HCRX_MSCEN (1ULL << 11)
1653
1654#define HPFAR_NS (1ULL << 63)
1655
1656#define SCR_NS (1U << 0)
1657#define SCR_IRQ (1U << 1)
1658#define SCR_FIQ (1U << 2)
1659#define SCR_EA (1U << 3)
1660#define SCR_FW (1U << 4)
1661#define SCR_AW (1U << 5)
1662#define SCR_NET (1U << 6)
1663#define SCR_SMD (1U << 7)
1664#define SCR_HCE (1U << 8)
1665#define SCR_SIF (1U << 9)
1666#define SCR_RW (1U << 10)
1667#define SCR_ST (1U << 11)
1668#define SCR_TWI (1U << 12)
1669#define SCR_TWE (1U << 13)
1670#define SCR_TLOR (1U << 14)
1671#define SCR_TERR (1U << 15)
1672#define SCR_APK (1U << 16)
1673#define SCR_API (1U << 17)
1674#define SCR_EEL2 (1U << 18)
1675#define SCR_EASE (1U << 19)
1676#define SCR_NMEA (1U << 20)
1677#define SCR_FIEN (1U << 21)
1678#define SCR_ENSCXT (1U << 25)
1679#define SCR_ATA (1U << 26)
1680#define SCR_FGTEN (1U << 27)
1681#define SCR_ECVEN (1U << 28)
1682#define SCR_TWEDEN (1U << 29)
1683#define SCR_TWEDEL MAKE_64BIT_MASK(30, 4)
1684#define SCR_TME (1ULL << 34)
1685#define SCR_AMVOFFEN (1ULL << 35)
1686#define SCR_ENAS0 (1ULL << 36)
1687#define SCR_ADEN (1ULL << 37)
1688#define SCR_HXEN (1ULL << 38)
1689#define SCR_TRNDR (1ULL << 40)
1690#define SCR_ENTP2 (1ULL << 41)
1691#define SCR_GPF (1ULL << 48)
1692
1693#define HSTR_TTEE (1 << 16)
1694#define HSTR_TJDBX (1 << 17)
1695
1696
1697uint32_t vfp_get_fpscr(CPUARMState *env);
1698void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1699
1700
1701
1702
1703
1704
1705
1706
1707#define FPSR_MASK 0xf800009f
1708#define FPCR_MASK 0x07ff9f00
1709
1710#define FPCR_IOE (1 << 8)
1711#define FPCR_DZE (1 << 9)
1712#define FPCR_OFE (1 << 10)
1713#define FPCR_UFE (1 << 11)
1714#define FPCR_IXE (1 << 12)
1715#define FPCR_IDE (1 << 15)
1716#define FPCR_FZ16 (1 << 19)
1717#define FPCR_RMODE_MASK (3 << 22)
1718#define FPCR_FZ (1 << 24)
1719#define FPCR_DN (1 << 25)
1720#define FPCR_AHP (1 << 26)
1721#define FPCR_QC (1 << 27)
1722#define FPCR_V (1 << 28)
1723#define FPCR_C (1 << 29)
1724#define FPCR_Z (1 << 30)
1725#define FPCR_N (1 << 31)
1726
1727#define FPCR_LTPSIZE_SHIFT 16
1728#define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT)
1729#define FPCR_LTPSIZE_LENGTH 3
1730
1731#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
1732#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
1733
1734static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1735{
1736 return vfp_get_fpscr(env) & FPSR_MASK;
1737}
1738
1739static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1740{
1741 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1742 vfp_set_fpscr(env, new_fpscr);
1743}
1744
1745static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1746{
1747 return vfp_get_fpscr(env) & FPCR_MASK;
1748}
1749
1750static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1751{
1752 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1753 vfp_set_fpscr(env, new_fpscr);
1754}
1755
1756enum arm_cpu_mode {
1757 ARM_CPU_MODE_USR = 0x10,
1758 ARM_CPU_MODE_FIQ = 0x11,
1759 ARM_CPU_MODE_IRQ = 0x12,
1760 ARM_CPU_MODE_SVC = 0x13,
1761 ARM_CPU_MODE_MON = 0x16,
1762 ARM_CPU_MODE_ABT = 0x17,
1763 ARM_CPU_MODE_HYP = 0x1a,
1764 ARM_CPU_MODE_UND = 0x1b,
1765 ARM_CPU_MODE_SYS = 0x1f
1766};
1767
1768
1769#define ARM_VFP_FPSID 0
1770#define ARM_VFP_FPSCR 1
1771#define ARM_VFP_MVFR2 5
1772#define ARM_VFP_MVFR1 6
1773#define ARM_VFP_MVFR0 7
1774#define ARM_VFP_FPEXC 8
1775#define ARM_VFP_FPINST 9
1776#define ARM_VFP_FPINST2 10
1777
1778#define ARM_VFP_FPSCR_NZCVQC 2
1779#define ARM_VFP_VPR 12
1780#define ARM_VFP_P0 13
1781#define ARM_VFP_FPCXT_NS 14
1782#define ARM_VFP_FPCXT_S 15
1783
1784
1785#define QEMU_VFP_FPSCR_NZCV 0xffff
1786
1787
1788#define ARM_IWMMXT_wCID 0
1789#define ARM_IWMMXT_wCon 1
1790#define ARM_IWMMXT_wCSSF 2
1791#define ARM_IWMMXT_wCASF 3
1792#define ARM_IWMMXT_wCGR0 8
1793#define ARM_IWMMXT_wCGR1 9
1794#define ARM_IWMMXT_wCGR2 10
1795#define ARM_IWMMXT_wCGR3 11
1796
1797
1798FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1799FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1800FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1801FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1802FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1803FIELD(V7M_CCR, STKALIGN, 9, 1)
1804FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
1805FIELD(V7M_CCR, DC, 16, 1)
1806FIELD(V7M_CCR, IC, 17, 1)
1807FIELD(V7M_CCR, BP, 18, 1)
1808FIELD(V7M_CCR, LOB, 19, 1)
1809FIELD(V7M_CCR, TRD, 20, 1)
1810
1811
1812FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1813FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1814FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1815FIELD(V7M_SCR, SEVONPEND, 4, 1)
1816
1817
1818FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1819FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1820FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1821FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1822FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1823FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1824FIELD(V7M_AIRCR, PRIS, 14, 1)
1825FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1826FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1827
1828
1829FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1830FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1831FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1832FIELD(V7M_CFSR, MSTKERR, 4, 1)
1833FIELD(V7M_CFSR, MLSPERR, 5, 1)
1834FIELD(V7M_CFSR, MMARVALID, 7, 1)
1835
1836
1837FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1838FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1839FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1840FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1841FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1842FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1843FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1844
1845
1846FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1847FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1848FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1849FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1850FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
1851FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1852FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1853
1854
1855FIELD(V7M_CFSR, MMFSR, 0, 8)
1856FIELD(V7M_CFSR, BFSR, 8, 8)
1857FIELD(V7M_CFSR, UFSR, 16, 16)
1858
1859
1860FIELD(V7M_HFSR, VECTTBL, 1, 1)
1861FIELD(V7M_HFSR, FORCED, 30, 1)
1862FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1863
1864
1865FIELD(V7M_DFSR, HALTED, 0, 1)
1866FIELD(V7M_DFSR, BKPT, 1, 1)
1867FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1868FIELD(V7M_DFSR, VCATCH, 3, 1)
1869FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1870
1871
1872FIELD(V7M_SFSR, INVEP, 0, 1)
1873FIELD(V7M_SFSR, INVIS, 1, 1)
1874FIELD(V7M_SFSR, INVER, 2, 1)
1875FIELD(V7M_SFSR, AUVIOL, 3, 1)
1876FIELD(V7M_SFSR, INVTRAN, 4, 1)
1877FIELD(V7M_SFSR, LSPERR, 5, 1)
1878FIELD(V7M_SFSR, SFARVALID, 6, 1)
1879FIELD(V7M_SFSR, LSERR, 7, 1)
1880
1881
1882FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1883FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1884FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1885
1886
1887FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
1888FIELD(V7M_CLIDR, LOUIS, 21, 3)
1889FIELD(V7M_CLIDR, LOC, 24, 3)
1890FIELD(V7M_CLIDR, LOUU, 27, 3)
1891FIELD(V7M_CLIDR, ICB, 30, 2)
1892
1893FIELD(V7M_CSSELR, IND, 0, 1)
1894FIELD(V7M_CSSELR, LEVEL, 1, 3)
1895
1896
1897
1898
1899FIELD(V7M_CSSELR, INDEX, 0, 4)
1900
1901
1902FIELD(V7M_FPCCR, LSPACT, 0, 1)
1903FIELD(V7M_FPCCR, USER, 1, 1)
1904FIELD(V7M_FPCCR, S, 2, 1)
1905FIELD(V7M_FPCCR, THREAD, 3, 1)
1906FIELD(V7M_FPCCR, HFRDY, 4, 1)
1907FIELD(V7M_FPCCR, MMRDY, 5, 1)
1908FIELD(V7M_FPCCR, BFRDY, 6, 1)
1909FIELD(V7M_FPCCR, SFRDY, 7, 1)
1910FIELD(V7M_FPCCR, MONRDY, 8, 1)
1911FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1)
1912FIELD(V7M_FPCCR, UFRDY, 10, 1)
1913FIELD(V7M_FPCCR, RES0, 11, 15)
1914FIELD(V7M_FPCCR, TS, 26, 1)
1915FIELD(V7M_FPCCR, CLRONRETS, 27, 1)
1916FIELD(V7M_FPCCR, CLRONRET, 28, 1)
1917FIELD(V7M_FPCCR, LSPENS, 29, 1)
1918FIELD(V7M_FPCCR, LSPEN, 30, 1)
1919FIELD(V7M_FPCCR, ASPEN, 31, 1)
1920
1921#define R_V7M_FPCCR_BANKED_MASK \
1922 (R_V7M_FPCCR_LSPACT_MASK | \
1923 R_V7M_FPCCR_USER_MASK | \
1924 R_V7M_FPCCR_THREAD_MASK | \
1925 R_V7M_FPCCR_MMRDY_MASK | \
1926 R_V7M_FPCCR_SPLIMVIOL_MASK | \
1927 R_V7M_FPCCR_UFRDY_MASK | \
1928 R_V7M_FPCCR_ASPEN_MASK)
1929
1930
1931FIELD(V7M_VPR, P0, 0, 16)
1932FIELD(V7M_VPR, MASK01, 16, 4)
1933FIELD(V7M_VPR, MASK23, 20, 4)
1934
1935
1936
1937
1938FIELD(CLIDR_EL1, CTYPE1, 0, 3)
1939FIELD(CLIDR_EL1, CTYPE2, 3, 3)
1940FIELD(CLIDR_EL1, CTYPE3, 6, 3)
1941FIELD(CLIDR_EL1, CTYPE4, 9, 3)
1942FIELD(CLIDR_EL1, CTYPE5, 12, 3)
1943FIELD(CLIDR_EL1, CTYPE6, 15, 3)
1944FIELD(CLIDR_EL1, CTYPE7, 18, 3)
1945FIELD(CLIDR_EL1, LOUIS, 21, 3)
1946FIELD(CLIDR_EL1, LOC, 24, 3)
1947FIELD(CLIDR_EL1, LOUU, 27, 3)
1948FIELD(CLIDR_EL1, ICB, 30, 3)
1949
1950
1951FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
1952FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
1953FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
1954
1955
1956FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
1957FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
1958FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
1959
1960FIELD(CTR_EL0, IMINLINE, 0, 4)
1961FIELD(CTR_EL0, L1IP, 14, 2)
1962FIELD(CTR_EL0, DMINLINE, 16, 4)
1963FIELD(CTR_EL0, ERG, 20, 4)
1964FIELD(CTR_EL0, CWG, 24, 4)
1965FIELD(CTR_EL0, IDC, 28, 1)
1966FIELD(CTR_EL0, DIC, 29, 1)
1967FIELD(CTR_EL0, TMINLINE, 32, 6)
1968
1969FIELD(MIDR_EL1, REVISION, 0, 4)
1970FIELD(MIDR_EL1, PARTNUM, 4, 12)
1971FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
1972FIELD(MIDR_EL1, VARIANT, 20, 4)
1973FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
1974
1975FIELD(ID_ISAR0, SWAP, 0, 4)
1976FIELD(ID_ISAR0, BITCOUNT, 4, 4)
1977FIELD(ID_ISAR0, BITFIELD, 8, 4)
1978FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
1979FIELD(ID_ISAR0, COPROC, 16, 4)
1980FIELD(ID_ISAR0, DEBUG, 20, 4)
1981FIELD(ID_ISAR0, DIVIDE, 24, 4)
1982
1983FIELD(ID_ISAR1, ENDIAN, 0, 4)
1984FIELD(ID_ISAR1, EXCEPT, 4, 4)
1985FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
1986FIELD(ID_ISAR1, EXTEND, 12, 4)
1987FIELD(ID_ISAR1, IFTHEN, 16, 4)
1988FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
1989FIELD(ID_ISAR1, INTERWORK, 24, 4)
1990FIELD(ID_ISAR1, JAZELLE, 28, 4)
1991
1992FIELD(ID_ISAR2, LOADSTORE, 0, 4)
1993FIELD(ID_ISAR2, MEMHINT, 4, 4)
1994FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
1995FIELD(ID_ISAR2, MULT, 12, 4)
1996FIELD(ID_ISAR2, MULTS, 16, 4)
1997FIELD(ID_ISAR2, MULTU, 20, 4)
1998FIELD(ID_ISAR2, PSR_AR, 24, 4)
1999FIELD(ID_ISAR2, REVERSAL, 28, 4)
2000
2001FIELD(ID_ISAR3, SATURATE, 0, 4)
2002FIELD(ID_ISAR3, SIMD, 4, 4)
2003FIELD(ID_ISAR3, SVC, 8, 4)
2004FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
2005FIELD(ID_ISAR3, TABBRANCH, 16, 4)
2006FIELD(ID_ISAR3, T32COPY, 20, 4)
2007FIELD(ID_ISAR3, TRUENOP, 24, 4)
2008FIELD(ID_ISAR3, T32EE, 28, 4)
2009
2010FIELD(ID_ISAR4, UNPRIV, 0, 4)
2011FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
2012FIELD(ID_ISAR4, WRITEBACK, 8, 4)
2013FIELD(ID_ISAR4, SMC, 12, 4)
2014FIELD(ID_ISAR4, BARRIER, 16, 4)
2015FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
2016FIELD(ID_ISAR4, PSR_M, 24, 4)
2017FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
2018
2019FIELD(ID_ISAR5, SEVL, 0, 4)
2020FIELD(ID_ISAR5, AES, 4, 4)
2021FIELD(ID_ISAR5, SHA1, 8, 4)
2022FIELD(ID_ISAR5, SHA2, 12, 4)
2023FIELD(ID_ISAR5, CRC32, 16, 4)
2024FIELD(ID_ISAR5, RDM, 24, 4)
2025FIELD(ID_ISAR5, VCMA, 28, 4)
2026
2027FIELD(ID_ISAR6, JSCVT, 0, 4)
2028FIELD(ID_ISAR6, DP, 4, 4)
2029FIELD(ID_ISAR6, FHM, 8, 4)
2030FIELD(ID_ISAR6, SB, 12, 4)
2031FIELD(ID_ISAR6, SPECRES, 16, 4)
2032FIELD(ID_ISAR6, BF16, 20, 4)
2033FIELD(ID_ISAR6, I8MM, 24, 4)
2034
2035FIELD(ID_MMFR0, VMSA, 0, 4)
2036FIELD(ID_MMFR0, PMSA, 4, 4)
2037FIELD(ID_MMFR0, OUTERSHR, 8, 4)
2038FIELD(ID_MMFR0, SHARELVL, 12, 4)
2039FIELD(ID_MMFR0, TCM, 16, 4)
2040FIELD(ID_MMFR0, AUXREG, 20, 4)
2041FIELD(ID_MMFR0, FCSE, 24, 4)
2042FIELD(ID_MMFR0, INNERSHR, 28, 4)
2043
2044FIELD(ID_MMFR1, L1HVDVA, 0, 4)
2045FIELD(ID_MMFR1, L1UNIVA, 4, 4)
2046FIELD(ID_MMFR1, L1HVDSW, 8, 4)
2047FIELD(ID_MMFR1, L1UNISW, 12, 4)
2048FIELD(ID_MMFR1, L1HVD, 16, 4)
2049FIELD(ID_MMFR1, L1UNI, 20, 4)
2050FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
2051FIELD(ID_MMFR1, BPRED, 28, 4)
2052
2053FIELD(ID_MMFR2, L1HVDFG, 0, 4)
2054FIELD(ID_MMFR2, L1HVDBG, 4, 4)
2055FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
2056FIELD(ID_MMFR2, HVDTLB, 12, 4)
2057FIELD(ID_MMFR2, UNITLB, 16, 4)
2058FIELD(ID_MMFR2, MEMBARR, 20, 4)
2059FIELD(ID_MMFR2, WFISTALL, 24, 4)
2060FIELD(ID_MMFR2, HWACCFLG, 28, 4)
2061
2062FIELD(ID_MMFR3, CMAINTVA, 0, 4)
2063FIELD(ID_MMFR3, CMAINTSW, 4, 4)
2064FIELD(ID_MMFR3, BPMAINT, 8, 4)
2065FIELD(ID_MMFR3, MAINTBCST, 12, 4)
2066FIELD(ID_MMFR3, PAN, 16, 4)
2067FIELD(ID_MMFR3, COHWALK, 20, 4)
2068FIELD(ID_MMFR3, CMEMSZ, 24, 4)
2069FIELD(ID_MMFR3, SUPERSEC, 28, 4)
2070
2071FIELD(ID_MMFR4, SPECSEI, 0, 4)
2072FIELD(ID_MMFR4, AC2, 4, 4)
2073FIELD(ID_MMFR4, XNX, 8, 4)
2074FIELD(ID_MMFR4, CNP, 12, 4)
2075FIELD(ID_MMFR4, HPDS, 16, 4)
2076FIELD(ID_MMFR4, LSM, 20, 4)
2077FIELD(ID_MMFR4, CCIDX, 24, 4)
2078FIELD(ID_MMFR4, EVT, 28, 4)
2079
2080FIELD(ID_MMFR5, ETS, 0, 4)
2081FIELD(ID_MMFR5, NTLBPA, 4, 4)
2082
2083FIELD(ID_PFR0, STATE0, 0, 4)
2084FIELD(ID_PFR0, STATE1, 4, 4)
2085FIELD(ID_PFR0, STATE2, 8, 4)
2086FIELD(ID_PFR0, STATE3, 12, 4)
2087FIELD(ID_PFR0, CSV2, 16, 4)
2088FIELD(ID_PFR0, AMU, 20, 4)
2089FIELD(ID_PFR0, DIT, 24, 4)
2090FIELD(ID_PFR0, RAS, 28, 4)
2091
2092FIELD(ID_PFR1, PROGMOD, 0, 4)
2093FIELD(ID_PFR1, SECURITY, 4, 4)
2094FIELD(ID_PFR1, MPROGMOD, 8, 4)
2095FIELD(ID_PFR1, VIRTUALIZATION, 12, 4)
2096FIELD(ID_PFR1, GENTIMER, 16, 4)
2097FIELD(ID_PFR1, SEC_FRAC, 20, 4)
2098FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
2099FIELD(ID_PFR1, GIC, 28, 4)
2100
2101FIELD(ID_PFR2, CSV3, 0, 4)
2102FIELD(ID_PFR2, SSBS, 4, 4)
2103FIELD(ID_PFR2, RAS_FRAC, 8, 4)
2104
2105FIELD(ID_AA64ISAR0, AES, 4, 4)
2106FIELD(ID_AA64ISAR0, SHA1, 8, 4)
2107FIELD(ID_AA64ISAR0, SHA2, 12, 4)
2108FIELD(ID_AA64ISAR0, CRC32, 16, 4)
2109FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
2110FIELD(ID_AA64ISAR0, RDM, 28, 4)
2111FIELD(ID_AA64ISAR0, SHA3, 32, 4)
2112FIELD(ID_AA64ISAR0, SM3, 36, 4)
2113FIELD(ID_AA64ISAR0, SM4, 40, 4)
2114FIELD(ID_AA64ISAR0, DP, 44, 4)
2115FIELD(ID_AA64ISAR0, FHM, 48, 4)
2116FIELD(ID_AA64ISAR0, TS, 52, 4)
2117FIELD(ID_AA64ISAR0, TLB, 56, 4)
2118FIELD(ID_AA64ISAR0, RNDR, 60, 4)
2119
2120FIELD(ID_AA64ISAR1, DPB, 0, 4)
2121FIELD(ID_AA64ISAR1, APA, 4, 4)
2122FIELD(ID_AA64ISAR1, API, 8, 4)
2123FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
2124FIELD(ID_AA64ISAR1, FCMA, 16, 4)
2125FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
2126FIELD(ID_AA64ISAR1, GPA, 24, 4)
2127FIELD(ID_AA64ISAR1, GPI, 28, 4)
2128FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
2129FIELD(ID_AA64ISAR1, SB, 36, 4)
2130FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
2131FIELD(ID_AA64ISAR1, BF16, 44, 4)
2132FIELD(ID_AA64ISAR1, DGH, 48, 4)
2133FIELD(ID_AA64ISAR1, I8MM, 52, 4)
2134FIELD(ID_AA64ISAR1, XS, 56, 4)
2135FIELD(ID_AA64ISAR1, LS64, 60, 4)
2136
2137FIELD(ID_AA64ISAR2, WFXT, 0, 4)
2138FIELD(ID_AA64ISAR2, RPRES, 4, 4)
2139FIELD(ID_AA64ISAR2, GPA3, 8, 4)
2140FIELD(ID_AA64ISAR2, APA3, 12, 4)
2141FIELD(ID_AA64ISAR2, MOPS, 16, 4)
2142FIELD(ID_AA64ISAR2, BC, 20, 4)
2143FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4)
2144
2145FIELD(ID_AA64PFR0, EL0, 0, 4)
2146FIELD(ID_AA64PFR0, EL1, 4, 4)
2147FIELD(ID_AA64PFR0, EL2, 8, 4)
2148FIELD(ID_AA64PFR0, EL3, 12, 4)
2149FIELD(ID_AA64PFR0, FP, 16, 4)
2150FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
2151FIELD(ID_AA64PFR0, GIC, 24, 4)
2152FIELD(ID_AA64PFR0, RAS, 28, 4)
2153FIELD(ID_AA64PFR0, SVE, 32, 4)
2154FIELD(ID_AA64PFR0, SEL2, 36, 4)
2155FIELD(ID_AA64PFR0, MPAM, 40, 4)
2156FIELD(ID_AA64PFR0, AMU, 44, 4)
2157FIELD(ID_AA64PFR0, DIT, 48, 4)
2158FIELD(ID_AA64PFR0, CSV2, 56, 4)
2159FIELD(ID_AA64PFR0, CSV3, 60, 4)
2160
2161FIELD(ID_AA64PFR1, BT, 0, 4)
2162FIELD(ID_AA64PFR1, SSBS, 4, 4)
2163FIELD(ID_AA64PFR1, MTE, 8, 4)
2164FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
2165FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
2166FIELD(ID_AA64PFR1, SME, 24, 4)
2167FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4)
2168FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4)
2169FIELD(ID_AA64PFR1, NMI, 36, 4)
2170
2171FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
2172FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
2173FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
2174FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
2175FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
2176FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
2177FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
2178FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
2179FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
2180FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
2181FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
2182FIELD(ID_AA64MMFR0, EXS, 44, 4)
2183FIELD(ID_AA64MMFR0, FGT, 56, 4)
2184FIELD(ID_AA64MMFR0, ECV, 60, 4)
2185
2186FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
2187FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
2188FIELD(ID_AA64MMFR1, VH, 8, 4)
2189FIELD(ID_AA64MMFR1, HPDS, 12, 4)
2190FIELD(ID_AA64MMFR1, LO, 16, 4)
2191FIELD(ID_AA64MMFR1, PAN, 20, 4)
2192FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
2193FIELD(ID_AA64MMFR1, XNX, 28, 4)
2194FIELD(ID_AA64MMFR1, TWED, 32, 4)
2195FIELD(ID_AA64MMFR1, ETS, 36, 4)
2196FIELD(ID_AA64MMFR1, HCX, 40, 4)
2197FIELD(ID_AA64MMFR1, AFP, 44, 4)
2198FIELD(ID_AA64MMFR1, NTLBPA, 48, 4)
2199FIELD(ID_AA64MMFR1, TIDCP1, 52, 4)
2200FIELD(ID_AA64MMFR1, CMOW, 56, 4)
2201
2202FIELD(ID_AA64MMFR2, CNP, 0, 4)
2203FIELD(ID_AA64MMFR2, UAO, 4, 4)
2204FIELD(ID_AA64MMFR2, LSM, 8, 4)
2205FIELD(ID_AA64MMFR2, IESB, 12, 4)
2206FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
2207FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
2208FIELD(ID_AA64MMFR2, NV, 24, 4)
2209FIELD(ID_AA64MMFR2, ST, 28, 4)
2210FIELD(ID_AA64MMFR2, AT, 32, 4)
2211FIELD(ID_AA64MMFR2, IDS, 36, 4)
2212FIELD(ID_AA64MMFR2, FWB, 40, 4)
2213FIELD(ID_AA64MMFR2, TTL, 48, 4)
2214FIELD(ID_AA64MMFR2, BBM, 52, 4)
2215FIELD(ID_AA64MMFR2, EVT, 56, 4)
2216FIELD(ID_AA64MMFR2, E0PD, 60, 4)
2217
2218FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
2219FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
2220FIELD(ID_AA64DFR0, PMUVER, 8, 4)
2221FIELD(ID_AA64DFR0, BRPS, 12, 4)
2222FIELD(ID_AA64DFR0, WRPS, 20, 4)
2223FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
2224FIELD(ID_AA64DFR0, PMSVER, 32, 4)
2225FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
2226FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
2227FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4)
2228FIELD(ID_AA64DFR0, MTPMU, 48, 4)
2229FIELD(ID_AA64DFR0, BRBE, 52, 4)
2230FIELD(ID_AA64DFR0, HPMN0, 60, 4)
2231
2232FIELD(ID_AA64ZFR0, SVEVER, 0, 4)
2233FIELD(ID_AA64ZFR0, AES, 4, 4)
2234FIELD(ID_AA64ZFR0, BITPERM, 16, 4)
2235FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4)
2236FIELD(ID_AA64ZFR0, SHA3, 32, 4)
2237FIELD(ID_AA64ZFR0, SM4, 40, 4)
2238FIELD(ID_AA64ZFR0, I8MM, 44, 4)
2239FIELD(ID_AA64ZFR0, F32MM, 52, 4)
2240FIELD(ID_AA64ZFR0, F64MM, 56, 4)
2241
2242FIELD(ID_AA64SMFR0, F32F32, 32, 1)
2243FIELD(ID_AA64SMFR0, B16F32, 34, 1)
2244FIELD(ID_AA64SMFR0, F16F32, 35, 1)
2245FIELD(ID_AA64SMFR0, I8I32, 36, 4)
2246FIELD(ID_AA64SMFR0, F64F64, 48, 1)
2247FIELD(ID_AA64SMFR0, I16I64, 52, 4)
2248FIELD(ID_AA64SMFR0, SMEVER, 56, 4)
2249FIELD(ID_AA64SMFR0, FA64, 63, 1)
2250
2251FIELD(ID_DFR0, COPDBG, 0, 4)
2252FIELD(ID_DFR0, COPSDBG, 4, 4)
2253FIELD(ID_DFR0, MMAPDBG, 8, 4)
2254FIELD(ID_DFR0, COPTRC, 12, 4)
2255FIELD(ID_DFR0, MMAPTRC, 16, 4)
2256FIELD(ID_DFR0, MPROFDBG, 20, 4)
2257FIELD(ID_DFR0, PERFMON, 24, 4)
2258FIELD(ID_DFR0, TRACEFILT, 28, 4)
2259
2260FIELD(ID_DFR1, MTPMU, 0, 4)
2261FIELD(ID_DFR1, HPMN0, 4, 4)
2262
2263FIELD(DBGDIDR, SE_IMP, 12, 1)
2264FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
2265FIELD(DBGDIDR, VERSION, 16, 4)
2266FIELD(DBGDIDR, CTX_CMPS, 20, 4)
2267FIELD(DBGDIDR, BRPS, 24, 4)
2268FIELD(DBGDIDR, WRPS, 28, 4)
2269
2270FIELD(DBGDEVID, PCSAMPLE, 0, 4)
2271FIELD(DBGDEVID, WPADDRMASK, 4, 4)
2272FIELD(DBGDEVID, BPADDRMASK, 8, 4)
2273FIELD(DBGDEVID, VECTORCATCH, 12, 4)
2274FIELD(DBGDEVID, VIRTEXTNS, 16, 4)
2275FIELD(DBGDEVID, DOUBLELOCK, 20, 4)
2276FIELD(DBGDEVID, AUXREGS, 24, 4)
2277FIELD(DBGDEVID, CIDMASK, 28, 4)
2278
2279FIELD(MVFR0, SIMDREG, 0, 4)
2280FIELD(MVFR0, FPSP, 4, 4)
2281FIELD(MVFR0, FPDP, 8, 4)
2282FIELD(MVFR0, FPTRAP, 12, 4)
2283FIELD(MVFR0, FPDIVIDE, 16, 4)
2284FIELD(MVFR0, FPSQRT, 20, 4)
2285FIELD(MVFR0, FPSHVEC, 24, 4)
2286FIELD(MVFR0, FPROUND, 28, 4)
2287
2288FIELD(MVFR1, FPFTZ, 0, 4)
2289FIELD(MVFR1, FPDNAN, 4, 4)
2290FIELD(MVFR1, SIMDLS, 8, 4)
2291FIELD(MVFR1, SIMDINT, 12, 4)
2292FIELD(MVFR1, SIMDSP, 16, 4)
2293FIELD(MVFR1, SIMDHP, 20, 4)
2294FIELD(MVFR1, MVE, 8, 4)
2295FIELD(MVFR1, FP16, 20, 4)
2296FIELD(MVFR1, FPHP, 24, 4)
2297FIELD(MVFR1, SIMDFMAC, 28, 4)
2298
2299FIELD(MVFR2, SIMDMISC, 0, 4)
2300FIELD(MVFR2, FPMISC, 4, 4)
2301
2302QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
2303
2304
2305
2306
2307
2308enum arm_features {
2309 ARM_FEATURE_AUXCR,
2310 ARM_FEATURE_XSCALE,
2311 ARM_FEATURE_IWMMXT,
2312 ARM_FEATURE_V6,
2313 ARM_FEATURE_V6K,
2314 ARM_FEATURE_V7,
2315 ARM_FEATURE_THUMB2,
2316 ARM_FEATURE_PMSA,
2317 ARM_FEATURE_NEON,
2318 ARM_FEATURE_M,
2319 ARM_FEATURE_OMAPCP,
2320 ARM_FEATURE_THUMB2EE,
2321 ARM_FEATURE_V7MP,
2322 ARM_FEATURE_V7VE,
2323 ARM_FEATURE_V4T,
2324 ARM_FEATURE_V5,
2325 ARM_FEATURE_STRONGARM,
2326 ARM_FEATURE_VAPA,
2327 ARM_FEATURE_GENERIC_TIMER,
2328 ARM_FEATURE_MVFR,
2329 ARM_FEATURE_DUMMY_C15_REGS,
2330 ARM_FEATURE_CACHE_TEST_CLEAN,
2331 ARM_FEATURE_CACHE_DIRTY_REG,
2332 ARM_FEATURE_CACHE_BLOCK_OPS,
2333 ARM_FEATURE_MPIDR,
2334 ARM_FEATURE_LPAE,
2335 ARM_FEATURE_V8,
2336 ARM_FEATURE_AARCH64,
2337 ARM_FEATURE_CBAR,
2338 ARM_FEATURE_CBAR_RO,
2339 ARM_FEATURE_EL2,
2340 ARM_FEATURE_EL3,
2341 ARM_FEATURE_THUMB_DSP,
2342 ARM_FEATURE_PMU,
2343 ARM_FEATURE_VBAR,
2344 ARM_FEATURE_M_SECURITY,
2345 ARM_FEATURE_M_MAIN,
2346 ARM_FEATURE_V8_1M,
2347};
2348
2349static inline int arm_feature(CPUARMState *env, int feature)
2350{
2351 return (env->features & (1ULL << feature)) != 0;
2352}
2353
2354void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
2355
2356#if !defined(CONFIG_USER_ONLY)
2357
2358
2359
2360
2361
2362
2363static inline bool arm_is_secure_below_el3(CPUARMState *env)
2364{
2365 if (arm_feature(env, ARM_FEATURE_EL3)) {
2366 return !(env->cp15.scr_el3 & SCR_NS);
2367 } else {
2368
2369
2370
2371 return false;
2372 }
2373}
2374
2375
2376static inline bool arm_is_el3_or_mon(CPUARMState *env)
2377{
2378 if (arm_feature(env, ARM_FEATURE_EL3)) {
2379 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
2380
2381 return true;
2382 } else if (!is_a64(env) &&
2383 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
2384
2385 return true;
2386 }
2387 }
2388 return false;
2389}
2390
2391
2392static inline bool arm_is_secure(CPUARMState *env)
2393{
2394 if (arm_is_el3_or_mon(env)) {
2395 return true;
2396 }
2397 return arm_is_secure_below_el3(env);
2398}
2399
2400
2401
2402
2403
2404static inline bool arm_is_el2_enabled(CPUARMState *env)
2405{
2406 if (arm_feature(env, ARM_FEATURE_EL2)) {
2407 if (arm_is_secure_below_el3(env)) {
2408 return (env->cp15.scr_el3 & SCR_EEL2) != 0;
2409 }
2410 return true;
2411 }
2412 return false;
2413}
2414
2415#else
2416static inline bool arm_is_secure_below_el3(CPUARMState *env)
2417{
2418 return false;
2419}
2420
2421static inline bool arm_is_secure(CPUARMState *env)
2422{
2423 return false;
2424}
2425
2426static inline bool arm_is_el2_enabled(CPUARMState *env)
2427{
2428 return false;
2429}
2430#endif
2431
2432
2433
2434
2435
2436
2437
2438uint64_t arm_hcr_el2_eff(CPUARMState *env);
2439uint64_t arm_hcrx_el2_eff(CPUARMState *env);
2440
2441
2442static inline bool arm_el_is_aa64(CPUARMState *env, int el)
2443{
2444
2445
2446
2447 assert(el >= 1 && el <= 3);
2448 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
2449
2450
2451
2452
2453
2454 if (el == 3) {
2455 return aa64;
2456 }
2457
2458 if (arm_feature(env, ARM_FEATURE_EL3) &&
2459 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) {
2460 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
2461 }
2462
2463 if (el == 2) {
2464 return aa64;
2465 }
2466
2467 if (arm_is_el2_enabled(env)) {
2468 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
2469 }
2470
2471 return aa64;
2472}
2473
2474
2475
2476
2477
2478
2479
2480
2481static inline bool access_secure_reg(CPUARMState *env)
2482{
2483 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
2484 !arm_el_is_aa64(env, 3) &&
2485 !(env->cp15.scr_el3 & SCR_NS));
2486
2487 return ret;
2488}
2489
2490
2491#define A32_BANKED_REG_GET(_env, _regname, _secure) \
2492 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
2493
2494#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
2495 do { \
2496 if (_secure) { \
2497 (_env)->cp15._regname##_s = (_val); \
2498 } else { \
2499 (_env)->cp15._regname##_ns = (_val); \
2500 } \
2501 } while (0)
2502
2503
2504
2505
2506
2507
2508#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
2509 A32_BANKED_REG_GET((_env), _regname, \
2510 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
2511
2512#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
2513 A32_BANKED_REG_SET((_env), _regname, \
2514 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
2515 (_val))
2516
2517void arm_cpu_list(void);
2518uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
2519 uint32_t cur_el, bool secure);
2520
2521
2522#ifndef CONFIG_USER_ONLY
2523bool armv7m_nvic_can_take_pending_exception(void *opaque);
2524#else
2525static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
2526{
2527 return true;
2528}
2529#endif
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
2582 bool *ptargets_secure);
2583
2584
2585
2586
2587
2588
2589
2590
2591void armv7m_nvic_acknowledge_irq(void *opaque);
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure);
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627int armv7m_nvic_raw_execution_priority(void *opaque);
2628
2629
2630
2631
2632
2633
2634
2635#ifndef CONFIG_USER_ONLY
2636bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
2637#else
2638static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
2639{
2640 return false;
2641}
2642#endif
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670#define CP_REG_AA64_SHIFT 28
2671#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
2672
2673
2674
2675
2676
2677#define CP_REG_NS_SHIFT 29
2678#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
2679
2680#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
2681 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
2682 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
2683
2684#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
2685 (CP_REG_AA64_MASK | \
2686 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
2687 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
2688 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
2689 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
2690 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
2691 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
2692
2693
2694
2695
2696static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
2697{
2698 uint32_t cpregid = kvmid;
2699 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
2700 cpregid |= CP_REG_AA64_MASK;
2701 } else {
2702 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
2703 cpregid |= (1 << 15);
2704 }
2705
2706
2707
2708
2709 cpregid |= 1 << CP_REG_NS_SHIFT;
2710 }
2711 return cpregid;
2712}
2713
2714
2715
2716
2717static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
2718{
2719 uint64_t kvmid;
2720
2721 if (cpregid & CP_REG_AA64_MASK) {
2722 kvmid = cpregid & ~CP_REG_AA64_MASK;
2723 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
2724 } else {
2725 kvmid = cpregid & ~(1 << 15);
2726 if (cpregid & (1 << 15)) {
2727 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
2728 } else {
2729 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
2730 }
2731 }
2732 return kvmid;
2733}
2734
2735
2736static inline int arm_highest_el(CPUARMState *env)
2737{
2738 if (arm_feature(env, ARM_FEATURE_EL3)) {
2739 return 3;
2740 }
2741 if (arm_feature(env, ARM_FEATURE_EL2)) {
2742 return 2;
2743 }
2744 return 1;
2745}
2746
2747
2748static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
2749{
2750 return env->v7m.exception != 0;
2751}
2752
2753
2754
2755
2756static inline int arm_current_el(CPUARMState *env)
2757{
2758 if (arm_feature(env, ARM_FEATURE_M)) {
2759 return arm_v7m_is_handler_mode(env) ||
2760 !(env->v7m.control[env->v7m.secure] & 1);
2761 }
2762
2763 if (is_a64(env)) {
2764 return extract32(env->pstate, 2, 2);
2765 }
2766
2767 switch (env->uncached_cpsr & 0x1f) {
2768 case ARM_CPU_MODE_USR:
2769 return 0;
2770 case ARM_CPU_MODE_HYP:
2771 return 2;
2772 case ARM_CPU_MODE_MON:
2773 return 3;
2774 default:
2775 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
2776
2777
2778
2779 return 3;
2780 }
2781
2782 return 1;
2783 }
2784}
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800bool write_list_to_cpustate(ARMCPU *cpu);
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
2824
2825#define ARM_CPUID_TI915T 0x54029152
2826#define ARM_CPUID_TI925T 0x54029252
2827
2828#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
2829#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
2830#define CPU_RESOLVING_TYPE TYPE_ARM_CPU
2831
2832#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
2833
2834#define cpu_list arm_cpu_list
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930#define ARM_MMU_IDX_A 0x10
2931#define ARM_MMU_IDX_NOTLB 0x20
2932#define ARM_MMU_IDX_M 0x40
2933
2934
2935#define ARM_MMU_IDX_A_NS 0x8
2936
2937
2938#define ARM_MMU_IDX_M_PRIV 0x1
2939#define ARM_MMU_IDX_M_NEGPRI 0x2
2940#define ARM_MMU_IDX_M_S 0x4
2941
2942#define ARM_MMU_IDX_TYPE_MASK \
2943 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB)
2944#define ARM_MMU_IDX_COREIDX_MASK 0xf
2945
2946typedef enum ARMMMUIdx {
2947
2948
2949
2950 ARMMMUIdx_SE10_0 = 0 | ARM_MMU_IDX_A,
2951 ARMMMUIdx_SE20_0 = 1 | ARM_MMU_IDX_A,
2952 ARMMMUIdx_SE10_1 = 2 | ARM_MMU_IDX_A,
2953 ARMMMUIdx_SE20_2 = 3 | ARM_MMU_IDX_A,
2954 ARMMMUIdx_SE10_1_PAN = 4 | ARM_MMU_IDX_A,
2955 ARMMMUIdx_SE20_2_PAN = 5 | ARM_MMU_IDX_A,
2956 ARMMMUIdx_SE2 = 6 | ARM_MMU_IDX_A,
2957 ARMMMUIdx_SE3 = 7 | ARM_MMU_IDX_A,
2958
2959 ARMMMUIdx_E10_0 = ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS,
2960 ARMMMUIdx_E20_0 = ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS,
2961 ARMMMUIdx_E10_1 = ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS,
2962 ARMMMUIdx_E20_2 = ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS,
2963 ARMMMUIdx_E10_1_PAN = ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS,
2964 ARMMMUIdx_E20_2_PAN = ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS,
2965 ARMMMUIdx_E2 = ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS,
2966
2967
2968
2969
2970
2971 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
2972 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
2973 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
2974 ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB,
2975 ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB,
2976 ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB,
2977
2978
2979
2980
2981
2982
2983
2984 ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_NOTLB,
2985 ARMMMUIdx_Stage2_S = 7 | ARM_MMU_IDX_NOTLB,
2986
2987
2988
2989
2990 ARMMMUIdx_MUser = ARM_MMU_IDX_M,
2991 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV,
2992 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI,
2993 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI,
2994 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S,
2995 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S,
2996 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S,
2997 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S,
2998} ARMMMUIdx;
2999
3000
3001
3002
3003
3004#define TO_CORE_BIT(NAME) \
3005 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)
3006
3007typedef enum ARMMMUIdxBit {
3008 TO_CORE_BIT(E10_0),
3009 TO_CORE_BIT(E20_0),
3010 TO_CORE_BIT(E10_1),
3011 TO_CORE_BIT(E10_1_PAN),
3012 TO_CORE_BIT(E2),
3013 TO_CORE_BIT(E20_2),
3014 TO_CORE_BIT(E20_2_PAN),
3015 TO_CORE_BIT(SE10_0),
3016 TO_CORE_BIT(SE20_0),
3017 TO_CORE_BIT(SE10_1),
3018 TO_CORE_BIT(SE20_2),
3019 TO_CORE_BIT(SE10_1_PAN),
3020 TO_CORE_BIT(SE20_2_PAN),
3021 TO_CORE_BIT(SE2),
3022 TO_CORE_BIT(SE3),
3023
3024 TO_CORE_BIT(MUser),
3025 TO_CORE_BIT(MPriv),
3026 TO_CORE_BIT(MUserNegPri),
3027 TO_CORE_BIT(MPrivNegPri),
3028 TO_CORE_BIT(MSUser),
3029 TO_CORE_BIT(MSPriv),
3030 TO_CORE_BIT(MSUserNegPri),
3031 TO_CORE_BIT(MSPrivNegPri),
3032} ARMMMUIdxBit;
3033
3034#undef TO_CORE_BIT
3035
3036#define MMU_USER_IDX 0
3037
3038
3039typedef enum ARMASIdx {
3040 ARMASIdx_NS = 0,
3041 ARMASIdx_S = 1,
3042 ARMASIdx_TagNS = 2,
3043 ARMASIdx_TagS = 3,
3044} ARMASIdx;
3045
3046static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
3047{
3048
3049
3050
3051 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
3052}
3053
3054static inline bool arm_sctlr_b(CPUARMState *env)
3055{
3056 return
3057
3058
3059
3060
3061#ifndef CONFIG_USER_ONLY
3062 !arm_feature(env, ARM_FEATURE_V7) &&
3063#endif
3064 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
3065}
3066
3067uint64_t arm_sctlr(CPUARMState *env, int el);
3068
3069static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
3070 bool sctlr_b)
3071{
3072#ifdef CONFIG_USER_ONLY
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085 if (sctlr_b) {
3086 return true;
3087 }
3088#endif
3089
3090 return env->uncached_cpsr & CPSR_E;
3091}
3092
3093static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr)
3094{
3095 return sctlr & (el ? SCTLR_EE : SCTLR_E0E);
3096}
3097
3098
3099static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
3100{
3101 if (!is_a64(env)) {
3102 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env));
3103 } else {
3104 int cur_el = arm_current_el(env);
3105 uint64_t sctlr = arm_sctlr(env, cur_el);
3106 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr);
3107 }
3108}
3109
3110#include "exec/cpu-all.h"
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1)
3137FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1)
3138FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1)
3139FIELD(TBFLAG_ANY, BE_DATA, 3, 1)
3140FIELD(TBFLAG_ANY, MMUIDX, 4, 4)
3141
3142FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
3143
3144FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
3145FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
3146
3147
3148
3149
3150FIELD(TBFLAG_AM32, CONDEXEC, 24, 8)
3151FIELD(TBFLAG_AM32, THUMB, 23, 1)
3152
3153
3154
3155
3156FIELD(TBFLAG_A32, VECLEN, 0, 3)
3157FIELD(TBFLAG_A32, VECSTRIDE, 3, 2)
3158
3159
3160
3161
3162
3163
3164FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2)
3165FIELD(TBFLAG_A32, VFPEN, 7, 1)
3166FIELD(TBFLAG_A32, SCTLR__B, 8, 1)
3167FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1)
3168
3169
3170
3171
3172
3173FIELD(TBFLAG_A32, NS, 10, 1)
3174
3175
3176
3177
3178FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1)
3179
3180
3181
3182
3183
3184FIELD(TBFLAG_M32, HANDLER, 0, 1)
3185
3186FIELD(TBFLAG_M32, STACKCHECK, 1, 1)
3187
3188FIELD(TBFLAG_M32, LSPACT, 2, 1)
3189
3190FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1)
3191
3192FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1)
3193
3194FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1)
3195
3196
3197
3198
3199FIELD(TBFLAG_A64, TBII, 0, 2)
3200FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
3201
3202FIELD(TBFLAG_A64, VL, 4, 4)
3203FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
3204FIELD(TBFLAG_A64, BT, 9, 1)
3205FIELD(TBFLAG_A64, BTYPE, 10, 2)
3206FIELD(TBFLAG_A64, TBID, 12, 2)
3207FIELD(TBFLAG_A64, UNPRIV, 14, 1)
3208FIELD(TBFLAG_A64, ATA, 15, 1)
3209FIELD(TBFLAG_A64, TCMA, 16, 2)
3210FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
3211FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
3212FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2)
3213FIELD(TBFLAG_A64, PSTATE_SM, 22, 1)
3214FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
3215FIELD(TBFLAG_A64, SVL, 24, 4)
3216
3217FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1)
3218
3219
3220
3221
3222#define DP_TBFLAG_ANY(DST, WHICH, VAL) \
3223 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL))
3224#define DP_TBFLAG_A64(DST, WHICH, VAL) \
3225 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL))
3226#define DP_TBFLAG_A32(DST, WHICH, VAL) \
3227 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL))
3228#define DP_TBFLAG_M32(DST, WHICH, VAL) \
3229 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL))
3230#define DP_TBFLAG_AM32(DST, WHICH, VAL) \
3231 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL))
3232
3233#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH)
3234#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH)
3235#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH)
3236#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH)
3237#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH)
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
3248{
3249 return EX_TBFLAG_ANY(env->hflags, MMUIDX);
3250}
3251
3252
3253
3254
3255
3256
3257
3258static inline int sve_vq(CPUARMState *env)
3259{
3260 return EX_TBFLAG_A64(env->hflags, VL) + 1;
3261}
3262
3263
3264
3265
3266
3267
3268
3269static inline int sme_vq(CPUARMState *env)
3270{
3271 return EX_TBFLAG_A64(env->hflags, SVL) + 1;
3272}
3273
3274static inline bool bswap_code(bool sctlr_b)
3275{
3276#ifdef CONFIG_USER_ONLY
3277
3278
3279
3280
3281 return
3282#if TARGET_BIG_ENDIAN
3283 1 ^
3284#endif
3285 sctlr_b;
3286#else
3287
3288
3289
3290 return 0;
3291#endif
3292}
3293
3294#ifdef CONFIG_USER_ONLY
3295static inline bool arm_cpu_bswap_data(CPUARMState *env)
3296{
3297 return
3298#if TARGET_BIG_ENDIAN
3299 1 ^
3300#endif
3301 arm_cpu_data_is_big_endian(env);
3302}
3303#endif
3304
3305void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
3306 target_ulong *cs_base, uint32_t *flags);
3307
3308enum {
3309 QEMU_PSCI_CONDUIT_DISABLED = 0,
3310 QEMU_PSCI_CONDUIT_SMC = 1,
3311 QEMU_PSCI_CONDUIT_HVC = 2,
3312};
3313
3314#ifndef CONFIG_USER_ONLY
3315
3316static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
3317{
3318 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
3319}
3320
3321
3322
3323
3324
3325static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
3326{
3327 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
3328}
3329#endif
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
3342 void *opaque);
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
3354 *opaque);
3355
3356
3357
3358
3359
3360void arm_rebuild_hflags(CPUARMState *env);
3361
3362
3363
3364
3365
3366static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
3367{
3368 return &env->vfp.zregs[regno >> 1].d[regno & 1];
3369}
3370
3371
3372
3373
3374
3375static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
3376{
3377 return &env->vfp.zregs[regno].d[0];
3378}
3379
3380
3381
3382
3383
3384static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
3385{
3386 return &env->vfp.zregs[regno].d[0];
3387}
3388
3389
3390extern const uint64_t pred_esz_masks[5];
3391
3392
3393static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
3394{
3395 return x;
3396}
3397
3398
3399
3400
3401
3402
3403#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0)
3404#define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1)
3405
3406
3407
3408
3409
3410
3411#define PAGE_BTI PAGE_TARGET_1
3412#define PAGE_MTE PAGE_TARGET_2
3413#define PAGE_TARGET_STICKY PAGE_MTE
3414
3415#ifdef TARGET_TAGGED_ADDRESSES
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x)
3428{
3429 ARMCPU *cpu = ARM_CPU(cs);
3430 if (cpu->env.tagged_addr_enable) {
3431
3432
3433
3434
3435 x &= sextract64(x, 0, 56);
3436 }
3437 return x;
3438}
3439#endif
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id)
3461{
3462 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
3463}
3464
3465static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
3466{
3467 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
3468}
3469
3470static inline bool isar_feature_aa32_lob(const ARMISARegisters *id)
3471{
3472
3473 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3;
3474}
3475
3476static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
3477{
3478 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
3479}
3480
3481static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
3482{
3483 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
3484}
3485
3486static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id)
3487{
3488 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1;
3489}
3490
3491static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id)
3492{
3493 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0;
3494}
3495
3496static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id)
3497{
3498 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0;
3499}
3500
3501static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id)
3502{
3503 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0;
3504}
3505
3506static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id)
3507{
3508 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0;
3509}
3510
3511static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
3512{
3513 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
3514}
3515
3516static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
3517{
3518 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
3519}
3520
3521static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
3522{
3523 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
3524}
3525
3526static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
3527{
3528 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
3529}
3530
3531static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
3532{
3533 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
3534}
3535
3536static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
3537{
3538 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
3539}
3540
3541static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id)
3542{
3543 return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0;
3544}
3545
3546static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id)
3547{
3548 return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0;
3549}
3550
3551static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
3552{
3553 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0;
3554}
3555
3556static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
3557{
3558 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
3559}
3560
3561static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
3562{
3563
3564
3565
3566
3567 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3;
3568}
3569
3570static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
3571{
3572
3573 if (isar_feature_aa32_mprofile(id)) {
3574 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0;
3575 } else {
3576 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
3577 }
3578}
3579
3580static inline bool isar_feature_aa32_mve(const ARMISARegisters *id)
3581{
3582
3583
3584
3585
3586
3587 return isar_feature_aa32_mprofile(id) &&
3588 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0;
3589}
3590
3591static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id)
3592{
3593
3594
3595
3596
3597
3598 return isar_feature_aa32_mprofile(id) &&
3599 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2;
3600}
3601
3602static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
3603{
3604
3605
3606
3607
3608 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
3609}
3610
3611static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
3612{
3613
3614 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
3615}
3616
3617static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
3618{
3619 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
3620}
3621
3622static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id)
3623{
3624
3625 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;
3626}
3627
3628static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id)
3629{
3630
3631 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;
3632}
3633
3634static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
3635{
3636
3637 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
3638}
3639
3640static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
3641{
3642
3643 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
3644}
3645
3646static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id)
3647{
3648 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id);
3649}
3650
3651
3652
3653
3654
3655
3656static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
3657{
3658 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0;
3659}
3660
3661static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
3662{
3663 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
3664}
3665
3666
3667
3668
3669
3670
3671
3672
3673static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id)
3674{
3675 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0;
3676}
3677
3678static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
3679{
3680 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
3681}
3682
3683static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
3684{
3685 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2;
3686}
3687
3688static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
3689{
3690 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3;
3691}
3692
3693static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
3694{
3695 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
3696}
3697
3698static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id)
3699{
3700 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4;
3701}
3702
3703static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
3704{
3705 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
3706}
3707
3708static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
3709{
3710 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2;
3711}
3712
3713static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id)
3714{
3715
3716 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
3717 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3718}
3719
3720static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id)
3721{
3722
3723 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 &&
3724 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3725}
3726
3727static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
3728{
3729 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0;
3730}
3731
3732static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id)
3733{
3734 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0;
3735}
3736
3737static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
3738{
3739 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
3740}
3741
3742static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
3743{
3744 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
3745}
3746
3747static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
3748{
3749 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
3750}
3751
3752static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
3753{
3754 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
3755}
3756
3757static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id)
3758{
3759 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 5;
3760}
3761
3762static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id)
3763{
3764 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8;
3765}
3766
3767static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id)
3768{
3769 return FIELD_EX32(id->dbgdevid, DBGDEVID, DOUBLELOCK) > 0;
3770}
3771
3772
3773
3774
3775static inline bool isar_feature_aa64_aes(const ARMISARegisters *id)
3776{
3777 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0;
3778}
3779
3780static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id)
3781{
3782 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1;
3783}
3784
3785static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id)
3786{
3787 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0;
3788}
3789
3790static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id)
3791{
3792 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0;
3793}
3794
3795static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id)
3796{
3797 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1;
3798}
3799
3800static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id)
3801{
3802 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0;
3803}
3804
3805static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
3806{
3807 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0;
3808}
3809
3810static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)
3811{
3812 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0;
3813}
3814
3815static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id)
3816{
3817 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0;
3818}
3819
3820static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id)
3821{
3822 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0;
3823}
3824
3825static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id)
3826{
3827 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0;
3828}
3829
3830static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
3831{
3832 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
3833}
3834
3835static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
3836{
3837 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
3838}
3839
3840static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
3841{
3842 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
3843}
3844
3845static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
3846{
3847 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
3848}
3849
3850static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id)
3851{
3852 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0;
3853}
3854
3855static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
3856{
3857 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
3858}
3859
3860static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
3861{
3862 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
3863}
3864
3865static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
3866{
3867
3868
3869
3870
3871 return (id->id_aa64isar1 &
3872 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) |
3873 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) |
3874 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) |
3875 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
3876}
3877
3878static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id)
3879{
3880
3881
3882
3883
3884 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0;
3885}
3886
3887static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
3888{
3889 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
3890}
3891
3892static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
3893{
3894 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0;
3895}
3896
3897static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
3898{
3899 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
3900}
3901
3902static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
3903{
3904 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
3905}
3906
3907static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
3908{
3909 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
3910}
3911
3912static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id)
3913{
3914 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0;
3915}
3916
3917static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id)
3918{
3919 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
3920}
3921
3922static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id)
3923{
3924 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0;
3925}
3926
3927static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
3928{
3929
3930 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
3931}
3932
3933static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
3934{
3935
3936 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
3937}
3938
3939static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
3940{
3941 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
3942}
3943
3944static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
3945{
3946 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
3947}
3948
3949static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id)
3950{
3951 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2;
3952}
3953
3954static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
3955{
3956 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0;
3957}
3958
3959static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id)
3960{
3961 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2;
3962}
3963
3964static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
3965{
3966 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
3967}
3968
3969static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id)
3970{
3971 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0;
3972}
3973
3974static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
3975{
3976 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
3977}
3978
3979static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
3980{
3981 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
3982}
3983
3984static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
3985{
3986 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
3987}
3988
3989static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
3990{
3991 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
3992}
3993
3994static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id)
3995{
3996 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0;
3997}
3998
3999static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
4000{
4001 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
4002}
4003
4004static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
4005{
4006 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
4007}
4008
4009static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id)
4010{
4011 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0;
4012}
4013
4014static inline bool isar_feature_aa64_ids(const ARMISARegisters *id)
4015{
4016 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0;
4017}
4018
4019static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
4020{
4021 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
4022}
4023
4024static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
4025{
4026 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
4027}
4028
4029static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
4030{
4031 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
4032}
4033
4034static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)
4035{
4036 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0;
4037}
4038
4039static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id)
4040{
4041 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
4042 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
4043}
4044
4045static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id)
4046{
4047 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
4048 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
4049}
4050
4051static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
4052{
4053 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
4054}
4055
4056static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
4057{
4058 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
4059}
4060
4061static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
4062{
4063 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
4064}
4065
4066static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
4067{
4068 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1;
4069}
4070
4071static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id)
4072{
4073 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
4074 return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id));
4075}
4076
4077static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id)
4078{
4079 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2;
4080}
4081
4082static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id)
4083{
4084 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
4085 return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id));
4086}
4087
4088static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
4089{
4090 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
4091}
4092
4093static inline bool isar_feature_aa64_lva(const ARMISARegisters *id)
4094{
4095 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0;
4096}
4097
4098static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
4099{
4100 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
4101}
4102
4103static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
4104{
4105 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
4106}
4107
4108static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
4109{
4110 int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
4111 if (key >= 2) {
4112 return true;
4113 }
4114 if (key == 1) {
4115 key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
4116 return key >= 2;
4117 }
4118 return false;
4119}
4120
4121static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
4122{
4123 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
4124}
4125
4126static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
4127{
4128 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
4129}
4130
4131static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
4132{
4133 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
4134}
4135
4136static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id)
4137{
4138 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0;
4139}
4140
4141static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id)
4142{
4143 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2;
4144}
4145
4146static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id)
4147{
4148 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0;
4149}
4150
4151static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id)
4152{
4153 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0;
4154}
4155
4156static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id)
4157{
4158 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0;
4159}
4160
4161static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id)
4162{
4163 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0;
4164}
4165
4166static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)
4167{
4168 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0;
4169}
4170
4171static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id)
4172{
4173 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0;
4174}
4175
4176static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id)
4177{
4178 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0;
4179}
4180
4181static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id)
4182{
4183 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64);
4184}
4185
4186static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id)
4187{
4188 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf;
4189}
4190
4191static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id)
4192{
4193 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64);
4194}
4195
4196static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id)
4197{
4198 return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0;
4199}
4200
4201
4202
4203
4204static inline bool isar_feature_any_fp16(const ARMISARegisters *id)
4205{
4206 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id);
4207}
4208
4209static inline bool isar_feature_any_predinv(const ARMISARegisters *id)
4210{
4211 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id);
4212}
4213
4214static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id)
4215{
4216 return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id);
4217}
4218
4219static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id)
4220{
4221 return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id);
4222}
4223
4224static inline bool isar_feature_any_ccidx(const ARMISARegisters *id)
4225{
4226 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id);
4227}
4228
4229static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
4230{
4231 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
4232}
4233
4234static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id)
4235{
4236 return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id);
4237}
4238
4239static inline bool isar_feature_any_ras(const ARMISARegisters *id)
4240{
4241 return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id);
4242}
4243
4244
4245
4246
4247#define cpu_isar_feature(name, cpu) \
4248 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); })
4249
4250#endif
4251