LXR qemu/target/arm/cpu

   1/*
   2 * QEMU ARM TCG CPUs.
   3 *
   4 * Copyright (c) 2012 SUSE LINUX Products GmbH
   5 *
   6 * This code is licensed under the GNU GPL v2 or later.
   7 *
   8 * SPDX-License-Identifier: GPL-2.0-or-later
   9 */
  10
  11#include "qemu/osdep.h"
  12#include "cpu.h"
  13#ifdef CONFIG_TCG
  14#include "hw/core/tcg-cpu-ops.h"
  15#endif /* CONFIG_TCG */
  16#include "internals.h"
  17#include "target/arm/idau.h"
  18#if !defined(CONFIG_USER_ONLY)
  19#include "hw/boards.h"
  20#endif
  21#include "cpregs.h"
  22
  23
  24/* Share AArch32 -cpu max features with AArch64. */
  25void aa32_max_features(ARMCPU *cpu)
  26{
  27    uint32_t t;
  28
  29    /* Add additional features supported by QEMU */
  30    t = cpu->isar.id_isar5;
  31    t = FIELD_DP32(t, ID_ISAR5, AES, 2);          /* FEAT_PMULL */
  32    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);         /* FEAT_SHA1 */
  33    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);         /* FEAT_SHA256 */
  34    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
  35    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);          /* FEAT_RDM */
  36    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);         /* FEAT_FCMA */
  37    cpu->isar.id_isar5 = t;
  38
  39    t = cpu->isar.id_isar6;
  40    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);        /* FEAT_JSCVT */
  41    t = FIELD_DP32(t, ID_ISAR6, DP, 1);           /* Feat_DotProd */
  42    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);          /* FEAT_FHM */
  43    t = FIELD_DP32(t, ID_ISAR6, SB, 1);           /* FEAT_SB */
  44    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);      /* FEAT_SPECRES */
  45    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);         /* FEAT_AA32BF16 */
  46    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);         /* FEAT_AA32I8MM */
  47    cpu->isar.id_isar6 = t;
  48
  49    t = cpu->isar.mvfr1;
  50    t = FIELD_DP32(t, MVFR1, FPHP, 3);            /* FEAT_FP16 */
  51    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);          /* FEAT_FP16 */
  52    cpu->isar.mvfr1 = t;
  53
  54    t = cpu->isar.mvfr2;
  55    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3);        /* SIMD MaxNum */
  56    t = FIELD_DP32(t, MVFR2, FPMISC, 4);          /* FP MaxNum */
  57    cpu->isar.mvfr2 = t;
  58
  59    t = cpu->isar.id_mmfr3;
  60    t = FIELD_DP32(t, ID_MMFR3, PAN, 2);          /* FEAT_PAN2 */
  61    cpu->isar.id_mmfr3 = t;
  62
  63    t = cpu->isar.id_mmfr4;
  64    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1);         /* FEAT_AA32HPD */
  65    t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
  66    t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
  67    t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX*/
  68    cpu->isar.id_mmfr4 = t;
  69
  70    t = cpu->isar.id_pfr0;
  71    t = FIELD_DP32(t, ID_PFR0, CSV2, 2);          /* FEAT_CVS2 */
  72    t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
  73    t = FIELD_DP32(t, ID_PFR0, RAS, 1);           /* FEAT_RAS */
  74    cpu->isar.id_pfr0 = t;
  75
  76    t = cpu->isar.id_pfr2;
  77    t = FIELD_DP32(t, ID_PFR2, CSV3, 1);          /* FEAT_CSV3 */
  78    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);          /* FEAT_SSBS */
  79    cpu->isar.id_pfr2 = t;
  80
  81    t = cpu->isar.id_dfr0;
  82    t = FIELD_DP32(t, ID_DFR0, COPDBG, 9);        /* FEAT_Debugv8p4 */
  83    t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9);       /* FEAT_Debugv8p4 */
  84    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5);       /* FEAT_PMUv3p4 */
  85    cpu->isar.id_dfr0 = t;
  86}
  87
  88#ifndef CONFIG_USER_ONLY
  89static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
  90{
  91    ARMCPU *cpu = env_archcpu(env);
  92
  93    /* Number of cores is in [25:24]; otherwise we RAZ */
  94    return (cpu->core_count - 1) << 24;
  95}
  96
  97static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
  98    { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
  99      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
 100      .access = PL1_RW, .readfn = l2ctlr_read,
 101      .writefn = arm_cp_write_ignore },
 102    { .name = "L2CTLR",
 103      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
 104      .access = PL1_RW, .readfn = l2ctlr_read,
 105      .writefn = arm_cp_write_ignore },
 106    { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
 107      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
 108      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 109    { .name = "L2ECTLR",
 110      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
 111      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 112    { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
 113      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
 114      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 115    { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
 116      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
 117      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 118    { .name = "CPUACTLR",
 119      .cp = 15, .opc1 = 0, .crm = 15,
 120      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 121    { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
 122      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
 123      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 124    { .name = "CPUECTLR",
 125      .cp = 15, .opc1 = 1, .crm = 15,
 126      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 127    { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
 128      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
 129      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 130    { .name = "CPUMERRSR",
 131      .cp = 15, .opc1 = 2, .crm = 15,
 132      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 133    { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
 134      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
 135      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 136    { .name = "L2MERRSR",
 137      .cp = 15, .opc1 = 3, .crm = 15,
 138      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 139};
 140
 141void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
 142{
 143    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 144}
 145#endif /* !CONFIG_USER_ONLY */
 146
 147/* CPU models. These are not needed for the AArch64 linux-user build. */
 148#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 149
 150#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
 151static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 152{
 153    CPUClass *cc = CPU_GET_CLASS(cs);
 154    ARMCPU *cpu = ARM_CPU(cs);
 155    CPUARMState *env = &cpu->env;
 156    bool ret = false;
 157
 158    /*
 159     * ARMv7-M interrupt masking works differently than -A or -R.
 160     * There is no FIQ/IRQ distinction. Instead of I and F bits
 161     * masking FIQ and IRQ interrupts, an exception is taken only
 162     * if it is higher priority than the current execution priority
 163     * (which depends on state like BASEPRI, FAULTMASK and the
 164     * currently active exception).
 165     */
 166    if (interrupt_request & CPU_INTERRUPT_HARD
 167        && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
 168        cs->exception_index = EXCP_IRQ;
 169        cc->tcg_ops->do_interrupt(cs);
 170        ret = true;
 171    }
 172    return ret;
 173}
 174#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
 175
 176static void arm926_initfn(Object *obj)
 177{
 178    ARMCPU *cpu = ARM_CPU(obj);
 179
 180    cpu->dtb_compatible = "arm,arm926";
 181    set_feature(&cpu->env, ARM_FEATURE_V5);
 182    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 183    set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 184    cpu->midr = 0x41069265;
 185    cpu->reset_fpsid = 0x41011090;
 186    cpu->ctr = 0x1dd20d2;
 187    cpu->reset_sctlr = 0x00090078;
 188
 189    /*
 190     * ARMv5 does not have the ID_ISAR registers, but we can still
 191     * set the field to indicate Jazelle support within QEMU.
 192     */
 193    cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
 194    /*
 195     * Similarly, we need to set MVFR0 fields to enable vfp and short vector
 196     * support even though ARMv5 doesn't have this register.
 197     */
 198    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
 199    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
 200    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
 201}
 202
 203static void arm946_initfn(Object *obj)
 204{
 205    ARMCPU *cpu = ARM_CPU(obj);
 206
 207    cpu->dtb_compatible = "arm,arm946";
 208    set_feature(&cpu->env, ARM_FEATURE_V5);
 209    set_feature(&cpu->env, ARM_FEATURE_PMSA);
 210    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 211    cpu->midr = 0x41059461;
 212    cpu->ctr = 0x0f004006;
 213    cpu->reset_sctlr = 0x00000078;
 214}
 215
 216static void arm1026_initfn(Object *obj)
 217{
 218    ARMCPU *cpu = ARM_CPU(obj);
 219
 220    cpu->dtb_compatible = "arm,arm1026";
 221    set_feature(&cpu->env, ARM_FEATURE_V5);
 222    set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 223    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 224    set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 225    cpu->midr = 0x4106a262;
 226    cpu->reset_fpsid = 0x410110a0;
 227    cpu->ctr = 0x1dd20d2;
 228    cpu->reset_sctlr = 0x00090078;
 229    cpu->reset_auxcr = 1;
 230
 231    /*
 232     * ARMv5 does not have the ID_ISAR registers, but we can still
 233     * set the field to indicate Jazelle support within QEMU.
 234     */
 235    cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
 236    /*
 237     * Similarly, we need to set MVFR0 fields to enable vfp and short vector
 238     * support even though ARMv5 doesn't have this register.
 239     */
 240    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
 241    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
 242    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
 243
 244    {
 245        /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 246        ARMCPRegInfo ifar = {
 247            .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 248            .access = PL1_RW,
 249            .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
 250            .resetvalue = 0
 251        };
 252        define_one_arm_cp_reg(cpu, &ifar);
 253    }
 254}
 255
 256static void arm1136_r2_initfn(Object *obj)
 257{
 258    ARMCPU *cpu = ARM_CPU(obj);
 259    /*
 260     * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 261     * older core than plain "arm1136". In particular this does not
 262     * have the v6K features.
 263     * These ID register values are correct for 1136 but may be wrong
 264     * for 1136_r2 (in particular r0p2 does not actually implement most
 265     * of the ID registers).
 266     */
 267
 268    cpu->dtb_compatible = "arm,arm1136";
 269    set_feature(&cpu->env, ARM_FEATURE_V6);
 270    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 271    set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 272    set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 273    cpu->midr = 0x4107b362;
 274    cpu->reset_fpsid = 0x410120b4;
 275    cpu->isar.mvfr0 = 0x11111111;
 276    cpu->isar.mvfr1 = 0x00000000;
 277    cpu->ctr = 0x1dd20d2;
 278    cpu->reset_sctlr = 0x00050078;
 279    cpu->isar.id_pfr0 = 0x111;
 280    cpu->isar.id_pfr1 = 0x1;
 281    cpu->isar.id_dfr0 = 0x2;
 282    cpu->id_afr0 = 0x3;
 283    cpu->isar.id_mmfr0 = 0x01130003;
 284    cpu->isar.id_mmfr1 = 0x10030302;
 285    cpu->isar.id_mmfr2 = 0x01222110;
 286    cpu->isar.id_isar0 = 0x00140011;
 287    cpu->isar.id_isar1 = 0x12002111;
 288    cpu->isar.id_isar2 = 0x11231111;
 289    cpu->isar.id_isar3 = 0x01102131;
 290    cpu->isar.id_isar4 = 0x141;
 291    cpu->reset_auxcr = 7;
 292}
 293
 294static void arm1136_initfn(Object *obj)
 295{
 296    ARMCPU *cpu = ARM_CPU(obj);
 297
 298    cpu->dtb_compatible = "arm,arm1136";
 299    set_feature(&cpu->env, ARM_FEATURE_V6K);
 300    set_feature(&cpu->env, ARM_FEATURE_V6);
 301    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 302    set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 303    set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 304    cpu->midr = 0x4117b363;
 305    cpu->reset_fpsid = 0x410120b4;
 306    cpu->isar.mvfr0 = 0x11111111;
 307    cpu->isar.mvfr1 = 0x00000000;
 308    cpu->ctr = 0x1dd20d2;
 309    cpu->reset_sctlr = 0x00050078;
 310    cpu->isar.id_pfr0 = 0x111;
 311    cpu->isar.id_pfr1 = 0x1;
 312    cpu->isar.id_dfr0 = 0x2;
 313    cpu->id_afr0 = 0x3;
 314    cpu->isar.id_mmfr0 = 0x01130003;
 315    cpu->isar.id_mmfr1 = 0x10030302;
 316    cpu->isar.id_mmfr2 = 0x01222110;
 317    cpu->isar.id_isar0 = 0x00140011;
 318    cpu->isar.id_isar1 = 0x12002111;
 319    cpu->isar.id_isar2 = 0x11231111;
 320    cpu->isar.id_isar3 = 0x01102131;
 321    cpu->isar.id_isar4 = 0x141;
 322    cpu->reset_auxcr = 7;
 323}
 324
 325static void arm1176_initfn(Object *obj)
 326{
 327    ARMCPU *cpu = ARM_CPU(obj);
 328
 329    cpu->dtb_compatible = "arm,arm1176";
 330    set_feature(&cpu->env, ARM_FEATURE_V6K);
 331    set_feature(&cpu->env, ARM_FEATURE_VAPA);
 332    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 333    set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 334    set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 335    set_feature(&cpu->env, ARM_FEATURE_EL3);
 336    cpu->midr = 0x410fb767;
 337    cpu->reset_fpsid = 0x410120b5;
 338    cpu->isar.mvfr0 = 0x11111111;
 339    cpu->isar.mvfr1 = 0x00000000;
 340    cpu->ctr = 0x1dd20d2;
 341    cpu->reset_sctlr = 0x00050078;
 342    cpu->isar.id_pfr0 = 0x111;
 343    cpu->isar.id_pfr1 = 0x11;
 344    cpu->isar.id_dfr0 = 0x33;
 345    cpu->id_afr0 = 0;
 346    cpu->isar.id_mmfr0 = 0x01130003;
 347    cpu->isar.id_mmfr1 = 0x10030302;
 348    cpu->isar.id_mmfr2 = 0x01222100;
 349    cpu->isar.id_isar0 = 0x0140011;
 350    cpu->isar.id_isar1 = 0x12002111;
 351    cpu->isar.id_isar2 = 0x11231121;
 352    cpu->isar.id_isar3 = 0x01102131;
 353    cpu->isar.id_isar4 = 0x01141;
 354    cpu->reset_auxcr = 7;
 355}
 356
 357static void arm11mpcore_initfn(Object *obj)
 358{
 359    ARMCPU *cpu = ARM_CPU(obj);
 360
 361    cpu->dtb_compatible = "arm,arm11mpcore";
 362    set_feature(&cpu->env, ARM_FEATURE_V6K);
 363    set_feature(&cpu->env, ARM_FEATURE_VAPA);
 364    set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 365    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 366    cpu->midr = 0x410fb022;
 367    cpu->reset_fpsid = 0x410120b4;
 368    cpu->isar.mvfr0 = 0x11111111;
 369    cpu->isar.mvfr1 = 0x00000000;
 370    cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 371    cpu->isar.id_pfr0 = 0x111;
 372    cpu->isar.id_pfr1 = 0x1;
 373    cpu->isar.id_dfr0 = 0;
 374    cpu->id_afr0 = 0x2;
 375    cpu->isar.id_mmfr0 = 0x01100103;
 376    cpu->isar.id_mmfr1 = 0x10020302;
 377    cpu->isar.id_mmfr2 = 0x01222000;
 378    cpu->isar.id_isar0 = 0x00100011;
 379    cpu->isar.id_isar1 = 0x12002111;
 380    cpu->isar.id_isar2 = 0x11221011;
 381    cpu->isar.id_isar3 = 0x01102131;
 382    cpu->isar.id_isar4 = 0x141;
 383    cpu->reset_auxcr = 1;
 384}
 385
 386static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 387    { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 388      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 389    { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 390      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 391};
 392
 393static void cortex_a8_initfn(Object *obj)
 394{
 395    ARMCPU *cpu = ARM_CPU(obj);
 396
 397    cpu->dtb_compatible = "arm,cortex-a8";
 398    set_feature(&cpu->env, ARM_FEATURE_V7);
 399    set_feature(&cpu->env, ARM_FEATURE_NEON);
 400    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 401    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 402    set_feature(&cpu->env, ARM_FEATURE_EL3);
 403    cpu->midr = 0x410fc080;
 404    cpu->reset_fpsid = 0x410330c0;
 405    cpu->isar.mvfr0 = 0x11110222;
 406    cpu->isar.mvfr1 = 0x00011111;
 407    cpu->ctr = 0x82048004;
 408    cpu->reset_sctlr = 0x00c50078;
 409    cpu->isar.id_pfr0 = 0x1031;
 410    cpu->isar.id_pfr1 = 0x11;
 411    cpu->isar.id_dfr0 = 0x400;
 412    cpu->id_afr0 = 0;
 413    cpu->isar.id_mmfr0 = 0x31100003;
 414    cpu->isar.id_mmfr1 = 0x20000000;
 415    cpu->isar.id_mmfr2 = 0x01202000;
 416    cpu->isar.id_mmfr3 = 0x11;
 417    cpu->isar.id_isar0 = 0x00101111;
 418    cpu->isar.id_isar1 = 0x12112111;
 419    cpu->isar.id_isar2 = 0x21232031;
 420    cpu->isar.id_isar3 = 0x11112131;
 421    cpu->isar.id_isar4 = 0x00111142;
 422    cpu->isar.dbgdidr = 0x15141000;
 423    cpu->clidr = (1 << 27) | (2 << 24) | 3;
 424    cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 425    cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 426    cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 427    cpu->reset_auxcr = 2;
 428    cpu->isar.reset_pmcr_el0 = 0x41002000;
 429    define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 430}
 431
 432static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 433    /*
 434     * power_control should be set to maximum latency. Again,
 435     * default to 0 and set by private hook
 436     */
 437    { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 438      .access = PL1_RW, .resetvalue = 0,
 439      .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 440    { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 441      .access = PL1_RW, .resetvalue = 0,
 442      .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 443    { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 444      .access = PL1_RW, .resetvalue = 0,
 445      .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 446    { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 447      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 448    /* TLB lockdown control */
 449    { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 450      .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 451    { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 452      .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 453    { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 454      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 455    { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 456      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 457    { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 458      .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 459};
 460
 461static void cortex_a9_initfn(Object *obj)
 462{
 463    ARMCPU *cpu = ARM_CPU(obj);
 464
 465    cpu->dtb_compatible = "arm,cortex-a9";
 466    set_feature(&cpu->env, ARM_FEATURE_V7);
 467    set_feature(&cpu->env, ARM_FEATURE_NEON);
 468    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 469    set_feature(&cpu->env, ARM_FEATURE_EL3);
 470    /*
 471     * Note that A9 supports the MP extensions even for
 472     * A9UP and single-core A9MP (which are both different
 473     * and valid configurations; we don't model A9UP).
 474     */
 475    set_feature(&cpu->env, ARM_FEATURE_V7MP);
 476    set_feature(&cpu->env, ARM_FEATURE_CBAR);
 477    cpu->midr = 0x410fc090;
 478    cpu->reset_fpsid = 0x41033090;
 479    cpu->isar.mvfr0 = 0x11110222;
 480    cpu->isar.mvfr1 = 0x01111111;
 481    cpu->ctr = 0x80038003;
 482    cpu->reset_sctlr = 0x00c50078;
 483    cpu->isar.id_pfr0 = 0x1031;
 484    cpu->isar.id_pfr1 = 0x11;
 485    cpu->isar.id_dfr0 = 0x000;
 486    cpu->id_afr0 = 0;
 487    cpu->isar.id_mmfr0 = 0x00100103;
 488    cpu->isar.id_mmfr1 = 0x20000000;
 489    cpu->isar.id_mmfr2 = 0x01230000;
 490    cpu->isar.id_mmfr3 = 0x00002111;
 491    cpu->isar.id_isar0 = 0x00101111;
 492    cpu->isar.id_isar1 = 0x13112111;
 493    cpu->isar.id_isar2 = 0x21232041;
 494    cpu->isar.id_isar3 = 0x11112131;
 495    cpu->isar.id_isar4 = 0x00111142;
 496    cpu->isar.dbgdidr = 0x35141000;
 497    cpu->clidr = (1 << 27) | (1 << 24) | 3;
 498    cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
 499    cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
 500    cpu->isar.reset_pmcr_el0 = 0x41093000;
 501    define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 502}
 503
 504#ifndef CONFIG_USER_ONLY
 505static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 506{
 507    MachineState *ms = MACHINE(qdev_get_machine());
 508
 509    /*
 510     * Linux wants the number of processors from here.
 511     * Might as well set the interrupt-controller bit too.
 512     */
 513    return ((ms->smp.cpus - 1) << 24) | (1 << 23);
 514}
 515#endif
 516
 517static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 518#ifndef CONFIG_USER_ONLY
 519    { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 520      .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 521      .writefn = arm_cp_write_ignore, },
 522#endif
 523    { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 524      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 525};
 526
 527static void cortex_a7_initfn(Object *obj)
 528{
 529    ARMCPU *cpu = ARM_CPU(obj);
 530
 531    cpu->dtb_compatible = "arm,cortex-a7";
 532    set_feature(&cpu->env, ARM_FEATURE_V7VE);
 533    set_feature(&cpu->env, ARM_FEATURE_NEON);
 534    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 535    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 536    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 537    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 538    set_feature(&cpu->env, ARM_FEATURE_EL2);
 539    set_feature(&cpu->env, ARM_FEATURE_EL3);
 540    set_feature(&cpu->env, ARM_FEATURE_PMU);
 541    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
 542    cpu->midr = 0x410fc075;
 543    cpu->reset_fpsid = 0x41023075;
 544    cpu->isar.mvfr0 = 0x10110222;
 545    cpu->isar.mvfr1 = 0x11111111;
 546    cpu->ctr = 0x84448003;
 547    cpu->reset_sctlr = 0x00c50078;
 548    cpu->isar.id_pfr0 = 0x00001131;
 549    cpu->isar.id_pfr1 = 0x00011011;
 550    cpu->isar.id_dfr0 = 0x02010555;
 551    cpu->id_afr0 = 0x00000000;
 552    cpu->isar.id_mmfr0 = 0x10101105;
 553    cpu->isar.id_mmfr1 = 0x40000000;
 554    cpu->isar.id_mmfr2 = 0x01240000;
 555    cpu->isar.id_mmfr3 = 0x02102211;
 556    /*
 557     * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
 558     * table 4-41 gives 0x02101110, which includes the arm div insns.
 559     */
 560    cpu->isar.id_isar0 = 0x02101110;
 561    cpu->isar.id_isar1 = 0x13112111;
 562    cpu->isar.id_isar2 = 0x21232041;
 563    cpu->isar.id_isar3 = 0x11112131;
 564    cpu->isar.id_isar4 = 0x10011142;
 565    cpu->isar.dbgdidr = 0x3515f005;
 566    cpu->isar.dbgdevid = 0x01110f13;
 567    cpu->isar.dbgdevid1 = 0x1;
 568    cpu->clidr = 0x0a200023;
 569    cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 570    cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 571    cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 572    cpu->isar.reset_pmcr_el0 = 0x41072000;
 573    define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
 574}
 575
 576static void cortex_a15_initfn(Object *obj)
 577{
 578    ARMCPU *cpu = ARM_CPU(obj);
 579
 580    cpu->dtb_compatible = "arm,cortex-a15";
 581    set_feature(&cpu->env, ARM_FEATURE_V7VE);
 582    set_feature(&cpu->env, ARM_FEATURE_NEON);
 583    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 584    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 585    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 586    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 587    set_feature(&cpu->env, ARM_FEATURE_EL2);
 588    set_feature(&cpu->env, ARM_FEATURE_EL3);
 589    set_feature(&cpu->env, ARM_FEATURE_PMU);
 590    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 591    cpu->midr = 0x412fc0f1;
 592    cpu->reset_fpsid = 0x410430f0;
 593    cpu->isar.mvfr0 = 0x10110222;
 594    cpu->isar.mvfr1 = 0x11111111;
 595    cpu->ctr = 0x8444c004;
 596    cpu->reset_sctlr = 0x00c50078;
 597    cpu->isar.id_pfr0 = 0x00001131;
 598    cpu->isar.id_pfr1 = 0x00011011;
 599    cpu->isar.id_dfr0 = 0x02010555;
 600    cpu->id_afr0 = 0x00000000;
 601    cpu->isar.id_mmfr0 = 0x10201105;
 602    cpu->isar.id_mmfr1 = 0x20000000;
 603    cpu->isar.id_mmfr2 = 0x01240000;
 604    cpu->isar.id_mmfr3 = 0x02102211;
 605    cpu->isar.id_isar0 = 0x02101110;
 606    cpu->isar.id_isar1 = 0x13112111;
 607    cpu->isar.id_isar2 = 0x21232041;
 608    cpu->isar.id_isar3 = 0x11112131;
 609    cpu->isar.id_isar4 = 0x10011142;
 610    cpu->isar.dbgdidr = 0x3515f021;
 611    cpu->isar.dbgdevid = 0x01110f13;
 612    cpu->isar.dbgdevid1 = 0x0;
 613    cpu->clidr = 0x0a200023;
 614    cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 615    cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 616    cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 617    cpu->isar.reset_pmcr_el0 = 0x410F3000;
 618    define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 619}
 620
 621static void cortex_m0_initfn(Object *obj)
 622{
 623    ARMCPU *cpu = ARM_CPU(obj);
 624    set_feature(&cpu->env, ARM_FEATURE_V6);
 625    set_feature(&cpu->env, ARM_FEATURE_M);
 626
 627    cpu->midr = 0x410cc200;
 628
 629    /*
 630     * These ID register values are not guest visible, because
 631     * we do not implement the Main Extension. They must be set
 632     * to values corresponding to the Cortex-M0's implemented
 633     * features, because QEMU generally controls its emulation
 634     * by looking at ID register fields. We use the same values as
 635     * for the M3.
 636     */
 637    cpu->isar.id_pfr0 = 0x00000030;
 638    cpu->isar.id_pfr1 = 0x00000200;
 639    cpu->isar.id_dfr0 = 0x00100000;
 640    cpu->id_afr0 = 0x00000000;
 641    cpu->isar.id_mmfr0 = 0x00000030;
 642    cpu->isar.id_mmfr1 = 0x00000000;
 643    cpu->isar.id_mmfr2 = 0x00000000;
 644    cpu->isar.id_mmfr3 = 0x00000000;
 645    cpu->isar.id_isar0 = 0x01141110;
 646    cpu->isar.id_isar1 = 0x02111000;
 647    cpu->isar.id_isar2 = 0x21112231;
 648    cpu->isar.id_isar3 = 0x01111110;
 649    cpu->isar.id_isar4 = 0x01310102;
 650    cpu->isar.id_isar5 = 0x00000000;
 651    cpu->isar.id_isar6 = 0x00000000;
 652}
 653
 654static void cortex_m3_initfn(Object *obj)
 655{
 656    ARMCPU *cpu = ARM_CPU(obj);
 657    set_feature(&cpu->env, ARM_FEATURE_V7);
 658    set_feature(&cpu->env, ARM_FEATURE_M);
 659    set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 660    cpu->midr = 0x410fc231;
 661    cpu->pmsav7_dregion = 8;
 662    cpu->isar.id_pfr0 = 0x00000030;
 663    cpu->isar.id_pfr1 = 0x00000200;
 664    cpu->isar.id_dfr0 = 0x00100000;
 665    cpu->id_afr0 = 0x00000000;
 666    cpu->isar.id_mmfr0 = 0x00000030;
 667    cpu->isar.id_mmfr1 = 0x00000000;
 668    cpu->isar.id_mmfr2 = 0x00000000;
 669    cpu->isar.id_mmfr3 = 0x00000000;
 670    cpu->isar.id_isar0 = 0x01141110;
 671    cpu->isar.id_isar1 = 0x02111000;
 672    cpu->isar.id_isar2 = 0x21112231;
 673    cpu->isar.id_isar3 = 0x01111110;
 674    cpu->isar.id_isar4 = 0x01310102;
 675    cpu->isar.id_isar5 = 0x00000000;
 676    cpu->isar.id_isar6 = 0x00000000;
 677}
 678
 679static void cortex_m4_initfn(Object *obj)
 680{
 681    ARMCPU *cpu = ARM_CPU(obj);
 682
 683    set_feature(&cpu->env, ARM_FEATURE_V7);
 684    set_feature(&cpu->env, ARM_FEATURE_M);
 685    set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 686    set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 687    cpu->midr = 0x410fc240; /* r0p0 */
 688    cpu->pmsav7_dregion = 8;
 689    cpu->isar.mvfr0 = 0x10110021;
 690    cpu->isar.mvfr1 = 0x11000011;
 691    cpu->isar.mvfr2 = 0x00000000;
 692    cpu->isar.id_pfr0 = 0x00000030;
 693    cpu->isar.id_pfr1 = 0x00000200;
 694    cpu->isar.id_dfr0 = 0x00100000;
 695    cpu->id_afr0 = 0x00000000;
 696    cpu->isar.id_mmfr0 = 0x00000030;
 697    cpu->isar.id_mmfr1 = 0x00000000;
 698    cpu->isar.id_mmfr2 = 0x00000000;
 699    cpu->isar.id_mmfr3 = 0x00000000;
 700    cpu->isar.id_isar0 = 0x01141110;
 701    cpu->isar.id_isar1 = 0x02111000;
 702    cpu->isar.id_isar2 = 0x21112231;
 703    cpu->isar.id_isar3 = 0x01111110;
 704    cpu->isar.id_isar4 = 0x01310102;
 705    cpu->isar.id_isar5 = 0x00000000;
 706    cpu->isar.id_isar6 = 0x00000000;
 707}
 708
 709static void cortex_m7_initfn(Object *obj)
 710{
 711    ARMCPU *cpu = ARM_CPU(obj);
 712
 713    set_feature(&cpu->env, ARM_FEATURE_V7);
 714    set_feature(&cpu->env, ARM_FEATURE_M);
 715    set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 716    set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 717    cpu->midr = 0x411fc272; /* r1p2 */
 718    cpu->pmsav7_dregion = 8;
 719    cpu->isar.mvfr0 = 0x10110221;
 720    cpu->isar.mvfr1 = 0x12000011;
 721    cpu->isar.mvfr2 = 0x00000040;
 722    cpu->isar.id_pfr0 = 0x00000030;
 723    cpu->isar.id_pfr1 = 0x00000200;
 724    cpu->isar.id_dfr0 = 0x00100000;
 725    cpu->id_afr0 = 0x00000000;
 726    cpu->isar.id_mmfr0 = 0x00100030;
 727    cpu->isar.id_mmfr1 = 0x00000000;
 728    cpu->isar.id_mmfr2 = 0x01000000;
 729    cpu->isar.id_mmfr3 = 0x00000000;
 730    cpu->isar.id_isar0 = 0x01101110;
 731    cpu->isar.id_isar1 = 0x02112000;
 732    cpu->isar.id_isar2 = 0x20232231;
 733    cpu->isar.id_isar3 = 0x01111131;
 734    cpu->isar.id_isar4 = 0x01310132;
 735    cpu->isar.id_isar5 = 0x00000000;
 736    cpu->isar.id_isar6 = 0x00000000;
 737}
 738
 739static void cortex_m33_initfn(Object *obj)
 740{
 741    ARMCPU *cpu = ARM_CPU(obj);
 742
 743    set_feature(&cpu->env, ARM_FEATURE_V8);
 744    set_feature(&cpu->env, ARM_FEATURE_M);
 745    set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 746    set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
 747    set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 748    cpu->midr = 0x410fd213; /* r0p3 */
 749    cpu->pmsav7_dregion = 16;
 750    cpu->sau_sregion = 8;
 751    cpu->isar.mvfr0 = 0x10110021;
 752    cpu->isar.mvfr1 = 0x11000011;
 753    cpu->isar.mvfr2 = 0x00000040;
 754    cpu->isar.id_pfr0 = 0x00000030;
 755    cpu->isar.id_pfr1 = 0x00000210;
 756    cpu->isar.id_dfr0 = 0x00200000;
 757    cpu->id_afr0 = 0x00000000;
 758    cpu->isar.id_mmfr0 = 0x00101F40;
 759    cpu->isar.id_mmfr1 = 0x00000000;
 760    cpu->isar.id_mmfr2 = 0x01000000;
 761    cpu->isar.id_mmfr3 = 0x00000000;
 762    cpu->isar.id_isar0 = 0x01101110;
 763    cpu->isar.id_isar1 = 0x02212000;
 764    cpu->isar.id_isar2 = 0x20232232;
 765    cpu->isar.id_isar3 = 0x01111131;
 766    cpu->isar.id_isar4 = 0x01310132;
 767    cpu->isar.id_isar5 = 0x00000000;
 768    cpu->isar.id_isar6 = 0x00000000;
 769    cpu->clidr = 0x00000000;
 770    cpu->ctr = 0x8000c000;
 771}
 772
 773static void cortex_m55_initfn(Object *obj)
 774{
 775    ARMCPU *cpu = ARM_CPU(obj);
 776
 777    set_feature(&cpu->env, ARM_FEATURE_V8);
 778    set_feature(&cpu->env, ARM_FEATURE_V8_1M);
 779    set_feature(&cpu->env, ARM_FEATURE_M);
 780    set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 781    set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
 782    set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 783    cpu->midr = 0x410fd221; /* r0p1 */
 784    cpu->revidr = 0;
 785    cpu->pmsav7_dregion = 16;
 786    cpu->sau_sregion = 8;
 787    /* These are the MVFR* values for the FPU + full MVE configuration */
 788    cpu->isar.mvfr0 = 0x10110221;
 789    cpu->isar.mvfr1 = 0x12100211;
 790    cpu->isar.mvfr2 = 0x00000040;
 791    cpu->isar.id_pfr0 = 0x20000030;
 792    cpu->isar.id_pfr1 = 0x00000230;
 793    cpu->isar.id_dfr0 = 0x10200000;
 794    cpu->id_afr0 = 0x00000000;
 795    cpu->isar.id_mmfr0 = 0x00111040;
 796    cpu->isar.id_mmfr1 = 0x00000000;
 797    cpu->isar.id_mmfr2 = 0x01000000;
 798    cpu->isar.id_mmfr3 = 0x00000011;
 799    cpu->isar.id_isar0 = 0x01103110;
 800    cpu->isar.id_isar1 = 0x02212000;
 801    cpu->isar.id_isar2 = 0x20232232;
 802    cpu->isar.id_isar3 = 0x01111131;
 803    cpu->isar.id_isar4 = 0x01310132;
 804    cpu->isar.id_isar5 = 0x00000000;
 805    cpu->isar.id_isar6 = 0x00000000;
 806    cpu->clidr = 0x00000000; /* caches not implemented */
 807    cpu->ctr = 0x8303c003;
 808}
 809
 810static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
 811    /* Dummy the TCM region regs for the moment */
 812    { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
 813      .access = PL1_RW, .type = ARM_CP_CONST },
 814    { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
 815      .access = PL1_RW, .type = ARM_CP_CONST },
 816    { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
 817      .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
 818};
 819
 820static void cortex_r5_initfn(Object *obj)
 821{
 822    ARMCPU *cpu = ARM_CPU(obj);
 823
 824    set_feature(&cpu->env, ARM_FEATURE_V7);
 825    set_feature(&cpu->env, ARM_FEATURE_V7MP);
 826    set_feature(&cpu->env, ARM_FEATURE_PMSA);
 827    set_feature(&cpu->env, ARM_FEATURE_PMU);
 828    cpu->midr = 0x411fc153; /* r1p3 */
 829    cpu->isar.id_pfr0 = 0x0131;
 830    cpu->isar.id_pfr1 = 0x001;
 831    cpu->isar.id_dfr0 = 0x010400;
 832    cpu->id_afr0 = 0x0;
 833    cpu->isar.id_mmfr0 = 0x0210030;
 834    cpu->isar.id_mmfr1 = 0x00000000;
 835    cpu->isar.id_mmfr2 = 0x01200000;
 836    cpu->isar.id_mmfr3 = 0x0211;
 837    cpu->isar.id_isar0 = 0x02101111;
 838    cpu->isar.id_isar1 = 0x13112111;
 839    cpu->isar.id_isar2 = 0x21232141;
 840    cpu->isar.id_isar3 = 0x01112131;
 841    cpu->isar.id_isar4 = 0x0010142;
 842    cpu->isar.id_isar5 = 0x0;
 843    cpu->isar.id_isar6 = 0x0;
 844    cpu->mp_is_up = true;
 845    cpu->pmsav7_dregion = 16;
 846    cpu->isar.reset_pmcr_el0 = 0x41151800;
 847    define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
 848}
 849
 850static void cortex_r5f_initfn(Object *obj)
 851{
 852    ARMCPU *cpu = ARM_CPU(obj);
 853
 854    cortex_r5_initfn(obj);
 855    cpu->isar.mvfr0 = 0x10110221;
 856    cpu->isar.mvfr1 = 0x00000011;
 857}
 858
 859static void ti925t_initfn(Object *obj)
 860{
 861    ARMCPU *cpu = ARM_CPU(obj);
 862    set_feature(&cpu->env, ARM_FEATURE_V4T);
 863    set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 864    cpu->midr = ARM_CPUID_TI925T;
 865    cpu->ctr = 0x5109149;
 866    cpu->reset_sctlr = 0x00000070;
 867}
 868
 869static void sa1100_initfn(Object *obj)
 870{
 871    ARMCPU *cpu = ARM_CPU(obj);
 872
 873    cpu->dtb_compatible = "intel,sa1100";
 874    set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 875    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 876    cpu->midr = 0x4401A11B;
 877    cpu->reset_sctlr = 0x00000070;
 878}
 879
 880static void sa1110_initfn(Object *obj)
 881{
 882    ARMCPU *cpu = ARM_CPU(obj);
 883    set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 884    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 885    cpu->midr = 0x6901B119;
 886    cpu->reset_sctlr = 0x00000070;
 887}
 888
 889static void pxa250_initfn(Object *obj)
 890{
 891    ARMCPU *cpu = ARM_CPU(obj);
 892
 893    cpu->dtb_compatible = "marvell,xscale";
 894    set_feature(&cpu->env, ARM_FEATURE_V5);
 895    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 896    cpu->midr = 0x69052100;
 897    cpu->ctr = 0xd172172;
 898    cpu->reset_sctlr = 0x00000078;
 899}
 900
 901static void pxa255_initfn(Object *obj)
 902{
 903    ARMCPU *cpu = ARM_CPU(obj);
 904
 905    cpu->dtb_compatible = "marvell,xscale";
 906    set_feature(&cpu->env, ARM_FEATURE_V5);
 907    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 908    cpu->midr = 0x69052d00;
 909    cpu->ctr = 0xd172172;
 910    cpu->reset_sctlr = 0x00000078;
 911}
 912
 913static void pxa260_initfn(Object *obj)
 914{
 915    ARMCPU *cpu = ARM_CPU(obj);
 916
 917    cpu->dtb_compatible = "marvell,xscale";
 918    set_feature(&cpu->env, ARM_FEATURE_V5);
 919    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 920    cpu->midr = 0x69052903;
 921    cpu->ctr = 0xd172172;
 922    cpu->reset_sctlr = 0x00000078;
 923}
 924
 925static void pxa261_initfn(Object *obj)
 926{
 927    ARMCPU *cpu = ARM_CPU(obj);
 928
 929    cpu->dtb_compatible = "marvell,xscale";
 930    set_feature(&cpu->env, ARM_FEATURE_V5);
 931    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 932    cpu->midr = 0x69052d05;
 933    cpu->ctr = 0xd172172;
 934    cpu->reset_sctlr = 0x00000078;
 935}
 936
 937static void pxa262_initfn(Object *obj)
 938{
 939    ARMCPU *cpu = ARM_CPU(obj);
 940
 941    cpu->dtb_compatible = "marvell,xscale";
 942    set_feature(&cpu->env, ARM_FEATURE_V5);
 943    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 944    cpu->midr = 0x69052d06;
 945    cpu->ctr = 0xd172172;
 946    cpu->reset_sctlr = 0x00000078;
 947}
 948
 949static void pxa270a0_initfn(Object *obj)
 950{
 951    ARMCPU *cpu = ARM_CPU(obj);
 952
 953    cpu->dtb_compatible = "marvell,xscale";
 954    set_feature(&cpu->env, ARM_FEATURE_V5);
 955    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 956    set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 957    cpu->midr = 0x69054110;
 958    cpu->ctr = 0xd172172;
 959    cpu->reset_sctlr = 0x00000078;
 960}
 961
 962static void pxa270a1_initfn(Object *obj)
 963{
 964    ARMCPU *cpu = ARM_CPU(obj);
 965
 966    cpu->dtb_compatible = "marvell,xscale";
 967    set_feature(&cpu->env, ARM_FEATURE_V5);
 968    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 969    set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 970    cpu->midr = 0x69054111;
 971    cpu->ctr = 0xd172172;
 972    cpu->reset_sctlr = 0x00000078;
 973}
 974
 975static void pxa270b0_initfn(Object *obj)
 976{
 977    ARMCPU *cpu = ARM_CPU(obj);
 978
 979    cpu->dtb_compatible = "marvell,xscale";
 980    set_feature(&cpu->env, ARM_FEATURE_V5);
 981    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 982    set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 983    cpu->midr = 0x69054112;
 984    cpu->ctr = 0xd172172;
 985    cpu->reset_sctlr = 0x00000078;
 986}
 987
 988static void pxa270b1_initfn(Object *obj)
 989{
 990    ARMCPU *cpu = ARM_CPU(obj);
 991
 992    cpu->dtb_compatible = "marvell,xscale";
 993    set_feature(&cpu->env, ARM_FEATURE_V5);
 994    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 995    set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 996    cpu->midr = 0x69054113;
 997    cpu->ctr = 0xd172172;
 998    cpu->reset_sctlr = 0x00000078;
 999}
1000

1001static void pxa270c0_initfn(Object *obj)
1002{
1003    ARMCPU *cpu = ARM_CPU(obj);
1004
1005    cpu->dtb_compatible = "marvell,xscale";
1006    set_feature(&cpu->env, ARM_FEATURE_V5);
1007    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1008    set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1009    cpu->midr = 0x69054114;
1010    cpu->ctr = 0xd172172;
1011    cpu->reset_sctlr = 0x00000078;
1012}
1013
1014static void pxa270c5_initfn(Object *obj)
1015{
1016    ARMCPU *cpu = ARM_CPU(obj);
1017
1018    cpu->dtb_compatible = "marvell,xscale";
1019    set_feature(&cpu->env, ARM_FEATURE_V5);
1020    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1021    set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1022    cpu->midr = 0x69054117;
1023    cpu->ctr = 0xd172172;
1024    cpu->reset_sctlr = 0x00000078;
1025}
1026
1027#ifdef CONFIG_TCG
1028static const struct TCGCPUOps arm_v7m_tcg_ops = {
1029    .initialize = arm_translate_init,
1030    .synchronize_from_tb = arm_cpu_synchronize_from_tb,
1031    .debug_excp_handler = arm_debug_excp_handler,
1032
1033#ifdef CONFIG_USER_ONLY
1034    .record_sigsegv = arm_cpu_record_sigsegv,
1035    .record_sigbus = arm_cpu_record_sigbus,
1036#else
1037    .tlb_fill = arm_cpu_tlb_fill,
1038    .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
1039    .do_interrupt = arm_v7m_cpu_do_interrupt,
1040    .do_transaction_failed = arm_cpu_do_transaction_failed,
1041    .do_unaligned_access = arm_cpu_do_unaligned_access,
1042    .adjust_watchpoint_address = arm_adjust_watchpoint_address,
1043    .debug_check_watchpoint = arm_debug_check_watchpoint,
1044    .debug_check_breakpoint = arm_debug_check_breakpoint,
1045#endif /* !CONFIG_USER_ONLY */
1046};
1047#endif /* CONFIG_TCG */
1048
1049static void arm_v7m_class_init(ObjectClass *oc, void *data)
1050{
1051    ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1052    CPUClass *cc = CPU_CLASS(oc);
1053
1054    acc->info = data;
1055#ifdef CONFIG_TCG
1056    cc->tcg_ops = &arm_v7m_tcg_ops;
1057#endif /* CONFIG_TCG */
1058
1059    cc->gdb_core_xml_file = "arm-m-profile.xml";
1060}
1061
1062#ifndef TARGET_AARCH64
1063/*
1064 * -cpu max: a CPU with as many features enabled as our emulation supports.
1065 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
1066 * this only needs to handle 32 bits, and need not care about KVM.
1067 */
1068static void arm_max_initfn(Object *obj)
1069{
1070    ARMCPU *cpu = ARM_CPU(obj);
1071
1072    /* aarch64_a57_initfn, advertising none of the aarch64 features */
1073    cpu->dtb_compatible = "arm,cortex-a57";
1074    set_feature(&cpu->env, ARM_FEATURE_V8);
1075    set_feature(&cpu->env, ARM_FEATURE_NEON);
1076    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1077    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1078    set_feature(&cpu->env, ARM_FEATURE_EL2);
1079    set_feature(&cpu->env, ARM_FEATURE_EL3);
1080    set_feature(&cpu->env, ARM_FEATURE_PMU);
1081    cpu->midr = 0x411fd070;
1082    cpu->revidr = 0x00000000;
1083    cpu->reset_fpsid = 0x41034070;
1084    cpu->isar.mvfr0 = 0x10110222;
1085    cpu->isar.mvfr1 = 0x12111111;
1086    cpu->isar.mvfr2 = 0x00000043;
1087    cpu->ctr = 0x8444c004;
1088    cpu->reset_sctlr = 0x00c50838;
1089    cpu->isar.id_pfr0 = 0x00000131;
1090    cpu->isar.id_pfr1 = 0x00011011;
1091    cpu->isar.id_dfr0 = 0x03010066;
1092    cpu->id_afr0 = 0x00000000;
1093    cpu->isar.id_mmfr0 = 0x10101105;
1094    cpu->isar.id_mmfr1 = 0x40000000;
1095    cpu->isar.id_mmfr2 = 0x01260000;
1096    cpu->isar.id_mmfr3 = 0x02102211;
1097    cpu->isar.id_isar0 = 0x02101110;
1098    cpu->isar.id_isar1 = 0x13112111;
1099    cpu->isar.id_isar2 = 0x21232042;
1100    cpu->isar.id_isar3 = 0x01112131;
1101    cpu->isar.id_isar4 = 0x00011142;
1102    cpu->isar.id_isar5 = 0x00011121;
1103    cpu->isar.id_isar6 = 0;
1104    cpu->isar.dbgdidr = 0x3516d000;
1105    cpu->isar.dbgdevid = 0x00110f13;
1106    cpu->isar.dbgdevid1 = 0x2;
1107    cpu->isar.reset_pmcr_el0 = 0x41013000;
1108    cpu->clidr = 0x0a200023;
1109    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
1110    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
1111    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
1112    define_cortex_a72_a57_a53_cp_reginfo(cpu);
1113
1114    aa32_max_features(cpu);
1115
1116#ifdef CONFIG_USER_ONLY
1117    /*
1118     * Break with true ARMv8 and add back old-style VFP short-vector support.
1119     * Only do this for user-mode, where -cpu max is the default, so that
1120     * older v6 and v7 programs are more likely to work without adjustment.
1121     */
1122    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
1123#endif
1124}
1125#endif /* !TARGET_AARCH64 */
1126
1127static const ARMCPUInfo arm_tcg_cpus[] = {
1128    { .name = "arm926",      .initfn = arm926_initfn },
1129    { .name = "arm946",      .initfn = arm946_initfn },
1130    { .name = "arm1026",     .initfn = arm1026_initfn },
1131    /*
1132     * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1133     * older core than plain "arm1136". In particular this does not
1134     * have the v6K features.
1135     */
1136    { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1137    { .name = "arm1136",     .initfn = arm1136_initfn },
1138    { .name = "arm1176",     .initfn = arm1176_initfn },
1139    { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1140    { .name = "cortex-a7",   .initfn = cortex_a7_initfn },
1141    { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1142    { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1143    { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1144    { .name = "cortex-m0",   .initfn = cortex_m0_initfn,
1145                             .class_init = arm_v7m_class_init },
1146    { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1147                             .class_init = arm_v7m_class_init },
1148    { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
1149                             .class_init = arm_v7m_class_init },
1150    { .name = "cortex-m7",   .initfn = cortex_m7_initfn,
1151                             .class_init = arm_v7m_class_init },
1152    { .name = "cortex-m33",  .initfn = cortex_m33_initfn,
1153                             .class_init = arm_v7m_class_init },
1154    { .name = "cortex-m55",  .initfn = cortex_m55_initfn,
1155                             .class_init = arm_v7m_class_init },
1156    { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
1157    { .name = "cortex-r5f",  .initfn = cortex_r5f_initfn },
1158    { .name = "ti925t",      .initfn = ti925t_initfn },
1159    { .name = "sa1100",      .initfn = sa1100_initfn },
1160    { .name = "sa1110",      .initfn = sa1110_initfn },
1161    { .name = "pxa250",      .initfn = pxa250_initfn },
1162    { .name = "pxa255",      .initfn = pxa255_initfn },
1163    { .name = "pxa260",      .initfn = pxa260_initfn },
1164    { .name = "pxa261",      .initfn = pxa261_initfn },
1165    { .name = "pxa262",      .initfn = pxa262_initfn },
1166    /* "pxa270" is an alias for "pxa270-a0" */
1167    { .name = "pxa270",      .initfn = pxa270a0_initfn },
1168    { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1169    { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1170    { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1171    { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1172    { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1173    { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1174#ifndef TARGET_AARCH64
1175    { .name = "max",         .initfn = arm_max_initfn },
1176#endif
1177#ifdef CONFIG_USER_ONLY
1178    { .name = "any",         .initfn = arm_max_initfn },
1179#endif
1180};
1181
1182static const TypeInfo idau_interface_type_info = {
1183    .name = TYPE_IDAU_INTERFACE,
1184    .parent = TYPE_INTERFACE,
1185    .class_size = sizeof(IDAUInterfaceClass),
1186};
1187
1188static void arm_tcg_cpu_register_types(void)
1189{
1190    size_t i;
1191
1192    type_register_static(&idau_interface_type_info);
1193    for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
1194        arm_cpu_register(&arm_tcg_cpus[i]);
1195    }
1196}
1197
1198type_init(arm_tcg_cpu_register_types)
1199
1200#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */
1201