1
2
3
4
5
6
7
8#include "qemu/osdep.h"
9#include "qemu/log.h"
10#include "cpu.h"
11#include "internals.h"
12#include "cpregs.h"
13#include "exec/exec-all.h"
14#include "exec/helper-proto.h"
15
16
17
18static int arm_debug_target_el(CPUARMState *env)
19{
20 bool secure = arm_is_secure(env);
21 bool route_to_el2 = false;
22
23 if (arm_is_el2_enabled(env)) {
24 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
25 env->cp15.mdcr_el2 & MDCR_TDE;
26 }
27
28 if (route_to_el2) {
29 return 2;
30 } else if (arm_feature(env, ARM_FEATURE_EL3) &&
31 !arm_el_is_aa64(env, 3) && secure) {
32 return 3;
33 } else {
34 return 1;
35 }
36}
37
38
39
40
41
42G_NORETURN static void
43raise_exception_debug(CPUARMState *env, uint32_t excp, uint32_t syndrome)
44{
45 int debug_el = arm_debug_target_el(env);
46 int cur_el = arm_current_el(env);
47
48
49
50
51
52
53 assert(debug_el >= cur_el);
54 syndrome |= (debug_el == cur_el) << ARM_EL_EC_SHIFT;
55 raise_exception(env, excp, syndrome, debug_el);
56}
57
58
59static bool aa64_generate_debug_exceptions(CPUARMState *env)
60{
61 int cur_el = arm_current_el(env);
62 int debug_el;
63
64 if (cur_el == 3) {
65 return false;
66 }
67
68
69 if (arm_is_secure_below_el3(env)
70 && extract32(env->cp15.mdcr_el3, 16, 1)) {
71 return false;
72 }
73
74
75
76
77
78 debug_el = arm_debug_target_el(env);
79
80 if (cur_el == debug_el) {
81 return extract32(env->cp15.mdscr_el1, 13, 1)
82 && !(env->daif & PSTATE_D);
83 }
84
85
86 return debug_el > cur_el;
87}
88
89static bool aa32_generate_debug_exceptions(CPUARMState *env)
90{
91 int el = arm_current_el(env);
92
93 if (el == 0 && arm_el_is_aa64(env, 1)) {
94 return aa64_generate_debug_exceptions(env);
95 }
96
97 if (arm_is_secure(env)) {
98 int spd;
99
100 if (el == 0 && (env->cp15.sder & 1)) {
101
102
103
104
105
106 return true;
107 }
108
109 spd = extract32(env->cp15.mdcr_el3, 14, 2);
110 switch (spd) {
111 case 1:
112
113 case 0:
114
115
116
117
118
119
120 return true;
121 case 2:
122 return false;
123 case 3:
124 return true;
125 }
126 }
127
128 return el != 2;
129}
130
131
132
133
134
135
136
137
138
139
140
141
142
143bool arm_generate_debug_exceptions(CPUARMState *env)
144{
145 if ((env->cp15.oslsr_el1 & 1) || (env->cp15.osdlr_el1 & 1)) {
146 return false;
147 }
148 if (is_a64(env)) {
149 return aa64_generate_debug_exceptions(env);
150 } else {
151 return aa32_generate_debug_exceptions(env);
152 }
153}
154
155
156
157
158
159bool arm_singlestep_active(CPUARMState *env)
160{
161 return extract32(env->cp15.mdscr_el1, 0, 1)
162 && arm_el_is_aa64(env, arm_debug_target_el(env))
163 && arm_generate_debug_exceptions(env);
164}
165
166
167static bool linked_bp_matches(ARMCPU *cpu, int lbn)
168{
169 CPUARMState *env = &cpu->env;
170 uint64_t bcr = env->cp15.dbgbcr[lbn];
171 int brps = arm_num_brps(cpu);
172 int ctx_cmps = arm_num_ctx_cmps(cpu);
173 int bt;
174 uint32_t contextidr;
175 uint64_t hcr_el2;
176
177
178
179
180
181
182
183
184 if (lbn >= brps || lbn < (brps - ctx_cmps)) {
185 return false;
186 }
187
188 bcr = env->cp15.dbgbcr[lbn];
189
190 if (extract64(bcr, 0, 1) == 0) {
191
192 return false;
193 }
194
195 bt = extract64(bcr, 20, 4);
196 hcr_el2 = arm_hcr_el2_eff(env);
197
198 switch (bt) {
199 case 3:
200 switch (arm_current_el(env)) {
201 default:
202
203 return false;
204 case 2:
205 if (!(hcr_el2 & HCR_E2H)) {
206
207 return false;
208 }
209 contextidr = env->cp15.contextidr_el[2];
210 break;
211 case 1:
212 contextidr = env->cp15.contextidr_el[1];
213 break;
214 case 0:
215 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
216 contextidr = env->cp15.contextidr_el[2];
217 } else {
218 contextidr = env->cp15.contextidr_el[1];
219 }
220 break;
221 }
222 break;
223
224 case 7:
225 contextidr = env->cp15.contextidr_el[1];
226 break;
227 case 13:
228 contextidr = env->cp15.contextidr_el[2];
229 break;
230
231 case 9:
232 case 11:
233 case 15:
234 default:
235
236
237
238
239 return false;
240 }
241
242
243
244
245
246
247 return contextidr == (uint32_t)env->cp15.dbgbvr[lbn];
248}
249
250static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
251{
252 CPUARMState *env = &cpu->env;
253 uint64_t cr;
254 int pac, hmc, ssc, wt, lbn;
255
256
257
258
259 bool is_secure = arm_is_secure(env);
260 int access_el = arm_current_el(env);
261
262 if (is_wp) {
263 CPUWatchpoint *wp = env->cpu_watchpoint[n];
264
265 if (!wp || !(wp->flags & BP_WATCHPOINT_HIT)) {
266 return false;
267 }
268 cr = env->cp15.dbgwcr[n];
269 if (wp->hitattrs.user) {
270
271
272
273
274
275 access_el = 0;
276 }
277 } else {
278 uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
279
280 if (!env->cpu_breakpoint[n] || env->cpu_breakpoint[n]->pc != pc) {
281 return false;
282 }
283 cr = env->cp15.dbgbcr[n];
284 }
285
286
287
288
289
290
291
292
293
294
295
296
297
298 pac = FIELD_EX64(cr, DBGWCR, PAC);
299 hmc = FIELD_EX64(cr, DBGWCR, HMC);
300 ssc = FIELD_EX64(cr, DBGWCR, SSC);
301
302 switch (ssc) {
303 case 0:
304 break;
305 case 1:
306 case 3:
307 if (is_secure) {
308 return false;
309 }
310 break;
311 case 2:
312 if (!is_secure) {
313 return false;
314 }
315 break;
316 }
317
318 switch (access_el) {
319 case 3:
320 case 2:
321 if (!hmc) {
322 return false;
323 }
324 break;
325 case 1:
326 if (extract32(pac, 0, 1) == 0) {
327 return false;
328 }
329 break;
330 case 0:
331 if (extract32(pac, 1, 1) == 0) {
332 return false;
333 }
334 break;
335 default:
336 g_assert_not_reached();
337 }
338
339 wt = FIELD_EX64(cr, DBGWCR, WT);
340 lbn = FIELD_EX64(cr, DBGWCR, LBN);
341
342 if (wt && !linked_bp_matches(cpu, lbn)) {
343 return false;
344 }
345
346 return true;
347}
348
349static bool check_watchpoints(ARMCPU *cpu)
350{
351 CPUARMState *env = &cpu->env;
352 int n;
353
354
355
356
357
358 if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
359 || !arm_generate_debug_exceptions(env)) {
360 return false;
361 }
362
363 for (n = 0; n < ARRAY_SIZE(env->cpu_watchpoint); n++) {
364 if (bp_wp_matches(cpu, n, true)) {
365 return true;
366 }
367 }
368 return false;
369}
370
371bool arm_debug_check_breakpoint(CPUState *cs)
372{
373 ARMCPU *cpu = ARM_CPU(cs);
374 CPUARMState *env = &cpu->env;
375 target_ulong pc;
376 int n;
377
378
379
380
381
382 if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
383 || !arm_generate_debug_exceptions(env)) {
384 return false;
385 }
386
387
388
389
390
391 if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) {
392 return false;
393 }
394
395
396
397
398 pc = is_a64(env) ? env->pc : env->regs[15];
399 if ((is_a64(env) || !env->thumb) && (pc & 3) != 0) {
400 return false;
401 }
402
403
404
405
406
407
408
409 for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
410 if (bp_wp_matches(cpu, n, false)) {
411 return true;
412 }
413 }
414 return false;
415}
416
417bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
418{
419
420
421
422
423 ARMCPU *cpu = ARM_CPU(cs);
424
425 return check_watchpoints(cpu);
426}
427
428
429
430
431
432static uint32_t arm_debug_exception_fsr(CPUARMState *env)
433{
434 ARMMMUFaultInfo fi = { .type = ARMFault_Debug };
435 int target_el = arm_debug_target_el(env);
436 bool using_lpae = false;
437
438 if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
439 using_lpae = true;
440 } else {
441 if (arm_feature(env, ARM_FEATURE_LPAE) &&
442 (env->cp15.tcr_el[target_el] & TTBCR_EAE)) {
443 using_lpae = true;
444 }
445 }
446
447 if (using_lpae) {
448 return arm_fi_to_lfsc(&fi);
449 } else {
450 return arm_fi_to_sfsc(&fi);
451 }
452}
453
454void arm_debug_excp_handler(CPUState *cs)
455{
456
457
458
459
460 ARMCPU *cpu = ARM_CPU(cs);
461 CPUARMState *env = &cpu->env;
462 CPUWatchpoint *wp_hit = cs->watchpoint_hit;
463
464 if (wp_hit) {
465 if (wp_hit->flags & BP_CPU) {
466 bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0;
467
468 cs->watchpoint_hit = NULL;
469
470 env->exception.fsr = arm_debug_exception_fsr(env);
471 env->exception.vaddress = wp_hit->hitaddr;
472 raise_exception_debug(env, EXCP_DATA_ABORT,
473 syn_watchpoint(0, 0, wnr));
474 }
475 } else {
476 uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
477
478
479
480
481
482
483
484 if (cpu_breakpoint_test(cs, pc, BP_GDB)
485 || !cpu_breakpoint_test(cs, pc, BP_CPU)) {
486 return;
487 }
488
489 env->exception.fsr = arm_debug_exception_fsr(env);
490
491
492
493
494
495 env->exception.vaddress = 0;
496 raise_exception_debug(env, EXCP_PREFETCH_ABORT, syn_breakpoint(0));
497 }
498}
499
500
501
502
503
504void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome)
505{
506 int debug_el = arm_debug_target_el(env);
507 int cur_el = arm_current_el(env);
508
509
510 env->exception.fsr = arm_debug_exception_fsr(env);
511
512
513
514
515
516 env->exception.vaddress = 0;
517
518
519
520
521
522
523
524
525 if (debug_el < cur_el) {
526 debug_el = cur_el;
527 }
528 raise_exception(env, EXCP_BKPT, syndrome, debug_el);
529}
530
531void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome)
532{
533 raise_exception_debug(env, EXCP_UDEF, syndrome);
534}
535
536
537
538
539
540static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri,
541 bool isread)
542{
543 int el = arm_current_el(env);
544 uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
545 bool mdcr_el2_tdosa = (mdcr_el2 & MDCR_TDOSA) || (mdcr_el2 & MDCR_TDE) ||
546 (arm_hcr_el2_eff(env) & HCR_TGE);
547
548 if (el < 2 && mdcr_el2_tdosa) {
549 return CP_ACCESS_TRAP_EL2;
550 }
551 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) {
552 return CP_ACCESS_TRAP_EL3;
553 }
554 return CP_ACCESS_OK;
555}
556
557
558
559
560
561static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri,
562 bool isread)
563{
564 int el = arm_current_el(env);
565 uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
566 bool mdcr_el2_tdra = (mdcr_el2 & MDCR_TDRA) || (mdcr_el2 & MDCR_TDE) ||
567 (arm_hcr_el2_eff(env) & HCR_TGE);
568
569 if (el < 2 && mdcr_el2_tdra) {
570 return CP_ACCESS_TRAP_EL2;
571 }
572 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
573 return CP_ACCESS_TRAP_EL3;
574 }
575 return CP_ACCESS_OK;
576}
577
578
579
580
581
582static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
583 bool isread)
584{
585 int el = arm_current_el(env);
586 uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
587 bool mdcr_el2_tda = (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) ||
588 (arm_hcr_el2_eff(env) & HCR_TGE);
589
590 if (el < 2 && mdcr_el2_tda) {
591 return CP_ACCESS_TRAP_EL2;
592 }
593 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
594 return CP_ACCESS_TRAP_EL3;
595 }
596 return CP_ACCESS_OK;
597}
598
599static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
600 uint64_t value)
601{
602
603
604
605
606 int oslock;
607
608 if (ri->state == ARM_CP_STATE_AA32) {
609 oslock = (value == 0xC5ACCE55);
610 } else {
611 oslock = value & 1;
612 }
613
614 env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock);
615}
616
617static void osdlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
618 uint64_t value)
619{
620 ARMCPU *cpu = env_archcpu(env);
621
622
623
624
625 if(arm_feature(env, ARM_FEATURE_AARCH64)
626 ? cpu_isar_feature(aa64_doublelock, cpu)
627 : cpu_isar_feature(aa32_doublelock, cpu)) {
628 env->cp15.osdlr_el1 = value & 1;
629 }
630}
631
632static const ARMCPRegInfo debug_cp_reginfo[] = {
633
634
635
636
637
638
639
640 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
641 .access = PL0_R, .accessfn = access_tdra,
642 .type = ARM_CP_CONST, .resetvalue = 0 },
643 { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
644 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
645 .access = PL1_R, .accessfn = access_tdra,
646 .type = ARM_CP_CONST, .resetvalue = 0 },
647 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
648 .access = PL0_R, .accessfn = access_tdra,
649 .type = ARM_CP_CONST, .resetvalue = 0 },
650
651 { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
652 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
653 .access = PL1_RW, .accessfn = access_tda,
654 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
655 .resetvalue = 0 },
656
657
658
659
660 { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,
661 .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
662 .access = PL0_R, .accessfn = access_tda,
663 .type = ARM_CP_CONST, .resetvalue = 0 },
664
665
666
667
668
669 { .name = "DBGDSCRint", .state = ARM_CP_STATE_AA32,
670 .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
671 .type = ARM_CP_ALIAS,
672 .access = PL1_R, .accessfn = access_tda,
673 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
674 { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
675 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
676 .access = PL1_W, .type = ARM_CP_NO_RAW,
677 .accessfn = access_tdosa,
678 .writefn = oslar_write },
679 { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
680 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
681 .access = PL1_R, .resetvalue = 10,
682 .accessfn = access_tdosa,
683 .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
684
685 { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
686 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
687 .access = PL1_RW, .accessfn = access_tdosa,
688 .writefn = osdlr_write,
689 .fieldoffset = offsetof(CPUARMState, cp15.osdlr_el1) },
690
691
692
693
694 { .name = "DBGVCR",
695 .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
696 .access = PL1_RW, .accessfn = access_tda,
697 .type = ARM_CP_NOP },
698
699
700
701
702 { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
703 .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
704 .access = PL2_RW, .accessfn = access_tda,
705 .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP },
706
707
708
709
710
711 { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
712 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
713 .access = PL1_RW, .accessfn = access_tda,
714 .type = ARM_CP_NOP },
715};
716
717static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
718
719 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
720 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
721 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
722 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
723};
724
725void hw_watchpoint_update(ARMCPU *cpu, int n)
726{
727 CPUARMState *env = &cpu->env;
728 vaddr len = 0;
729 vaddr wvr = env->cp15.dbgwvr[n];
730 uint64_t wcr = env->cp15.dbgwcr[n];
731 int mask;
732 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
733
734 if (env->cpu_watchpoint[n]) {
735 cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
736 env->cpu_watchpoint[n] = NULL;
737 }
738
739 if (!FIELD_EX64(wcr, DBGWCR, E)) {
740
741 return;
742 }
743
744 switch (FIELD_EX64(wcr, DBGWCR, LSC)) {
745 case 0:
746
747 return;
748 case 1:
749 flags |= BP_MEM_READ;
750 break;
751 case 2:
752 flags |= BP_MEM_WRITE;
753 break;
754 case 3:
755 flags |= BP_MEM_ACCESS;
756 break;
757 }
758
759
760
761
762
763
764 mask = FIELD_EX64(wcr, DBGWCR, MASK);
765 if (mask == 1 || mask == 2) {
766
767
768
769
770
771 return;
772 } else if (mask) {
773
774 len = 1ULL << mask;
775
776
777
778
779
780 wvr &= ~(len - 1);
781 } else {
782
783 int bas = FIELD_EX64(wcr, DBGWCR, BAS);
784 int basstart;
785
786 if (extract64(wvr, 2, 1)) {
787
788
789
790
791 bas &= 0xf;
792 }
793
794 if (bas == 0) {
795
796 return;
797 }
798
799
800
801
802
803
804
805 basstart = ctz32(bas);
806 len = cto32(bas >> basstart);
807 wvr += basstart;
808 }
809
810 cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
811 &env->cpu_watchpoint[n]);
812}
813
814void hw_watchpoint_update_all(ARMCPU *cpu)
815{
816 int i;
817 CPUARMState *env = &cpu->env;
818
819
820
821
822
823 cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
824 memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
825
826 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
827 hw_watchpoint_update(cpu, i);
828 }
829}
830
831static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
832 uint64_t value)
833{
834 ARMCPU *cpu = env_archcpu(env);
835 int i = ri->crm;
836
837
838
839
840
841
842
843
844
845
846
847
848 value &= ~3ULL;
849
850 raw_write(env, ri, value);
851 hw_watchpoint_update(cpu, i);
852}
853
854static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
855 uint64_t value)
856{
857 ARMCPU *cpu = env_archcpu(env);
858 int i = ri->crm;
859
860 raw_write(env, ri, value);
861 hw_watchpoint_update(cpu, i);
862}
863
864void hw_breakpoint_update(ARMCPU *cpu, int n)
865{
866 CPUARMState *env = &cpu->env;
867 uint64_t bvr = env->cp15.dbgbvr[n];
868 uint64_t bcr = env->cp15.dbgbcr[n];
869 vaddr addr;
870 int bt;
871 int flags = BP_CPU;
872
873 if (env->cpu_breakpoint[n]) {
874 cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
875 env->cpu_breakpoint[n] = NULL;
876 }
877
878 if (!extract64(bcr, 0, 1)) {
879
880 return;
881 }
882
883 bt = extract64(bcr, 20, 4);
884
885 switch (bt) {
886 case 4:
887 case 5:
888 qemu_log_mask(LOG_UNIMP,
889 "arm: address mismatch breakpoint types not implemented\n");
890 return;
891 case 0:
892 case 1:
893 {
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918 int bas = extract64(bcr, 5, 4);
919 addr = bvr & ~3ULL;
920 if (bas == 0) {
921 return;
922 }
923 if (bas == 0xc) {
924 addr += 2;
925 }
926 break;
927 }
928 case 2:
929 case 8:
930 case 10:
931 qemu_log_mask(LOG_UNIMP,
932 "arm: unlinked context breakpoint types not implemented\n");
933 return;
934 case 9:
935 case 11:
936 case 3:
937 default:
938
939
940
941
942
943
944 return;
945 }
946
947 cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
948}
949
950void hw_breakpoint_update_all(ARMCPU *cpu)
951{
952 int i;
953 CPUARMState *env = &cpu->env;
954
955
956
957
958
959 cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
960 memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
961
962 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
963 hw_breakpoint_update(cpu, i);
964 }
965}
966
967static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
968 uint64_t value)
969{
970 ARMCPU *cpu = env_archcpu(env);
971 int i = ri->crm;
972
973 raw_write(env, ri, value);
974 hw_breakpoint_update(cpu, i);
975}
976
977static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
978 uint64_t value)
979{
980 ARMCPU *cpu = env_archcpu(env);
981 int i = ri->crm;
982
983
984
985
986
987 value = deposit64(value, 6, 1, extract64(value, 5, 1));
988 value = deposit64(value, 8, 1, extract64(value, 7, 1));
989
990 raw_write(env, ri, value);
991 hw_breakpoint_update(cpu, i);
992}
993
994void define_debug_regs(ARMCPU *cpu)
995{
996
997
998
999
1000 int i;
1001 int wrps, brps, ctx_cmps;
1002
1003
1004
1005
1006
1007
1008 if (cpu->isar.dbgdidr != 0) {
1009 ARMCPRegInfo dbgdidr = {
1010 .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0,
1011 .opc1 = 0, .opc2 = 0,
1012 .access = PL0_R, .accessfn = access_tda,
1013 .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr,
1014 };
1015 define_one_arm_cp_reg(cpu, &dbgdidr);
1016 }
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028 if (extract32(cpu->isar.dbgdidr, 15, 1)) {
1029 ARMCPRegInfo dbgdevid = {
1030 .name = "DBGDEVID",
1031 .cp = 14, .opc1 = 0, .crn = 7, .opc2 = 2, .crn = 7,
1032 .access = PL1_R, .accessfn = access_tda,
1033 .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdevid,
1034 };
1035 define_one_arm_cp_reg(cpu, &dbgdevid);
1036 }
1037 if (cpu_isar_feature(aa32_debugv7p1, cpu)) {
1038 ARMCPRegInfo dbgdevid12[] = {
1039 {
1040 .name = "DBGDEVID1",
1041 .cp = 14, .opc1 = 0, .crn = 7, .opc2 = 1, .crn = 7,
1042 .access = PL1_R, .accessfn = access_tda,
1043 .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdevid1,
1044 }, {
1045 .name = "DBGDEVID2",
1046 .cp = 14, .opc1 = 0, .crn = 7, .opc2 = 0, .crn = 7,
1047 .access = PL1_R, .accessfn = access_tda,
1048 .type = ARM_CP_CONST, .resetvalue = 0,
1049 },
1050 };
1051 define_arm_cp_regs(cpu, dbgdevid12);
1052 }
1053
1054 brps = arm_num_brps(cpu);
1055 wrps = arm_num_wrps(cpu);
1056 ctx_cmps = arm_num_ctx_cmps(cpu);
1057
1058 assert(ctx_cmps <= brps);
1059
1060 define_arm_cp_regs(cpu, debug_cp_reginfo);
1061
1062 if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
1063 define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
1064 }
1065
1066 for (i = 0; i < brps; i++) {
1067 char *dbgbvr_el1_name = g_strdup_printf("DBGBVR%d_EL1", i);
1068 char *dbgbcr_el1_name = g_strdup_printf("DBGBCR%d_EL1", i);
1069 ARMCPRegInfo dbgregs[] = {
1070 { .name = dbgbvr_el1_name, .state = ARM_CP_STATE_BOTH,
1071 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
1072 .access = PL1_RW, .accessfn = access_tda,
1073 .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
1074 .writefn = dbgbvr_write, .raw_writefn = raw_write
1075 },
1076 { .name = dbgbcr_el1_name, .state = ARM_CP_STATE_BOTH,
1077 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
1078 .access = PL1_RW, .accessfn = access_tda,
1079 .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
1080 .writefn = dbgbcr_write, .raw_writefn = raw_write
1081 },
1082 };
1083 define_arm_cp_regs(cpu, dbgregs);
1084 g_free(dbgbvr_el1_name);
1085 g_free(dbgbcr_el1_name);
1086 }
1087
1088 for (i = 0; i < wrps; i++) {
1089 char *dbgwvr_el1_name = g_strdup_printf("DBGWVR%d_EL1", i);
1090 char *dbgwcr_el1_name = g_strdup_printf("DBGWCR%d_EL1", i);
1091 ARMCPRegInfo dbgregs[] = {
1092 { .name = dbgwvr_el1_name, .state = ARM_CP_STATE_BOTH,
1093 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
1094 .access = PL1_RW, .accessfn = access_tda,
1095 .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
1096 .writefn = dbgwvr_write, .raw_writefn = raw_write
1097 },
1098 { .name = dbgwcr_el1_name, .state = ARM_CP_STATE_BOTH,
1099 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
1100 .access = PL1_RW, .accessfn = access_tda,
1101 .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
1102 .writefn = dbgwcr_write, .raw_writefn = raw_write
1103 },
1104 };
1105 define_arm_cp_regs(cpu, dbgregs);
1106 g_free(dbgwvr_el1_name);
1107 g_free(dbgwcr_el1_name);
1108 }
1109}
1110
1111#if !defined(CONFIG_USER_ONLY)
1112
1113vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
1114{
1115 ARMCPU *cpu = ARM_CPU(cs);
1116 CPUARMState *env = &cpu->env;
1117
1118
1119
1120
1121
1122
1123
1124
1125 if (arm_sctlr_b(env)) {
1126 if (len == 1) {
1127 addr ^= 3;
1128 } else if (len == 2) {
1129 addr ^= 2;
1130 }
1131 }
1132
1133 return addr;
1134}
1135
1136#endif
1137