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21#include "qemu/osdep.h"
22#include "qemu/log.h"
23#include "cpu.h"
24#include "hw/core/tcg-cpu-ops.h"
25#include "exec/exec-all.h"
26#include "exec/address-spaces.h"
27#include "exec/helper-proto.h"
28
29bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
30{
31 bool ret = false;
32 CPUClass *cc = CPU_GET_CLASS(cs);
33 AVRCPU *cpu = AVR_CPU(cs);
34 CPUAVRState *env = &cpu->env;
35
36 if (interrupt_request & CPU_INTERRUPT_RESET) {
37 if (cpu_interrupts_enabled(env)) {
38 cs->exception_index = EXCP_RESET;
39 cc->tcg_ops->do_interrupt(cs);
40
41 cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
42
43 ret = true;
44 }
45 }
46 if (interrupt_request & CPU_INTERRUPT_HARD) {
47 if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
48 int index = ctz32(env->intsrc);
49 cs->exception_index = EXCP_INT(index);
50 cc->tcg_ops->do_interrupt(cs);
51
52 env->intsrc &= env->intsrc - 1;
53 if (!env->intsrc) {
54 cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
55 }
56
57 ret = true;
58 }
59 }
60 return ret;
61}
62
63void avr_cpu_do_interrupt(CPUState *cs)
64{
65 AVRCPU *cpu = AVR_CPU(cs);
66 CPUAVRState *env = &cpu->env;
67
68 uint32_t ret = env->pc_w;
69 int vector = 0;
70 int size = avr_feature(env, AVR_FEATURE_JMP_CALL) ? 2 : 1;
71 int base = 0;
72
73 if (cs->exception_index == EXCP_RESET) {
74 vector = 0;
75 } else if (env->intsrc != 0) {
76 vector = ctz32(env->intsrc) + 1;
77 }
78
79 if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {
80 cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
81 cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
82 cpu_stb_data(env, env->sp--, (ret & 0xff0000) >> 16);
83 } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) {
84 cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
85 cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
86 } else {
87 cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
88 }
89
90 env->pc_w = base + vector * size;
91 env->sregI = 0;
92
93 cs->exception_index = -1;
94}
95
96hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
97{
98 return addr;
99}
100
101bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
102 MMUAccessType access_type, int mmu_idx,
103 bool probe, uintptr_t retaddr)
104{
105 int prot = 0;
106 MemTxAttrs attrs = {};
107 uint32_t paddr;
108
109 address &= TARGET_PAGE_MASK;
110
111 if (mmu_idx == MMU_CODE_IDX) {
112
113 paddr = OFFSET_CODE + address;
114 prot = PAGE_READ | PAGE_EXEC;
115 if (paddr + TARGET_PAGE_SIZE > OFFSET_DATA) {
116 error_report("execution left flash memory");
117 abort();
118 }
119 } else if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
120
121
122
123
124 AVRCPU *cpu = AVR_CPU(cs);
125 CPUAVRState *env = &cpu->env;
126 env->fullacc = 1;
127 cpu_loop_exit_restore(cs, retaddr);
128 } else {
129
130 paddr = OFFSET_DATA + address;
131 prot = PAGE_READ | PAGE_WRITE;
132 }
133
134 tlb_set_page_with_attrs(cs, address, paddr, attrs, prot,
135 mmu_idx, TARGET_PAGE_SIZE);
136
137 return true;
138}
139
140
141
142
143
144void helper_sleep(CPUAVRState *env)
145{
146 CPUState *cs = env_cpu(env);
147
148 cs->exception_index = EXCP_HLT;
149 cpu_loop_exit(cs);
150}
151
152void helper_unsupported(CPUAVRState *env)
153{
154 CPUState *cs = env_cpu(env);
155
156
157
158
159
160 cs->exception_index = EXCP_DEBUG;
161 if (qemu_loglevel_mask(LOG_UNIMP)) {
162 qemu_log("UNSUPPORTED\n");
163 cpu_dump_state(cs, stderr, 0);
164 }
165 cpu_loop_exit(cs);
166}
167
168void helper_debug(CPUAVRState *env)
169{
170 CPUState *cs = env_cpu(env);
171
172 cs->exception_index = EXCP_DEBUG;
173 cpu_loop_exit(cs);
174}
175
176void helper_break(CPUAVRState *env)
177{
178 CPUState *cs = env_cpu(env);
179
180 cs->exception_index = EXCP_DEBUG;
181 cpu_loop_exit(cs);
182}
183
184void helper_wdr(CPUAVRState *env)
185{
186 qemu_log_mask(LOG_UNIMP, "WDG reset (not implemented)\n");
187}
188
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195
196
197
198
199target_ulong helper_inb(CPUAVRState *env, uint32_t port)
200{
201 target_ulong data = 0;
202
203 switch (port) {
204 case 0x38:
205 data = 0xff & (env->rampD >> 16);
206 break;
207 case 0x39:
208 data = 0xff & (env->rampX >> 16);
209 break;
210 case 0x3a:
211 data = 0xff & (env->rampY >> 16);
212 break;
213 case 0x3b:
214 data = 0xff & (env->rampZ >> 16);
215 break;
216 case 0x3c:
217 data = 0xff & (env->eind >> 16);
218 break;
219 case 0x3d:
220 data = env->sp & 0x00ff;
221 break;
222 case 0x3e:
223 data = env->sp >> 8;
224 break;
225 case 0x3f:
226 data = cpu_get_sreg(env);
227 break;
228 default:
229
230 data = address_space_ldub(&address_space_memory,
231 OFFSET_IO_REGISTERS + port,
232 MEMTXATTRS_UNSPECIFIED, NULL);
233 }
234
235 return data;
236}
237
238
239
240
241
242
243
244
245
246
247
248void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data)
249{
250 data &= 0x000000ff;
251
252 switch (port) {
253 case 0x38:
254 if (avr_feature(env, AVR_FEATURE_RAMPD)) {
255 env->rampD = (data & 0xff) << 16;
256 }
257 break;
258 case 0x39:
259 if (avr_feature(env, AVR_FEATURE_RAMPX)) {
260 env->rampX = (data & 0xff) << 16;
261 }
262 break;
263 case 0x3a:
264 if (avr_feature(env, AVR_FEATURE_RAMPY)) {
265 env->rampY = (data & 0xff) << 16;
266 }
267 break;
268 case 0x3b:
269 if (avr_feature(env, AVR_FEATURE_RAMPZ)) {
270 env->rampZ = (data & 0xff) << 16;
271 }
272 break;
273 case 0x3c:
274 env->eind = (data & 0xff) << 16;
275 break;
276 case 0x3d:
277 env->sp = (env->sp & 0xff00) | (data);
278 break;
279 case 0x3e:
280 if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) {
281 env->sp = (env->sp & 0x00ff) | (data << 8);
282 }
283 break;
284 case 0x3f:
285 cpu_set_sreg(env, data);
286 break;
287 default:
288
289 address_space_stb(&address_space_memory, OFFSET_IO_REGISTERS + port,
290 data, MEMTXATTRS_UNSPECIFIED, NULL);
291 }
292}
293
294
295
296
297
298target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr)
299{
300 uint8_t data;
301
302 env->fullacc = false;
303
304 if (addr < NUMBER_OF_CPU_REGISTERS) {
305
306 data = env->r[addr];
307 } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
308
309 data = helper_inb(env, addr - NUMBER_OF_CPU_REGISTERS);
310 } else {
311
312 data = address_space_ldub(&address_space_memory, OFFSET_DATA + addr,
313 MEMTXATTRS_UNSPECIFIED, NULL);
314 }
315 return data;
316}
317
318
319
320
321
322void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr)
323{
324 env->fullacc = false;
325
326
327 assert(OFFSET_CPU_REGISTERS == OFFSET_DATA);
328 assert(OFFSET_IO_REGISTERS == OFFSET_CPU_REGISTERS +
329 NUMBER_OF_CPU_REGISTERS);
330
331 if (addr < NUMBER_OF_CPU_REGISTERS) {
332
333 env->r[addr] = data;
334 } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
335
336 helper_outb(env, addr - NUMBER_OF_CPU_REGISTERS, data);
337 } else {
338
339 address_space_stb(&address_space_memory, OFFSET_DATA + addr, data,
340 MEMTXATTRS_UNSPECIFIED, NULL);
341 }
342}
343