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20#ifndef I386_CPU_H
21#define I386_CPU_H
22
23#include "sysemu/tcg.h"
24#include "cpu-qom.h"
25#include "kvm/hyperv-proto.h"
26#include "exec/cpu-defs.h"
27#include "qapi/qapi-types-common.h"
28#include "qemu/cpu-float.h"
29
30
31#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
32
33#define KVM_HAVE_MCE_INJECTION 1
34
35
36
37#define TARGET_HAS_PRECISE_SMC
38
39#ifdef TARGET_X86_64
40#define I386_ELF_MACHINE EM_X86_64
41#define ELF_MACHINE_UNAME "x86_64"
42#else
43#define I386_ELF_MACHINE EM_386
44#define ELF_MACHINE_UNAME "i686"
45#endif
46
47enum {
48 R_EAX = 0,
49 R_ECX = 1,
50 R_EDX = 2,
51 R_EBX = 3,
52 R_ESP = 4,
53 R_EBP = 5,
54 R_ESI = 6,
55 R_EDI = 7,
56 R_R8 = 8,
57 R_R9 = 9,
58 R_R10 = 10,
59 R_R11 = 11,
60 R_R12 = 12,
61 R_R13 = 13,
62 R_R14 = 14,
63 R_R15 = 15,
64
65 R_AL = 0,
66 R_CL = 1,
67 R_DL = 2,
68 R_BL = 3,
69 R_AH = 4,
70 R_CH = 5,
71 R_DH = 6,
72 R_BH = 7,
73};
74
75typedef enum X86Seg {
76 R_ES = 0,
77 R_CS = 1,
78 R_SS = 2,
79 R_DS = 3,
80 R_FS = 4,
81 R_GS = 5,
82 R_LDTR = 6,
83 R_TR = 7,
84} X86Seg;
85
86
87#define DESC_G_SHIFT 23
88#define DESC_G_MASK (1 << DESC_G_SHIFT)
89#define DESC_B_SHIFT 22
90#define DESC_B_MASK (1 << DESC_B_SHIFT)
91#define DESC_L_SHIFT 21
92#define DESC_L_MASK (1 << DESC_L_SHIFT)
93#define DESC_AVL_SHIFT 20
94#define DESC_AVL_MASK (1 << DESC_AVL_SHIFT)
95#define DESC_P_SHIFT 15
96#define DESC_P_MASK (1 << DESC_P_SHIFT)
97#define DESC_DPL_SHIFT 13
98#define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
99#define DESC_S_SHIFT 12
100#define DESC_S_MASK (1 << DESC_S_SHIFT)
101#define DESC_TYPE_SHIFT 8
102#define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
103#define DESC_A_MASK (1 << 8)
104
105#define DESC_CS_MASK (1 << 11)
106#define DESC_C_MASK (1 << 10)
107#define DESC_R_MASK (1 << 9)
108
109#define DESC_E_MASK (1 << 10)
110#define DESC_W_MASK (1 << 9)
111
112#define DESC_TSS_BUSY_MASK (1 << 9)
113
114
115#define CC_C 0x0001
116#define CC_P 0x0004
117#define CC_A 0x0010
118#define CC_Z 0x0040
119#define CC_S 0x0080
120#define CC_O 0x0800
121
122#define TF_SHIFT 8
123#define IOPL_SHIFT 12
124#define VM_SHIFT 17
125
126#define TF_MASK 0x00000100
127#define IF_MASK 0x00000200
128#define DF_MASK 0x00000400
129#define IOPL_MASK 0x00003000
130#define NT_MASK 0x00004000
131#define RF_MASK 0x00010000
132#define VM_MASK 0x00020000
133#define AC_MASK 0x00040000
134#define VIF_MASK 0x00080000
135#define VIP_MASK 0x00100000
136#define ID_MASK 0x00200000
137
138
139
140
141
142
143#define HF_CPL_SHIFT 0
144
145#define HF_INHIBIT_IRQ_SHIFT 3
146
147#define HF_CS32_SHIFT 4
148#define HF_SS32_SHIFT 5
149
150#define HF_ADDSEG_SHIFT 6
151
152#define HF_PE_SHIFT 7
153#define HF_TF_SHIFT 8
154#define HF_MP_SHIFT 9
155#define HF_EM_SHIFT 10
156#define HF_TS_SHIFT 11
157#define HF_IOPL_SHIFT 12
158#define HF_LMA_SHIFT 14
159#define HF_CS64_SHIFT 15
160#define HF_RF_SHIFT 16
161#define HF_VM_SHIFT 17
162#define HF_AC_SHIFT 18
163#define HF_SMM_SHIFT 19
164#define HF_SVME_SHIFT 20
165#define HF_GUEST_SHIFT 21
166#define HF_OSFXSR_SHIFT 22
167#define HF_SMAP_SHIFT 23
168#define HF_IOBPT_SHIFT 24
169#define HF_MPX_EN_SHIFT 25
170#define HF_MPX_IU_SHIFT 26
171#define HF_UMIP_SHIFT 27
172
173#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
174#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
175#define HF_CS32_MASK (1 << HF_CS32_SHIFT)
176#define HF_SS32_MASK (1 << HF_SS32_SHIFT)
177#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
178#define HF_PE_MASK (1 << HF_PE_SHIFT)
179#define HF_TF_MASK (1 << HF_TF_SHIFT)
180#define HF_MP_MASK (1 << HF_MP_SHIFT)
181#define HF_EM_MASK (1 << HF_EM_SHIFT)
182#define HF_TS_MASK (1 << HF_TS_SHIFT)
183#define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
184#define HF_LMA_MASK (1 << HF_LMA_SHIFT)
185#define HF_CS64_MASK (1 << HF_CS64_SHIFT)
186#define HF_RF_MASK (1 << HF_RF_SHIFT)
187#define HF_VM_MASK (1 << HF_VM_SHIFT)
188#define HF_AC_MASK (1 << HF_AC_SHIFT)
189#define HF_SMM_MASK (1 << HF_SMM_SHIFT)
190#define HF_SVME_MASK (1 << HF_SVME_SHIFT)
191#define HF_GUEST_MASK (1 << HF_GUEST_SHIFT)
192#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
193#define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
194#define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
195#define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
196#define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
197#define HF_UMIP_MASK (1 << HF_UMIP_SHIFT)
198
199
200
201#define HF2_GIF_SHIFT 0
202#define HF2_HIF_SHIFT 1
203#define HF2_NMI_SHIFT 2
204#define HF2_VINTR_SHIFT 3
205#define HF2_SMM_INSIDE_NMI_SHIFT 4
206#define HF2_MPX_PR_SHIFT 5
207#define HF2_NPT_SHIFT 6
208#define HF2_IGNNE_SHIFT 7
209#define HF2_VGIF_SHIFT 8
210
211#define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
212#define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
213#define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
214#define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
215#define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
216#define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
217#define HF2_NPT_MASK (1 << HF2_NPT_SHIFT)
218#define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT)
219#define HF2_VGIF_MASK (1 << HF2_VGIF_SHIFT)
220
221#define CR0_PE_SHIFT 0
222#define CR0_MP_SHIFT 1
223
224#define CR0_PE_MASK (1U << 0)
225#define CR0_MP_MASK (1U << 1)
226#define CR0_EM_MASK (1U << 2)
227#define CR0_TS_MASK (1U << 3)
228#define CR0_ET_MASK (1U << 4)
229#define CR0_NE_MASK (1U << 5)
230#define CR0_WP_MASK (1U << 16)
231#define CR0_AM_MASK (1U << 18)
232#define CR0_NW_MASK (1U << 29)
233#define CR0_CD_MASK (1U << 30)
234#define CR0_PG_MASK (1U << 31)
235
236#define CR4_VME_MASK (1U << 0)
237#define CR4_PVI_MASK (1U << 1)
238#define CR4_TSD_MASK (1U << 2)
239#define CR4_DE_MASK (1U << 3)
240#define CR4_PSE_MASK (1U << 4)
241#define CR4_PAE_MASK (1U << 5)
242#define CR4_MCE_MASK (1U << 6)
243#define CR4_PGE_MASK (1U << 7)
244#define CR4_PCE_MASK (1U << 8)
245#define CR4_OSFXSR_SHIFT 9
246#define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
247#define CR4_OSXMMEXCPT_MASK (1U << 10)
248#define CR4_UMIP_MASK (1U << 11)
249#define CR4_LA57_MASK (1U << 12)
250#define CR4_VMXE_MASK (1U << 13)
251#define CR4_SMXE_MASK (1U << 14)
252#define CR4_FSGSBASE_MASK (1U << 16)
253#define CR4_PCIDE_MASK (1U << 17)
254#define CR4_OSXSAVE_MASK (1U << 18)
255#define CR4_SMEP_MASK (1U << 20)
256#define CR4_SMAP_MASK (1U << 21)
257#define CR4_PKE_MASK (1U << 22)
258#define CR4_PKS_MASK (1U << 24)
259
260#define CR4_RESERVED_MASK \
261(~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \
262 | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \
263 | CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \
264 | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \
265 | CR4_LA57_MASK \
266 | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \
267 | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK))
268
269#define DR6_BD (1 << 13)
270#define DR6_BS (1 << 14)
271#define DR6_BT (1 << 15)
272#define DR6_FIXED_1 0xffff0ff0
273
274#define DR7_GD (1 << 13)
275#define DR7_TYPE_SHIFT 16
276#define DR7_LEN_SHIFT 18
277#define DR7_FIXED_1 0x00000400
278#define DR7_GLOBAL_BP_MASK 0xaa
279#define DR7_LOCAL_BP_MASK 0x55
280#define DR7_MAX_BP 4
281#define DR7_TYPE_BP_INST 0x0
282#define DR7_TYPE_DATA_WR 0x1
283#define DR7_TYPE_IO_RW 0x2
284#define DR7_TYPE_DATA_RW 0x3
285
286#define DR_RESERVED_MASK 0xffffffff00000000ULL
287
288#define PG_PRESENT_BIT 0
289#define PG_RW_BIT 1
290#define PG_USER_BIT 2
291#define PG_PWT_BIT 3
292#define PG_PCD_BIT 4
293#define PG_ACCESSED_BIT 5
294#define PG_DIRTY_BIT 6
295#define PG_PSE_BIT 7
296#define PG_GLOBAL_BIT 8
297#define PG_PSE_PAT_BIT 12
298#define PG_PKRU_BIT 59
299#define PG_NX_BIT 63
300
301#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
302#define PG_RW_MASK (1 << PG_RW_BIT)
303#define PG_USER_MASK (1 << PG_USER_BIT)
304#define PG_PWT_MASK (1 << PG_PWT_BIT)
305#define PG_PCD_MASK (1 << PG_PCD_BIT)
306#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
307#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
308#define PG_PSE_MASK (1 << PG_PSE_BIT)
309#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
310#define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
311#define PG_ADDRESS_MASK 0x000ffffffffff000LL
312#define PG_HI_USER_MASK 0x7ff0000000000000LL
313#define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
314#define PG_NX_MASK (1ULL << PG_NX_BIT)
315
316#define PG_ERROR_W_BIT 1
317
318#define PG_ERROR_P_MASK 0x01
319#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
320#define PG_ERROR_U_MASK 0x04
321#define PG_ERROR_RSVD_MASK 0x08
322#define PG_ERROR_I_D_MASK 0x10
323#define PG_ERROR_PK_MASK 0x20
324
325#define PG_MODE_PAE (1 << 0)
326#define PG_MODE_LMA (1 << 1)
327#define PG_MODE_NXE (1 << 2)
328#define PG_MODE_PSE (1 << 3)
329#define PG_MODE_LA57 (1 << 4)
330#define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15)
331
332
333#define PG_MODE_WP (1 << 16)
334#define PG_MODE_PKE (1 << 17)
335#define PG_MODE_PKS (1 << 18)
336#define PG_MODE_SMEP (1 << 19)
337
338#define MCG_CTL_P (1ULL<<8)
339#define MCG_SER_P (1ULL<<24)
340#define MCG_LMCE_P (1ULL<<27)
341
342#define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
343#define MCE_BANKS_DEF 10
344
345#define MCG_CAP_BANKS_MASK 0xff
346
347#define MCG_STATUS_RIPV (1ULL<<0)
348#define MCG_STATUS_EIPV (1ULL<<1)
349#define MCG_STATUS_MCIP (1ULL<<2)
350#define MCG_STATUS_LMCE (1ULL<<3)
351
352#define MCG_EXT_CTL_LMCE_EN (1ULL<<0)
353
354#define MCI_STATUS_VAL (1ULL<<63)
355#define MCI_STATUS_OVER (1ULL<<62)
356#define MCI_STATUS_UC (1ULL<<61)
357#define MCI_STATUS_EN (1ULL<<60)
358#define MCI_STATUS_MISCV (1ULL<<59)
359#define MCI_STATUS_ADDRV (1ULL<<58)
360#define MCI_STATUS_PCC (1ULL<<57)
361#define MCI_STATUS_S (1ULL<<56)
362#define MCI_STATUS_AR (1ULL<<55)
363
364
365#define MCM_ADDR_SEGOFF 0
366#define MCM_ADDR_LINEAR 1
367#define MCM_ADDR_PHYS 2
368#define MCM_ADDR_MEM 3
369#define MCM_ADDR_GENERIC 7
370
371#define MSR_IA32_TSC 0x10
372#define MSR_IA32_APICBASE 0x1b
373#define MSR_IA32_APICBASE_BSP (1<<8)
374#define MSR_IA32_APICBASE_ENABLE (1<<11)
375#define MSR_IA32_APICBASE_EXTD (1 << 10)
376#define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
377#define MSR_IA32_FEATURE_CONTROL 0x0000003a
378#define MSR_TSC_ADJUST 0x0000003b
379#define MSR_IA32_SPEC_CTRL 0x48
380#define MSR_VIRT_SSBD 0xc001011f
381#define MSR_IA32_PRED_CMD 0x49
382#define MSR_IA32_UCODE_REV 0x8b
383#define MSR_IA32_CORE_CAPABILITY 0xcf
384
385#define MSR_IA32_ARCH_CAPABILITIES 0x10a
386#define ARCH_CAP_TSX_CTRL_MSR (1<<7)
387
388#define MSR_IA32_PERF_CAPABILITIES 0x345
389#define PERF_CAP_LBR_FMT 0x3f
390
391#define MSR_IA32_TSX_CTRL 0x122
392#define MSR_IA32_TSCDEADLINE 0x6e0
393#define MSR_IA32_PKRS 0x6e1
394#define MSR_ARCH_LBR_CTL 0x000014ce
395#define MSR_ARCH_LBR_DEPTH 0x000014cf
396#define MSR_ARCH_LBR_FROM_0 0x00001500
397#define MSR_ARCH_LBR_TO_0 0x00001600
398#define MSR_ARCH_LBR_INFO_0 0x00001200
399
400#define FEATURE_CONTROL_LOCKED (1<<0)
401#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1ULL << 1)
402#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
403#define FEATURE_CONTROL_SGX_LC (1ULL << 17)
404#define FEATURE_CONTROL_SGX (1ULL << 18)
405#define FEATURE_CONTROL_LMCE (1<<20)
406
407#define MSR_IA32_SGXLEPUBKEYHASH0 0x8c
408#define MSR_IA32_SGXLEPUBKEYHASH1 0x8d
409#define MSR_IA32_SGXLEPUBKEYHASH2 0x8e
410#define MSR_IA32_SGXLEPUBKEYHASH3 0x8f
411
412#define MSR_P6_PERFCTR0 0xc1
413
414#define MSR_IA32_SMBASE 0x9e
415#define MSR_SMI_COUNT 0x34
416#define MSR_CORE_THREAD_COUNT 0x35
417#define MSR_MTRRcap 0xfe
418#define MSR_MTRRcap_VCNT 8
419#define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
420#define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
421
422#define MSR_IA32_SYSENTER_CS 0x174
423#define MSR_IA32_SYSENTER_ESP 0x175
424#define MSR_IA32_SYSENTER_EIP 0x176
425
426#define MSR_MCG_CAP 0x179
427#define MSR_MCG_STATUS 0x17a
428#define MSR_MCG_CTL 0x17b
429#define MSR_MCG_EXT_CTL 0x4d0
430
431#define MSR_P6_EVNTSEL0 0x186
432
433#define MSR_IA32_PERF_STATUS 0x198
434
435#define MSR_IA32_MISC_ENABLE 0x1a0
436
437#define MSR_IA32_MISC_ENABLE_DEFAULT 1
438#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
439
440#define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
441#define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
442
443#define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
444
445#define MSR_MTRRfix64K_00000 0x250
446#define MSR_MTRRfix16K_80000 0x258
447#define MSR_MTRRfix16K_A0000 0x259
448#define MSR_MTRRfix4K_C0000 0x268
449#define MSR_MTRRfix4K_C8000 0x269
450#define MSR_MTRRfix4K_D0000 0x26a
451#define MSR_MTRRfix4K_D8000 0x26b
452#define MSR_MTRRfix4K_E0000 0x26c
453#define MSR_MTRRfix4K_E8000 0x26d
454#define MSR_MTRRfix4K_F0000 0x26e
455#define MSR_MTRRfix4K_F8000 0x26f
456
457#define MSR_PAT 0x277
458
459#define MSR_MTRRdefType 0x2ff
460
461#define MSR_CORE_PERF_FIXED_CTR0 0x309
462#define MSR_CORE_PERF_FIXED_CTR1 0x30a
463#define MSR_CORE_PERF_FIXED_CTR2 0x30b
464#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
465#define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
466#define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
467#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
468
469#define MSR_MC0_CTL 0x400
470#define MSR_MC0_STATUS 0x401
471#define MSR_MC0_ADDR 0x402
472#define MSR_MC0_MISC 0x403
473
474#define MSR_IA32_RTIT_OUTPUT_BASE 0x560
475#define MSR_IA32_RTIT_OUTPUT_MASK 0x561
476#define MSR_IA32_RTIT_CTL 0x570
477#define MSR_IA32_RTIT_STATUS 0x571
478#define MSR_IA32_RTIT_CR3_MATCH 0x572
479#define MSR_IA32_RTIT_ADDR0_A 0x580
480#define MSR_IA32_RTIT_ADDR0_B 0x581
481#define MSR_IA32_RTIT_ADDR1_A 0x582
482#define MSR_IA32_RTIT_ADDR1_B 0x583
483#define MSR_IA32_RTIT_ADDR2_A 0x584
484#define MSR_IA32_RTIT_ADDR2_B 0x585
485#define MSR_IA32_RTIT_ADDR3_A 0x586
486#define MSR_IA32_RTIT_ADDR3_B 0x587
487#define MAX_RTIT_ADDRS 8
488
489#define MSR_EFER 0xc0000080
490
491#define MSR_EFER_SCE (1 << 0)
492#define MSR_EFER_LME (1 << 8)
493#define MSR_EFER_LMA (1 << 10)
494#define MSR_EFER_NXE (1 << 11)
495#define MSR_EFER_SVME (1 << 12)
496#define MSR_EFER_FFXSR (1 << 14)
497
498#define MSR_EFER_RESERVED\
499 (~(target_ulong)(MSR_EFER_SCE | MSR_EFER_LME\
500 | MSR_EFER_LMA | MSR_EFER_NXE | MSR_EFER_SVME\
501 | MSR_EFER_FFXSR))
502
503#define MSR_STAR 0xc0000081
504#define MSR_LSTAR 0xc0000082
505#define MSR_CSTAR 0xc0000083
506#define MSR_FMASK 0xc0000084
507#define MSR_FSBASE 0xc0000100
508#define MSR_GSBASE 0xc0000101
509#define MSR_KERNELGSBASE 0xc0000102
510#define MSR_TSC_AUX 0xc0000103
511#define MSR_AMD64_TSC_RATIO 0xc0000104
512
513#define MSR_AMD64_TSC_RATIO_DEFAULT 0x100000000ULL
514
515#define MSR_VM_HSAVE_PA 0xc0010117
516
517#define MSR_IA32_XFD 0x000001c4
518#define MSR_IA32_XFD_ERR 0x000001c5
519
520#define MSR_IA32_BNDCFGS 0x00000d90
521#define MSR_IA32_XSS 0x00000da0
522#define MSR_IA32_UMWAIT_CONTROL 0xe1
523
524#define MSR_IA32_VMX_BASIC 0x00000480
525#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
526#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
527#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
528#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
529#define MSR_IA32_VMX_MISC 0x00000485
530#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
531#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
532#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
533#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
534#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
535#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
536#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
537#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
538#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
539#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
540#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
541#define MSR_IA32_VMX_VMFUNC 0x00000491
542
543#define XSTATE_FP_BIT 0
544#define XSTATE_SSE_BIT 1
545#define XSTATE_YMM_BIT 2
546#define XSTATE_BNDREGS_BIT 3
547#define XSTATE_BNDCSR_BIT 4
548#define XSTATE_OPMASK_BIT 5
549#define XSTATE_ZMM_Hi256_BIT 6
550#define XSTATE_Hi16_ZMM_BIT 7
551#define XSTATE_PKRU_BIT 9
552#define XSTATE_ARCH_LBR_BIT 15
553#define XSTATE_XTILE_CFG_BIT 17
554#define XSTATE_XTILE_DATA_BIT 18
555
556#define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
557#define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
558#define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT)
559#define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT)
560#define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT)
561#define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
562#define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
563#define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
564#define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
565#define XSTATE_ARCH_LBR_MASK (1ULL << XSTATE_ARCH_LBR_BIT)
566#define XSTATE_XTILE_CFG_MASK (1ULL << XSTATE_XTILE_CFG_BIT)
567#define XSTATE_XTILE_DATA_MASK (1ULL << XSTATE_XTILE_DATA_BIT)
568
569#define XSTATE_DYNAMIC_MASK (XSTATE_XTILE_DATA_MASK)
570
571#define ESA_FEATURE_ALIGN64_BIT 1
572#define ESA_FEATURE_XFD_BIT 2
573
574#define ESA_FEATURE_ALIGN64_MASK (1U << ESA_FEATURE_ALIGN64_BIT)
575#define ESA_FEATURE_XFD_MASK (1U << ESA_FEATURE_XFD_BIT)
576
577
578
579#define CPUID_XSTATE_XCR0_MASK (XSTATE_FP_MASK | XSTATE_SSE_MASK | \
580 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | \
581 XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | \
582 XSTATE_ZMM_Hi256_MASK | \
583 XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK | \
584 XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA_MASK)
585
586
587typedef enum FeatureWord {
588 FEAT_1_EDX,
589 FEAT_1_ECX,
590 FEAT_7_0_EBX,
591 FEAT_7_0_ECX,
592 FEAT_7_0_EDX,
593 FEAT_7_1_EAX,
594 FEAT_8000_0001_EDX,
595 FEAT_8000_0001_ECX,
596 FEAT_8000_0007_EDX,
597 FEAT_8000_0008_EBX,
598 FEAT_C000_0001_EDX,
599 FEAT_KVM,
600 FEAT_KVM_HINTS,
601 FEAT_SVM,
602 FEAT_XSAVE,
603 FEAT_6_EAX,
604 FEAT_XSAVE_XCR0_LO,
605 FEAT_XSAVE_XCR0_HI,
606 FEAT_ARCH_CAPABILITIES,
607 FEAT_CORE_CAPABILITY,
608 FEAT_PERF_CAPABILITIES,
609 FEAT_VMX_PROCBASED_CTLS,
610 FEAT_VMX_SECONDARY_CTLS,
611 FEAT_VMX_PINBASED_CTLS,
612 FEAT_VMX_EXIT_CTLS,
613 FEAT_VMX_ENTRY_CTLS,
614 FEAT_VMX_MISC,
615 FEAT_VMX_EPT_VPID_CAPS,
616 FEAT_VMX_BASIC,
617 FEAT_VMX_VMFUNC,
618 FEAT_14_0_ECX,
619 FEAT_SGX_12_0_EAX,
620 FEAT_SGX_12_0_EBX,
621 FEAT_SGX_12_1_EAX,
622 FEAT_XSAVE_XSS_LO,
623 FEAT_XSAVE_XSS_HI,
624 FEATURE_WORDS,
625} FeatureWord;
626
627typedef uint64_t FeatureWordArray[FEATURE_WORDS];
628uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
629 bool migratable_only);
630
631
632#define CPUID_FP87 (1U << 0)
633#define CPUID_VME (1U << 1)
634#define CPUID_DE (1U << 2)
635#define CPUID_PSE (1U << 3)
636#define CPUID_TSC (1U << 4)
637#define CPUID_MSR (1U << 5)
638#define CPUID_PAE (1U << 6)
639#define CPUID_MCE (1U << 7)
640#define CPUID_CX8 (1U << 8)
641#define CPUID_APIC (1U << 9)
642#define CPUID_SEP (1U << 11)
643#define CPUID_MTRR (1U << 12)
644#define CPUID_PGE (1U << 13)
645#define CPUID_MCA (1U << 14)
646#define CPUID_CMOV (1U << 15)
647#define CPUID_PAT (1U << 16)
648#define CPUID_PSE36 (1U << 17)
649#define CPUID_PN (1U << 18)
650#define CPUID_CLFLUSH (1U << 19)
651#define CPUID_DTS (1U << 21)
652#define CPUID_ACPI (1U << 22)
653#define CPUID_MMX (1U << 23)
654#define CPUID_FXSR (1U << 24)
655#define CPUID_SSE (1U << 25)
656#define CPUID_SSE2 (1U << 26)
657#define CPUID_SS (1U << 27)
658#define CPUID_HT (1U << 28)
659#define CPUID_TM (1U << 29)
660#define CPUID_IA64 (1U << 30)
661#define CPUID_PBE (1U << 31)
662
663#define CPUID_EXT_SSE3 (1U << 0)
664#define CPUID_EXT_PCLMULQDQ (1U << 1)
665#define CPUID_EXT_DTES64 (1U << 2)
666#define CPUID_EXT_MONITOR (1U << 3)
667#define CPUID_EXT_DSCPL (1U << 4)
668#define CPUID_EXT_VMX (1U << 5)
669#define CPUID_EXT_SMX (1U << 6)
670#define CPUID_EXT_EST (1U << 7)
671#define CPUID_EXT_TM2 (1U << 8)
672#define CPUID_EXT_SSSE3 (1U << 9)
673#define CPUID_EXT_CID (1U << 10)
674#define CPUID_EXT_FMA (1U << 12)
675#define CPUID_EXT_CX16 (1U << 13)
676#define CPUID_EXT_XTPR (1U << 14)
677#define CPUID_EXT_PDCM (1U << 15)
678#define CPUID_EXT_PCID (1U << 17)
679#define CPUID_EXT_DCA (1U << 18)
680#define CPUID_EXT_SSE41 (1U << 19)
681#define CPUID_EXT_SSE42 (1U << 20)
682#define CPUID_EXT_X2APIC (1U << 21)
683#define CPUID_EXT_MOVBE (1U << 22)
684#define CPUID_EXT_POPCNT (1U << 23)
685#define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
686#define CPUID_EXT_AES (1U << 25)
687#define CPUID_EXT_XSAVE (1U << 26)
688#define CPUID_EXT_OSXSAVE (1U << 27)
689#define CPUID_EXT_AVX (1U << 28)
690#define CPUID_EXT_F16C (1U << 29)
691#define CPUID_EXT_RDRAND (1U << 30)
692#define CPUID_EXT_HYPERVISOR (1U << 31)
693
694#define CPUID_EXT2_FPU (1U << 0)
695#define CPUID_EXT2_VME (1U << 1)
696#define CPUID_EXT2_DE (1U << 2)
697#define CPUID_EXT2_PSE (1U << 3)
698#define CPUID_EXT2_TSC (1U << 4)
699#define CPUID_EXT2_MSR (1U << 5)
700#define CPUID_EXT2_PAE (1U << 6)
701#define CPUID_EXT2_MCE (1U << 7)
702#define CPUID_EXT2_CX8 (1U << 8)
703#define CPUID_EXT2_APIC (1U << 9)
704#define CPUID_EXT2_SYSCALL (1U << 11)
705#define CPUID_EXT2_MTRR (1U << 12)
706#define CPUID_EXT2_PGE (1U << 13)
707#define CPUID_EXT2_MCA (1U << 14)
708#define CPUID_EXT2_CMOV (1U << 15)
709#define CPUID_EXT2_PAT (1U << 16)
710#define CPUID_EXT2_PSE36 (1U << 17)
711#define CPUID_EXT2_MP (1U << 19)
712#define CPUID_EXT2_NX (1U << 20)
713#define CPUID_EXT2_MMXEXT (1U << 22)
714#define CPUID_EXT2_MMX (1U << 23)
715#define CPUID_EXT2_FXSR (1U << 24)
716#define CPUID_EXT2_FFXSR (1U << 25)
717#define CPUID_EXT2_PDPE1GB (1U << 26)
718#define CPUID_EXT2_RDTSCP (1U << 27)
719#define CPUID_EXT2_LM (1U << 29)
720#define CPUID_EXT2_3DNOWEXT (1U << 30)
721#define CPUID_EXT2_3DNOW (1U << 31)
722
723
724#define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
725 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
726 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
727 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
728 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
729 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
730 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
731 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
732 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
733
734#define CPUID_EXT3_LAHF_LM (1U << 0)
735#define CPUID_EXT3_CMP_LEG (1U << 1)
736#define CPUID_EXT3_SVM (1U << 2)
737#define CPUID_EXT3_EXTAPIC (1U << 3)
738#define CPUID_EXT3_CR8LEG (1U << 4)
739#define CPUID_EXT3_ABM (1U << 5)
740#define CPUID_EXT3_SSE4A (1U << 6)
741#define CPUID_EXT3_MISALIGNSSE (1U << 7)
742#define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
743#define CPUID_EXT3_OSVW (1U << 9)
744#define CPUID_EXT3_IBS (1U << 10)
745#define CPUID_EXT3_XOP (1U << 11)
746#define CPUID_EXT3_SKINIT (1U << 12)
747#define CPUID_EXT3_WDT (1U << 13)
748#define CPUID_EXT3_LWP (1U << 15)
749#define CPUID_EXT3_FMA4 (1U << 16)
750#define CPUID_EXT3_TCE (1U << 17)
751#define CPUID_EXT3_NODEID (1U << 19)
752#define CPUID_EXT3_TBM (1U << 21)
753#define CPUID_EXT3_TOPOEXT (1U << 22)
754#define CPUID_EXT3_PERFCORE (1U << 23)
755#define CPUID_EXT3_PERFNB (1U << 24)
756
757#define CPUID_SVM_NPT (1U << 0)
758#define CPUID_SVM_LBRV (1U << 1)
759#define CPUID_SVM_SVMLOCK (1U << 2)
760#define CPUID_SVM_NRIPSAVE (1U << 3)
761#define CPUID_SVM_TSCSCALE (1U << 4)
762#define CPUID_SVM_VMCBCLEAN (1U << 5)
763#define CPUID_SVM_FLUSHASID (1U << 6)
764#define CPUID_SVM_DECODEASSIST (1U << 7)
765#define CPUID_SVM_PAUSEFILTER (1U << 10)
766#define CPUID_SVM_PFTHRESHOLD (1U << 12)
767#define CPUID_SVM_AVIC (1U << 13)
768#define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15)
769#define CPUID_SVM_VGIF (1U << 16)
770#define CPUID_SVM_SVME_ADDR_CHK (1U << 28)
771
772
773#define CPUID_7_0_EBX_FSGSBASE (1U << 0)
774
775#define CPUID_7_0_EBX_SGX (1U << 2)
776
777#define CPUID_7_0_EBX_BMI1 (1U << 3)
778
779#define CPUID_7_0_EBX_HLE (1U << 4)
780
781#define CPUID_7_0_EBX_AVX2 (1U << 5)
782
783#define CPUID_7_0_EBX_SMEP (1U << 7)
784
785#define CPUID_7_0_EBX_BMI2 (1U << 8)
786
787#define CPUID_7_0_EBX_ERMS (1U << 9)
788
789#define CPUID_7_0_EBX_INVPCID (1U << 10)
790
791#define CPUID_7_0_EBX_RTM (1U << 11)
792
793#define CPUID_7_0_EBX_MPX (1U << 14)
794
795#define CPUID_7_0_EBX_AVX512F (1U << 16)
796
797#define CPUID_7_0_EBX_AVX512DQ (1U << 17)
798
799#define CPUID_7_0_EBX_RDSEED (1U << 18)
800
801#define CPUID_7_0_EBX_ADX (1U << 19)
802
803#define CPUID_7_0_EBX_SMAP (1U << 20)
804
805#define CPUID_7_0_EBX_AVX512IFMA (1U << 21)
806
807#define CPUID_7_0_EBX_PCOMMIT (1U << 22)
808
809#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
810
811#define CPUID_7_0_EBX_CLWB (1U << 24)
812
813#define CPUID_7_0_EBX_INTEL_PT (1U << 25)
814
815#define CPUID_7_0_EBX_AVX512PF (1U << 26)
816
817#define CPUID_7_0_EBX_AVX512ER (1U << 27)
818
819#define CPUID_7_0_EBX_AVX512CD (1U << 28)
820
821#define CPUID_7_0_EBX_SHA_NI (1U << 29)
822
823#define CPUID_7_0_EBX_AVX512BW (1U << 30)
824
825#define CPUID_7_0_EBX_AVX512VL (1U << 31)
826
827
828#define CPUID_7_0_ECX_AVX512_VBMI (1U << 1)
829
830#define CPUID_7_0_ECX_UMIP (1U << 2)
831
832#define CPUID_7_0_ECX_PKU (1U << 3)
833
834#define CPUID_7_0_ECX_OSPKE (1U << 4)
835
836#define CPUID_7_0_ECX_WAITPKG (1U << 5)
837
838#define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6)
839
840#define CPUID_7_0_ECX_GFNI (1U << 8)
841
842#define CPUID_7_0_ECX_VAES (1U << 9)
843
844#define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
845
846#define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
847
848#define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
849
850#define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14)
851
852#define CPUID_7_0_ECX_LA57 (1U << 16)
853
854#define CPUID_7_0_ECX_RDPID (1U << 22)
855
856#define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24)
857
858#define CPUID_7_0_ECX_CLDEMOTE (1U << 25)
859
860#define CPUID_7_0_ECX_MOVDIRI (1U << 27)
861
862#define CPUID_7_0_ECX_MOVDIR64B (1U << 28)
863
864#define CPUID_7_0_ECX_SGX_LC (1U << 30)
865
866#define CPUID_7_0_ECX_PKS (1U << 31)
867
868
869#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
870
871#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
872
873#define CPUID_7_0_EDX_FSRM (1U << 4)
874
875#define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)
876
877#define CPUID_7_0_EDX_SERIALIZE (1U << 14)
878
879#define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
880
881#define CPUID_7_0_EDX_ARCH_LBR (1U << 19)
882
883#define CPUID_7_0_EDX_AVX512_FP16 (1U << 23)
884
885#define CPUID_7_0_EDX_AMX_TILE (1U << 24)
886
887#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
888
889#define CPUID_7_0_EDX_STIBP (1U << 27)
890
891#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
892
893#define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30)
894
895#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31)
896
897
898#define CPUID_7_1_EAX_AVX_VNNI (1U << 4)
899
900#define CPUID_7_1_EAX_AVX512_BF16 (1U << 5)
901
902#define CPUID_D_1_EAX_XFD (1U << 4)
903
904
905#define CPUID_14_0_ECX_LIP (1U << 31)
906
907
908#define CPUID_8000_0008_EBX_CLZERO (1U << 0)
909
910#define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2)
911
912#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
913
914#define CPUID_8000_0008_EBX_IBPB (1U << 12)
915
916#define CPUID_8000_0008_EBX_IBRS (1U << 14)
917
918#define CPUID_8000_0008_EBX_STIBP (1U << 15)
919
920#define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24)
921
922#define CPUID_XSAVE_XSAVEOPT (1U << 0)
923#define CPUID_XSAVE_XSAVEC (1U << 1)
924#define CPUID_XSAVE_XGETBV1 (1U << 2)
925#define CPUID_XSAVE_XSAVES (1U << 3)
926
927#define CPUID_6_EAX_ARAT (1U << 2)
928
929
930#define CPUID_APM_INVTSC (1U << 8)
931
932#define CPUID_VENDOR_SZ 12
933
934#define CPUID_VENDOR_INTEL_1 0x756e6547
935#define CPUID_VENDOR_INTEL_2 0x49656e69
936#define CPUID_VENDOR_INTEL_3 0x6c65746e
937#define CPUID_VENDOR_INTEL "GenuineIntel"
938
939#define CPUID_VENDOR_AMD_1 0x68747541
940#define CPUID_VENDOR_AMD_2 0x69746e65
941#define CPUID_VENDOR_AMD_3 0x444d4163
942#define CPUID_VENDOR_AMD "AuthenticAMD"
943
944#define CPUID_VENDOR_VIA "CentaurHauls"
945
946#define CPUID_VENDOR_HYGON "HygonGenuine"
947
948#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
949 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
950 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
951#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
952 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
953 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
954
955#define CPUID_MWAIT_IBE (1U << 1)
956#define CPUID_MWAIT_EMX (1U << 0)
957
958
959#define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8)
960#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
961#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
962#define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8)
963
964
965#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
966#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
967#define MSR_ARCH_CAP_RSBA (1U << 2)
968#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
969#define MSR_ARCH_CAP_SSB_NO (1U << 4)
970#define MSR_ARCH_CAP_MDS_NO (1U << 5)
971#define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6)
972#define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7)
973#define MSR_ARCH_CAP_TAA_NO (1U << 8)
974
975#define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
976
977
978#define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull
979#define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32)
980#define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32)
981#define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49)
982#define MSR_VMX_BASIC_INS_OUTS (1ULL << 54)
983#define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55)
984
985#define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full
986#define MSR_VMX_MISC_STORE_LMA (1ULL << 5)
987#define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6)
988#define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7)
989#define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8)
990#define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull
991#define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29)
992#define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30)
993
994#define MSR_VMX_EPT_EXECONLY (1ULL << 0)
995#define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6)
996#define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7)
997#define MSR_VMX_EPT_UC (1ULL << 8)
998#define MSR_VMX_EPT_WB (1ULL << 14)
999#define MSR_VMX_EPT_2MB (1ULL << 16)
1000#define MSR_VMX_EPT_1GB (1ULL << 17)
1001#define MSR_VMX_EPT_INVEPT (1ULL << 20)
1002#define MSR_VMX_EPT_AD_BITS (1ULL << 21)
1003#define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22)
1004#define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25)
1005#define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26)
1006#define MSR_VMX_EPT_INVVPID (1ULL << 32)
1007#define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40)
1008#define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41)
1009#define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42)
1010#define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43)
1011
1012#define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0)
1013
1014
1015
1016#define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
1017#define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008
1018#define VMX_CPU_BASED_HLT_EXITING 0x00000080
1019#define VMX_CPU_BASED_INVLPG_EXITING 0x00000200
1020#define VMX_CPU_BASED_MWAIT_EXITING 0x00000400
1021#define VMX_CPU_BASED_RDPMC_EXITING 0x00000800
1022#define VMX_CPU_BASED_RDTSC_EXITING 0x00001000
1023#define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000
1024#define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000
1025#define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000
1026#define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000
1027#define VMX_CPU_BASED_TPR_SHADOW 0x00200000
1028#define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
1029#define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000
1030#define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000
1031#define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000
1032#define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
1033#define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000
1034#define VMX_CPU_BASED_MONITOR_EXITING 0x20000000
1035#define VMX_CPU_BASED_PAUSE_EXITING 0x40000000
1036#define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
1037
1038#define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
1039#define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002
1040#define VMX_SECONDARY_EXEC_DESC 0x00000004
1041#define VMX_SECONDARY_EXEC_RDTSCP 0x00000008
1042#define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
1043#define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020
1044#define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040
1045#define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
1046#define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
1047#define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
1048#define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
1049#define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800
1050#define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
1051#define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000
1052#define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000
1053#define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000
1054#define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000
1055#define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000
1056#define VMX_SECONDARY_EXEC_XSAVES 0x00100000
1057#define VMX_SECONDARY_EXEC_TSC_SCALING 0x02000000
1058
1059#define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001
1060#define VMX_PIN_BASED_NMI_EXITING 0x00000008
1061#define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020
1062#define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
1063#define VMX_PIN_BASED_POSTED_INTR 0x00000080
1064
1065#define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
1066#define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
1067#define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
1068#define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
1069#define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000
1070#define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000
1071#define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000
1072#define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000
1073#define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
1074#define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000
1075#define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000
1076#define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
1077#define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000
1078
1079#define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
1080#define VMX_VM_ENTRY_IA32E_MODE 0x00000200
1081#define VMX_VM_ENTRY_SMM 0x00000400
1082#define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
1083#define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
1084#define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000
1085#define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000
1086#define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000
1087#define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000
1088#define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
1089#define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000
1090
1091
1092#define HYPERV_FEAT_RELAXED 0
1093#define HYPERV_FEAT_VAPIC 1
1094#define HYPERV_FEAT_TIME 2
1095#define HYPERV_FEAT_CRASH 3
1096#define HYPERV_FEAT_RESET 4
1097#define HYPERV_FEAT_VPINDEX 5
1098#define HYPERV_FEAT_RUNTIME 6
1099#define HYPERV_FEAT_SYNIC 7
1100#define HYPERV_FEAT_STIMER 8
1101#define HYPERV_FEAT_FREQUENCIES 9
1102#define HYPERV_FEAT_REENLIGHTENMENT 10
1103#define HYPERV_FEAT_TLBFLUSH 11
1104#define HYPERV_FEAT_EVMCS 12
1105#define HYPERV_FEAT_IPI 13
1106#define HYPERV_FEAT_STIMER_DIRECT 14
1107#define HYPERV_FEAT_AVIC 15
1108#define HYPERV_FEAT_SYNDBG 16
1109#define HYPERV_FEAT_MSR_BITMAP 17
1110#define HYPERV_FEAT_XMM_INPUT 18
1111#define HYPERV_FEAT_TLBFLUSH_EXT 19
1112#define HYPERV_FEAT_TLBFLUSH_DIRECT 20
1113
1114#ifndef HYPERV_SPINLOCK_NEVER_NOTIFY
1115#define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF
1116#endif
1117
1118#define EXCP00_DIVZ 0
1119#define EXCP01_DB 1
1120#define EXCP02_NMI 2
1121#define EXCP03_INT3 3
1122#define EXCP04_INTO 4
1123#define EXCP05_BOUND 5
1124#define EXCP06_ILLOP 6
1125#define EXCP07_PREX 7
1126#define EXCP08_DBLE 8
1127#define EXCP09_XERR 9
1128#define EXCP0A_TSS 10
1129#define EXCP0B_NOSEG 11
1130#define EXCP0C_STACK 12
1131#define EXCP0D_GPF 13
1132#define EXCP0E_PAGE 14
1133#define EXCP10_COPR 16
1134#define EXCP11_ALGN 17
1135#define EXCP12_MCHK 18
1136
1137#define EXCP_VMEXIT 0x100
1138#define EXCP_SYSCALL 0x101
1139#define EXCP_VSYSCALL 0x102
1140
1141
1142#define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
1143#define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
1144#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
1145#define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
1146#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
1147#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
1148#define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
1149
1150
1151#define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
1152
1153
1154
1155
1156
1157
1158
1159
1160typedef enum {
1161 CC_OP_DYNAMIC,
1162 CC_OP_EFLAGS,
1163
1164 CC_OP_MULB,
1165 CC_OP_MULW,
1166 CC_OP_MULL,
1167 CC_OP_MULQ,
1168
1169 CC_OP_ADDB,
1170 CC_OP_ADDW,
1171 CC_OP_ADDL,
1172 CC_OP_ADDQ,
1173
1174 CC_OP_ADCB,
1175 CC_OP_ADCW,
1176 CC_OP_ADCL,
1177 CC_OP_ADCQ,
1178
1179 CC_OP_SUBB,
1180 CC_OP_SUBW,
1181 CC_OP_SUBL,
1182 CC_OP_SUBQ,
1183
1184 CC_OP_SBBB,
1185 CC_OP_SBBW,
1186 CC_OP_SBBL,
1187 CC_OP_SBBQ,
1188
1189 CC_OP_LOGICB,
1190 CC_OP_LOGICW,
1191 CC_OP_LOGICL,
1192 CC_OP_LOGICQ,
1193
1194 CC_OP_INCB,
1195 CC_OP_INCW,
1196 CC_OP_INCL,
1197 CC_OP_INCQ,
1198
1199 CC_OP_DECB,
1200 CC_OP_DECW,
1201 CC_OP_DECL,
1202 CC_OP_DECQ,
1203
1204 CC_OP_SHLB,
1205 CC_OP_SHLW,
1206 CC_OP_SHLL,
1207 CC_OP_SHLQ,
1208
1209 CC_OP_SARB,
1210 CC_OP_SARW,
1211 CC_OP_SARL,
1212 CC_OP_SARQ,
1213
1214 CC_OP_BMILGB,
1215 CC_OP_BMILGW,
1216 CC_OP_BMILGL,
1217 CC_OP_BMILGQ,
1218
1219 CC_OP_ADCX,
1220 CC_OP_ADOX,
1221 CC_OP_ADCOX,
1222
1223 CC_OP_CLR,
1224 CC_OP_POPCNT,
1225
1226 CC_OP_NB,
1227} CCOp;
1228
1229typedef struct SegmentCache {
1230 uint32_t selector;
1231 target_ulong base;
1232 uint32_t limit;
1233 uint32_t flags;
1234} SegmentCache;
1235
1236#define MMREG_UNION(n, bits) \
1237 union n { \
1238 uint8_t _b_##n[(bits)/8]; \
1239 uint16_t _w_##n[(bits)/16]; \
1240 uint32_t _l_##n[(bits)/32]; \
1241 uint64_t _q_##n[(bits)/64]; \
1242 float32 _s_##n[(bits)/32]; \
1243 float64 _d_##n[(bits)/64]; \
1244 }
1245
1246typedef MMREG_UNION(ZMMReg, 512) ZMMReg;
1247typedef MMREG_UNION(MMXReg, 64) MMXReg;
1248
1249typedef struct BNDReg {
1250 uint64_t lb;
1251 uint64_t ub;
1252} BNDReg;
1253
1254typedef struct BNDCSReg {
1255 uint64_t cfgu;
1256 uint64_t sts;
1257} BNDCSReg;
1258
1259#define BNDCFG_ENABLE 1ULL
1260#define BNDCFG_BNDPRESERVE 2ULL
1261#define BNDCFG_BDIR_MASK TARGET_PAGE_MASK
1262
1263#if HOST_BIG_ENDIAN
1264#define ZMM_B(n) _b_ZMMReg[63 - (n)]
1265#define ZMM_W(n) _w_ZMMReg[31 - (n)]
1266#define ZMM_L(n) _l_ZMMReg[15 - (n)]
1267#define ZMM_S(n) _s_ZMMReg[15 - (n)]
1268#define ZMM_Q(n) _q_ZMMReg[7 - (n)]
1269#define ZMM_D(n) _d_ZMMReg[7 - (n)]
1270
1271#define MMX_B(n) _b_MMXReg[7 - (n)]
1272#define MMX_W(n) _w_MMXReg[3 - (n)]
1273#define MMX_L(n) _l_MMXReg[1 - (n)]
1274#define MMX_S(n) _s_MMXReg[1 - (n)]
1275#else
1276#define ZMM_B(n) _b_ZMMReg[n]
1277#define ZMM_W(n) _w_ZMMReg[n]
1278#define ZMM_L(n) _l_ZMMReg[n]
1279#define ZMM_S(n) _s_ZMMReg[n]
1280#define ZMM_Q(n) _q_ZMMReg[n]
1281#define ZMM_D(n) _d_ZMMReg[n]
1282
1283#define MMX_B(n) _b_MMXReg[n]
1284#define MMX_W(n) _w_MMXReg[n]
1285#define MMX_L(n) _l_MMXReg[n]
1286#define MMX_S(n) _s_MMXReg[n]
1287#endif
1288#define MMX_Q(n) _q_MMXReg[n]
1289
1290typedef union {
1291 floatx80 d __attribute__((aligned(16)));
1292 MMXReg mmx;
1293} FPReg;
1294
1295typedef struct {
1296 uint64_t base;
1297 uint64_t mask;
1298} MTRRVar;
1299
1300#define CPU_NB_REGS64 16
1301#define CPU_NB_REGS32 8
1302
1303#ifdef TARGET_X86_64
1304#define CPU_NB_REGS CPU_NB_REGS64
1305#else
1306#define CPU_NB_REGS CPU_NB_REGS32
1307#endif
1308
1309#define MAX_FIXED_COUNTERS 3
1310#define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
1311
1312#define TARGET_INSN_START_EXTRA_WORDS 1
1313
1314#define NB_OPMASK_REGS 8
1315
1316
1317
1318
1319#define UNASSIGNED_APIC_ID 0xFFFFFFFF
1320
1321typedef union X86LegacyXSaveArea {
1322 struct {
1323 uint16_t fcw;
1324 uint16_t fsw;
1325 uint8_t ftw;
1326 uint8_t reserved;
1327 uint16_t fpop;
1328 uint64_t fpip;
1329 uint64_t fpdp;
1330 uint32_t mxcsr;
1331 uint32_t mxcsr_mask;
1332 FPReg fpregs[8];
1333 uint8_t xmm_regs[16][16];
1334 };
1335 uint8_t data[512];
1336} X86LegacyXSaveArea;
1337
1338typedef struct X86XSaveHeader {
1339 uint64_t xstate_bv;
1340 uint64_t xcomp_bv;
1341 uint64_t reserve0;
1342 uint8_t reserved[40];
1343} X86XSaveHeader;
1344
1345
1346typedef struct XSaveAVX {
1347 uint8_t ymmh[16][16];
1348} XSaveAVX;
1349
1350
1351typedef struct XSaveBNDREG {
1352 BNDReg bnd_regs[4];
1353} XSaveBNDREG;
1354
1355
1356typedef union XSaveBNDCSR {
1357 BNDCSReg bndcsr;
1358 uint8_t data[64];
1359} XSaveBNDCSR;
1360
1361
1362typedef struct XSaveOpmask {
1363 uint64_t opmask_regs[NB_OPMASK_REGS];
1364} XSaveOpmask;
1365
1366
1367typedef struct XSaveZMM_Hi256 {
1368 uint8_t zmm_hi256[16][32];
1369} XSaveZMM_Hi256;
1370
1371
1372typedef struct XSaveHi16_ZMM {
1373 uint8_t hi16_zmm[16][64];
1374} XSaveHi16_ZMM;
1375
1376
1377typedef struct XSavePKRU {
1378 uint32_t pkru;
1379 uint32_t padding;
1380} XSavePKRU;
1381
1382
1383typedef struct XSaveXTILECFG {
1384 uint8_t xtilecfg[64];
1385} XSaveXTILECFG;
1386
1387
1388typedef struct XSaveXTILEDATA {
1389 uint8_t xtiledata[8][1024];
1390} XSaveXTILEDATA;
1391
1392typedef struct {
1393 uint64_t from;
1394 uint64_t to;
1395 uint64_t info;
1396} LBREntry;
1397
1398#define ARCH_LBR_NR_ENTRIES 32
1399
1400
1401typedef struct XSavesArchLBR {
1402 uint64_t lbr_ctl;
1403 uint64_t lbr_depth;
1404 uint64_t ler_from;
1405 uint64_t ler_to;
1406 uint64_t ler_info;
1407 LBREntry lbr_records[ARCH_LBR_NR_ENTRIES];
1408} XSavesArchLBR;
1409
1410QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
1411QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
1412QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
1413QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
1414QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
1415QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
1416QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
1417QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) != 0x40);
1418QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) != 0x2000);
1419QEMU_BUILD_BUG_ON(sizeof(XSavesArchLBR) != 0x328);
1420
1421typedef struct ExtSaveArea {
1422 uint32_t feature, bits;
1423 uint32_t offset, size;
1424 uint32_t ecx;
1425} ExtSaveArea;
1426
1427#define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1)
1428
1429extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT];
1430
1431typedef enum TPRAccess {
1432 TPR_ACCESS_READ,
1433 TPR_ACCESS_WRITE,
1434} TPRAccess;
1435
1436
1437
1438enum CacheType {
1439 DATA_CACHE,
1440 INSTRUCTION_CACHE,
1441 UNIFIED_CACHE
1442};
1443
1444typedef struct CPUCacheInfo {
1445 enum CacheType type;
1446 uint8_t level;
1447
1448 uint32_t size;
1449
1450 uint16_t line_size;
1451
1452
1453
1454
1455 uint8_t associativity;
1456
1457 uint8_t partitions;
1458
1459 uint32_t sets;
1460
1461
1462
1463
1464
1465 uint8_t lines_per_tag;
1466
1467
1468 bool self_init;
1469
1470
1471
1472
1473
1474 bool no_invd_sharing;
1475
1476
1477
1478
1479 bool inclusive;
1480
1481
1482
1483
1484 bool complex_indexing;
1485} CPUCacheInfo;
1486
1487
1488typedef struct CPUCaches {
1489 CPUCacheInfo *l1d_cache;
1490 CPUCacheInfo *l1i_cache;
1491 CPUCacheInfo *l2_cache;
1492 CPUCacheInfo *l3_cache;
1493} CPUCaches;
1494
1495typedef struct HVFX86LazyFlags {
1496 target_ulong result;
1497 target_ulong auxbits;
1498} HVFX86LazyFlags;
1499
1500typedef struct CPUArchState {
1501
1502 target_ulong regs[CPU_NB_REGS];
1503 target_ulong eip;
1504 target_ulong eflags;
1505
1506
1507
1508
1509 target_ulong cc_dst;
1510 target_ulong cc_src;
1511 target_ulong cc_src2;
1512 uint32_t cc_op;
1513 int32_t df;
1514 uint32_t hflags;
1515
1516 uint32_t hflags2;
1517
1518
1519 SegmentCache segs[6];
1520 SegmentCache ldt;
1521 SegmentCache tr;
1522 SegmentCache gdt;
1523 SegmentCache idt;
1524
1525 target_ulong cr[5];
1526
1527 bool pdptrs_valid;
1528 uint64_t pdptrs[4];
1529 int32_t a20_mask;
1530
1531 BNDReg bnd_regs[4];
1532 BNDCSReg bndcs_regs;
1533 uint64_t msr_bndcfgs;
1534 uint64_t efer;
1535
1536
1537 struct {} start_init_save;
1538
1539
1540 unsigned int fpstt;
1541 uint16_t fpus;
1542 uint16_t fpuc;
1543 uint8_t fptags[8];
1544 FPReg fpregs[8];
1545
1546 uint16_t fpop;
1547 uint16_t fpcs;
1548 uint16_t fpds;
1549 uint64_t fpip;
1550 uint64_t fpdp;
1551
1552
1553 float_status fp_status;
1554 floatx80 ft0;
1555
1556 float_status mmx_status;
1557 float_status sse_status;
1558 uint32_t mxcsr;
1559 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32];
1560 ZMMReg xmm_t0;
1561 MMXReg mmx_t0;
1562
1563 uint64_t opmask_regs[NB_OPMASK_REGS];
1564#ifdef TARGET_X86_64
1565 uint8_t xtilecfg[64];
1566 uint8_t xtiledata[8192];
1567#endif
1568
1569
1570 uint32_t sysenter_cs;
1571 target_ulong sysenter_esp;
1572 target_ulong sysenter_eip;
1573 uint64_t star;
1574
1575 uint64_t vm_hsave;
1576
1577#ifdef TARGET_X86_64
1578 target_ulong lstar;
1579 target_ulong cstar;
1580 target_ulong fmask;
1581 target_ulong kernelgsbase;
1582#endif
1583
1584 uint64_t tsc_adjust;
1585 uint64_t tsc_deadline;
1586 uint64_t tsc_aux;
1587
1588 uint64_t xcr0;
1589
1590 uint64_t mcg_status;
1591 uint64_t msr_ia32_misc_enable;
1592 uint64_t msr_ia32_feature_control;
1593 uint64_t msr_ia32_sgxlepubkeyhash[4];
1594
1595 uint64_t msr_fixed_ctr_ctrl;
1596 uint64_t msr_global_ctrl;
1597 uint64_t msr_global_status;
1598 uint64_t msr_global_ovf_ctrl;
1599 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
1600 uint64_t msr_gp_counters[MAX_GP_COUNTERS];
1601 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
1602
1603 uint64_t pat;
1604 uint32_t smbase;
1605 uint64_t msr_smi_count;
1606
1607 uint32_t pkru;
1608 uint32_t pkrs;
1609 uint32_t tsx_ctrl;
1610
1611 uint64_t spec_ctrl;
1612 uint64_t amd_tsc_scale_msr;
1613 uint64_t virt_ssbd;
1614
1615
1616 struct {} end_init_save;
1617
1618 uint64_t system_time_msr;
1619 uint64_t wall_clock_msr;
1620 uint64_t steal_time_msr;
1621 uint64_t async_pf_en_msr;
1622 uint64_t async_pf_int_msr;
1623 uint64_t pv_eoi_en_msr;
1624 uint64_t poll_control_msr;
1625
1626
1627 uint64_t msr_hv_hypercall;
1628 uint64_t msr_hv_guest_os_id;
1629 uint64_t msr_hv_tsc;
1630 uint64_t msr_hv_syndbg_control;
1631 uint64_t msr_hv_syndbg_status;
1632 uint64_t msr_hv_syndbg_send_page;
1633 uint64_t msr_hv_syndbg_recv_page;
1634 uint64_t msr_hv_syndbg_pending_page;
1635 uint64_t msr_hv_syndbg_options;
1636
1637
1638 uint64_t msr_hv_vapic;
1639 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS];
1640 uint64_t msr_hv_runtime;
1641 uint64_t msr_hv_synic_control;
1642 uint64_t msr_hv_synic_evt_page;
1643 uint64_t msr_hv_synic_msg_page;
1644 uint64_t msr_hv_synic_sint[HV_SINT_COUNT];
1645 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT];
1646 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT];
1647 uint64_t msr_hv_reenlightenment_control;
1648 uint64_t msr_hv_tsc_emulation_control;
1649 uint64_t msr_hv_tsc_emulation_status;
1650
1651 uint64_t msr_rtit_ctrl;
1652 uint64_t msr_rtit_status;
1653 uint64_t msr_rtit_output_base;
1654 uint64_t msr_rtit_output_mask;
1655 uint64_t msr_rtit_cr3_match;
1656 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
1657
1658
1659 uint64_t msr_xfd;
1660 uint64_t msr_xfd_err;
1661
1662
1663 uint64_t msr_lbr_ctl;
1664 uint64_t msr_lbr_depth;
1665 LBREntry lbr_records[ARCH_LBR_NR_ENTRIES];
1666
1667
1668 int error_code;
1669 int exception_is_int;
1670 target_ulong exception_next_eip;
1671 target_ulong dr[8];
1672 union {
1673 struct CPUBreakpoint *cpu_breakpoint[4];
1674 struct CPUWatchpoint *cpu_watchpoint[4];
1675 };
1676 int old_exception;
1677
1678 uint64_t vm_vmcb;
1679 uint64_t tsc_offset;
1680 uint64_t intercept;
1681 uint16_t intercept_cr_read;
1682 uint16_t intercept_cr_write;
1683 uint16_t intercept_dr_read;
1684 uint16_t intercept_dr_write;
1685 uint32_t intercept_exceptions;
1686 uint64_t nested_cr3;
1687 uint32_t nested_pg_mode;
1688 uint8_t v_tpr;
1689 uint32_t int_ctl;
1690
1691
1692 uint8_t nmi_injected;
1693 uint8_t nmi_pending;
1694
1695 uintptr_t retaddr;
1696
1697
1698 struct {} end_reset_fields;
1699
1700
1701
1702
1703
1704 uint32_t cpuid_level_func7;
1705
1706 uint32_t cpuid_min_level_func7;
1707
1708 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2;
1709
1710 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2;
1711
1712 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2;
1713 uint32_t cpuid_vendor1;
1714 uint32_t cpuid_vendor2;
1715 uint32_t cpuid_vendor3;
1716 uint32_t cpuid_version;
1717 FeatureWordArray features;
1718
1719 FeatureWordArray user_features;
1720 uint32_t cpuid_model[12];
1721
1722
1723
1724
1725 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
1726
1727
1728 uint64_t mtrr_fixed[11];
1729 uint64_t mtrr_deftype;
1730 MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1731
1732
1733 uint32_t mp_state;
1734 int32_t exception_nr;
1735 int32_t interrupt_injected;
1736 uint8_t soft_interrupt;
1737 uint8_t exception_pending;
1738 uint8_t exception_injected;
1739 uint8_t has_error_code;
1740 uint8_t exception_has_payload;
1741 uint64_t exception_payload;
1742 uint32_t ins_len;
1743 uint32_t sipi_vector;
1744 bool tsc_valid;
1745 int64_t tsc_khz;
1746 int64_t user_tsc_khz;
1747 uint64_t apic_bus_freq;
1748 uint64_t tsc;
1749#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
1750 void *xsave_buf;
1751 uint32_t xsave_buf_len;
1752#endif
1753#if defined(CONFIG_KVM)
1754 struct kvm_nested_state *nested_state;
1755#endif
1756#if defined(CONFIG_HVF)
1757 HVFX86LazyFlags hvf_lflags;
1758 void *hvf_mmio_buf;
1759#endif
1760
1761 uint64_t mcg_cap;
1762 uint64_t mcg_ctl;
1763 uint64_t mcg_ext_ctl;
1764 uint64_t mce_banks[MCE_BANKS_DEF*4];
1765 uint64_t xstate_bv;
1766
1767
1768 uint16_t fpus_vmstate;
1769 uint16_t fptag_vmstate;
1770 uint16_t fpregs_format_vmstate;
1771
1772 uint64_t xss;
1773 uint32_t umwait;
1774
1775 TPRAccess tpr_access_type;
1776
1777 unsigned nr_dies;
1778} CPUX86State;
1779
1780struct kvm_msrs;
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791struct ArchCPU {
1792
1793 CPUState parent_obj;
1794
1795
1796 CPUNegativeOffsetState neg;
1797 CPUX86State env;
1798 VMChangeStateEntry *vmsentry;
1799
1800 uint64_t ucode_rev;
1801
1802 uint32_t hyperv_spinlock_attempts;
1803 char *hyperv_vendor;
1804 bool hyperv_synic_kvm_only;
1805 uint64_t hyperv_features;
1806 bool hyperv_passthrough;
1807 OnOffAuto hyperv_no_nonarch_cs;
1808 uint32_t hyperv_vendor_id[3];
1809 uint32_t hyperv_interface_id[4];
1810 uint32_t hyperv_limits[3];
1811 bool hyperv_enforce_cpuid;
1812 uint32_t hyperv_ver_id_build;
1813 uint16_t hyperv_ver_id_major;
1814 uint16_t hyperv_ver_id_minor;
1815 uint32_t hyperv_ver_id_sp;
1816 uint8_t hyperv_ver_id_sb;
1817 uint32_t hyperv_ver_id_sn;
1818
1819 bool check_cpuid;
1820 bool enforce_cpuid;
1821
1822
1823
1824
1825
1826 bool force_features;
1827 bool expose_kvm;
1828 bool expose_tcg;
1829 bool migratable;
1830 bool migrate_smi_count;
1831 bool max_features;
1832 uint32_t apic_id;
1833
1834
1835
1836 bool vmware_cpuid_freq;
1837
1838
1839 bool cache_info_passthrough;
1840
1841
1842
1843 struct {
1844 uint32_t eax;
1845 uint32_t ebx;
1846 uint32_t ecx;
1847 uint32_t edx;
1848 } mwait;
1849
1850
1851 FeatureWordArray filtered_features;
1852
1853
1854
1855
1856
1857
1858 bool enable_pmu;
1859
1860
1861
1862
1863
1864
1865
1866
1867 uint64_t lbr_fmt;
1868
1869
1870
1871
1872
1873 bool enable_lmce;
1874
1875
1876
1877
1878
1879 bool enable_l3_cache;
1880
1881
1882
1883
1884 bool legacy_cache;
1885
1886
1887 bool enable_cpuid_0xb;
1888
1889
1890 bool full_cpuid_auto_level;
1891
1892
1893 bool vendor_cpuid_only;
1894
1895
1896 bool intel_pt_auto_level;
1897
1898
1899 bool fill_mtrr_mask;
1900
1901
1902 bool host_phys_bits;
1903
1904
1905 uint8_t host_phys_bits_limit;
1906
1907
1908 bool kvm_no_smi_migration;
1909
1910
1911 bool kvm_pv_enforce_cpuid;
1912
1913
1914 uint32_t phys_bits;
1915
1916
1917
1918 struct DeviceState *apic_state;
1919 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
1920 Notifier machine_done;
1921
1922 struct kvm_msrs *kvm_msr_buf;
1923
1924 int32_t node_id;
1925 int32_t socket_id;
1926 int32_t die_id;
1927 int32_t core_id;
1928 int32_t thread_id;
1929
1930 int32_t hv_max_vps;
1931};
1932
1933
1934#ifndef CONFIG_USER_ONLY
1935extern const VMStateDescription vmstate_x86_cpu;
1936#endif
1937
1938int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
1939
1940int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
1941 int cpuid, void *opaque);
1942int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
1943 int cpuid, void *opaque);
1944int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1945 void *opaque);
1946int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1947 void *opaque);
1948
1949void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
1950 Error **errp);
1951
1952void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags);
1953
1954hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
1955 MemTxAttrs *attrs);
1956
1957int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1958int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1959
1960void x86_cpu_list(void);
1961int cpu_x86_support_mca_broadcast(CPUX86State *env);
1962
1963#ifndef CONFIG_USER_ONLY
1964int cpu_get_pic_interrupt(CPUX86State *s);
1965
1966
1967void x86_register_ferr_irq(qemu_irq irq);
1968void fpu_check_raise_ferr_irq(CPUX86State *s);
1969void cpu_set_ignne(void);
1970void cpu_clear_ignne(void);
1971#endif
1972
1973
1974void cpu_sync_bndcs_hflags(CPUX86State *env);
1975
1976
1977
1978static inline void cpu_x86_load_seg_cache(CPUX86State *env,
1979 X86Seg seg_reg, unsigned int selector,
1980 target_ulong base,
1981 unsigned int limit,
1982 unsigned int flags)
1983{
1984 SegmentCache *sc;
1985 unsigned int new_hflags;
1986
1987 sc = &env->segs[seg_reg];
1988 sc->selector = selector;
1989 sc->base = base;
1990 sc->limit = limit;
1991 sc->flags = flags;
1992
1993
1994 {
1995 if (seg_reg == R_CS) {
1996#ifdef TARGET_X86_64
1997 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
1998
1999 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
2000 env->hflags &= ~(HF_ADDSEG_MASK);
2001 } else
2002#endif
2003 {
2004
2005 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
2006 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
2007 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
2008 new_hflags;
2009 }
2010 }
2011 if (seg_reg == R_SS) {
2012 int cpl = (flags >> DESC_DPL_SHIFT) & 3;
2013#if HF_CPL_MASK != 3
2014#error HF_CPL_MASK is hardcoded
2015#endif
2016 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
2017
2018 cpu_sync_bndcs_hflags(env);
2019 }
2020 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
2021 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
2022 if (env->hflags & HF_CS64_MASK) {
2023
2024 } else if (!(env->cr[0] & CR0_PE_MASK) ||
2025 (env->eflags & VM_MASK) ||
2026 !(env->hflags & HF_CS32_MASK)) {
2027
2028
2029
2030
2031
2032 new_hflags |= HF_ADDSEG_MASK;
2033 } else {
2034 new_hflags |= ((env->segs[R_DS].base |
2035 env->segs[R_ES].base |
2036 env->segs[R_SS].base) != 0) <<
2037 HF_ADDSEG_SHIFT;
2038 }
2039 env->hflags = (env->hflags &
2040 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
2041 }
2042}
2043
2044static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
2045 uint8_t sipi_vector)
2046{
2047 CPUState *cs = CPU(cpu);
2048 CPUX86State *env = &cpu->env;
2049
2050 env->eip = 0;
2051 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
2052 sipi_vector << 12,
2053 env->segs[R_CS].limit,
2054 env->segs[R_CS].flags);
2055 cs->halted = 0;
2056}
2057
2058int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
2059 target_ulong *base, unsigned int *limit,
2060 unsigned int *flags);
2061
2062
2063
2064
2065
2066
2067
2068void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector);
2069void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
2070void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
2071void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr);
2072void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr);
2073
2074
2075void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
2076 uint32_t vendor2, uint32_t vendor3);
2077typedef struct PropValue {
2078 const char *prop, *value;
2079} PropValue;
2080void x86_cpu_apply_props(X86CPU *cpu, PropValue *props);
2081
2082uint32_t cpu_x86_virtual_addr_width(CPUX86State *env);
2083
2084
2085void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2086 uint32_t *eax, uint32_t *ebx,
2087 uint32_t *ecx, uint32_t *edx);
2088void cpu_clear_apic_feature(CPUX86State *env);
2089void host_cpuid(uint32_t function, uint32_t count,
2090 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
2091
2092
2093void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
2094
2095#ifndef CONFIG_USER_ONLY
2096static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
2097{
2098 return !!attrs.secure;
2099}
2100
2101static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs)
2102{
2103 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs));
2104}
2105
2106
2107
2108
2109
2110void cpu_load_efer(CPUX86State *env, uint64_t val);
2111uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
2112uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
2113uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
2114uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
2115void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
2116void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
2117void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
2118void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
2119void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
2120#endif
2121
2122
2123void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
2124void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
2125void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
2126void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
2127
2128
2129uint64_t cpu_get_tsc(CPUX86State *env);
2130
2131#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
2132#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
2133#define CPU_RESOLVING_TYPE TYPE_X86_CPU
2134
2135#ifdef TARGET_X86_64
2136#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
2137#else
2138#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
2139#endif
2140
2141#define cpu_list x86_cpu_list
2142
2143
2144#define MMU_KSMAP_IDX 0
2145#define MMU_USER_IDX 1
2146#define MMU_KNOSMAP_IDX 2
2147static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
2148{
2149 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
2150 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
2151 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
2152}
2153
2154static inline int cpu_mmu_index_kernel(CPUX86State *env)
2155{
2156 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
2157 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK))
2158 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
2159}
2160
2161#define CC_DST (env->cc_dst)
2162#define CC_SRC (env->cc_src)
2163#define CC_SRC2 (env->cc_src2)
2164#define CC_OP (env->cc_op)
2165
2166#include "exec/cpu-all.h"
2167#include "svm.h"
2168
2169#if !defined(CONFIG_USER_ONLY)
2170#include "hw/i386/apic.h"
2171#endif
2172
2173static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
2174 target_ulong *cs_base, uint32_t *flags)
2175{
2176 *cs_base = env->segs[R_CS].base;
2177 *pc = *cs_base + env->eip;
2178 *flags = env->hflags |
2179 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
2180}
2181
2182void do_cpu_init(X86CPU *cpu);
2183void do_cpu_sipi(X86CPU *cpu);
2184
2185#define MCE_INJECT_BROADCAST 1
2186#define MCE_INJECT_UNCOND_AO 2
2187
2188void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
2189 uint64_t status, uint64_t mcg_status, uint64_t addr,
2190 uint64_t misc, int flags);
2191
2192uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
2193
2194static inline uint32_t cpu_compute_eflags(CPUX86State *env)
2195{
2196 uint32_t eflags = env->eflags;
2197 if (tcg_enabled()) {
2198 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK);
2199 }
2200 return eflags;
2201}
2202
2203static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
2204{
2205 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
2206}
2207
2208static inline int32_t x86_get_a20_mask(CPUX86State *env)
2209{
2210 if (env->hflags & HF_SMM_MASK) {
2211 return -1;
2212 } else {
2213 return env->a20_mask;
2214 }
2215}
2216
2217static inline bool cpu_has_vmx(CPUX86State *env)
2218{
2219 return env->features[FEAT_1_ECX] & CPUID_EXT_VMX;
2220}
2221
2222static inline bool cpu_has_svm(CPUX86State *env)
2223{
2224 return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM;
2225}
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243static inline bool cpu_vmx_maybe_enabled(CPUX86State *env)
2244{
2245 return cpu_has_vmx(env) &&
2246 ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK));
2247}
2248
2249
2250int get_pg_mode(CPUX86State *env);
2251
2252
2253void update_fp_status(CPUX86State *env);
2254void update_mxcsr_status(CPUX86State *env);
2255void update_mxcsr_from_sse_status(CPUX86State *env);
2256
2257static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
2258{
2259 env->mxcsr = mxcsr;
2260 if (tcg_enabled()) {
2261 update_mxcsr_status(env);
2262 }
2263}
2264
2265static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
2266{
2267 env->fpuc = fpuc;
2268 if (tcg_enabled()) {
2269 update_fp_status(env);
2270 }
2271}
2272
2273
2274void helper_lock_init(void);
2275
2276
2277#ifdef CONFIG_USER_ONLY
2278static inline void
2279cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
2280 uint64_t param, uintptr_t retaddr)
2281{ }
2282static inline bool
2283cpu_svm_has_intercept(CPUX86State *env, uint32_t type)
2284{ return false; }
2285#else
2286void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
2287 uint64_t param, uintptr_t retaddr);
2288bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type);
2289#endif
2290
2291
2292void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
2293void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
2294 TPRAccess access);
2295
2296
2297
2298
2299#define CPU_VERSION_LATEST -1
2300
2301
2302
2303
2304
2305#define CPU_VERSION_AUTO -2
2306
2307
2308#define CPU_VERSION_LEGACY 0
2309
2310typedef int X86CPUVersion;
2311
2312
2313
2314
2315
2316void x86_cpu_set_default_version(X86CPUVersion version);
2317
2318#define APIC_DEFAULT_ADDRESS 0xfee00000
2319#define APIC_SPACE_SIZE 0x100000
2320
2321
2322void x86_cpu_dump_local_apic_state(CPUState *cs, int flags);
2323
2324
2325bool cpu_is_bsp(X86CPU *cpu);
2326
2327void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen);
2328void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen);
2329void x86_update_hflags(CPUX86State* env);
2330
2331static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat)
2332{
2333 return !!(cpu->hyperv_features & BIT(feat));
2334}
2335
2336static inline uint64_t cr4_reserved_bits(CPUX86State *env)
2337{
2338 uint64_t reserved_bits = CR4_RESERVED_MASK;
2339 if (!env->features[FEAT_XSAVE]) {
2340 reserved_bits |= CR4_OSXSAVE_MASK;
2341 }
2342 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMEP)) {
2343 reserved_bits |= CR4_SMEP_MASK;
2344 }
2345 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) {
2346 reserved_bits |= CR4_SMAP_MASK;
2347 }
2348 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE)) {
2349 reserved_bits |= CR4_FSGSBASE_MASK;
2350 }
2351 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) {
2352 reserved_bits |= CR4_PKE_MASK;
2353 }
2354 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57)) {
2355 reserved_bits |= CR4_LA57_MASK;
2356 }
2357 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) {
2358 reserved_bits |= CR4_UMIP_MASK;
2359 }
2360 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) {
2361 reserved_bits |= CR4_PKS_MASK;
2362 }
2363 return reserved_bits;
2364}
2365
2366static inline bool ctl_has_irq(CPUX86State *env)
2367{
2368 uint32_t int_prio;
2369 uint32_t tpr;
2370
2371 int_prio = (env->int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT;
2372 tpr = env->int_ctl & V_TPR_MASK;
2373
2374 if (env->int_ctl & V_IGN_TPR_MASK) {
2375 return (env->int_ctl & V_IRQ_MASK);
2376 }
2377
2378 return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr);
2379}
2380
2381hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
2382 int *prot);
2383#if defined(TARGET_X86_64) && \
2384 defined(CONFIG_USER_ONLY) && \
2385 defined(CONFIG_LINUX)
2386# define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20)
2387#endif
2388
2389#endif
2390