1/* 2 * Definitions for Hyper-V guest/hypervisor interaction - x86-specific part 3 * 4 * Copyright (c) 2017-2018 Virtuozzo International GmbH. 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10#ifndef TARGET_I386_HYPERV_PROTO_H 11#define TARGET_I386_HYPERV_PROTO_H 12 13#include "hw/hyperv/hyperv-proto.h" 14 15#define HV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 16#define HV_CPUID_INTERFACE 0x40000001 17#define HV_CPUID_VERSION 0x40000002 18#define HV_CPUID_FEATURES 0x40000003 19#define HV_CPUID_ENLIGHTMENT_INFO 0x40000004 20#define HV_CPUID_IMPLEMENT_LIMITS 0x40000005 21#define HV_CPUID_NESTED_FEATURES 0x4000000A 22#define HV_CPUID_SYNDBG_VENDOR_AND_MAX_FUNCTIONS 0x40000080 23#define HV_CPUID_SYNDBG_INTERFACE 0x40000081 24#define HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES 0x40000082 25#define HV_CPUID_MIN 0x40000005 26#define HV_CPUID_MAX 0x4000ffff 27#define HV_HYPERVISOR_PRESENT_BIT 0x80000000 28 29/* 30 * HV_CPUID_FEATURES.EAX bits 31 */ 32#define HV_VP_RUNTIME_AVAILABLE (1u << 0) 33#define HV_TIME_REF_COUNT_AVAILABLE (1u << 1) 34#define HV_SYNIC_AVAILABLE (1u << 2) 35#define HV_SYNTIMERS_AVAILABLE (1u << 3) 36#define HV_APIC_ACCESS_AVAILABLE (1u << 4) 37#define HV_HYPERCALL_AVAILABLE (1u << 5) 38#define HV_VP_INDEX_AVAILABLE (1u << 6) 39#define HV_RESET_AVAILABLE (1u << 7) 40#define HV_REFERENCE_TSC_AVAILABLE (1u << 9) 41#define HV_ACCESS_FREQUENCY_MSRS (1u << 11) 42#define HV_ACCESS_REENLIGHTENMENTS_CONTROL (1u << 13) 43 44/* 45 * HV_CPUID_FEATURES.EBX bits 46 */ 47#define HV_POST_MESSAGES (1u << 4) 48#define HV_SIGNAL_EVENTS (1u << 5) 49 50/* 51 * HV_CPUID_FEATURES.EDX bits 52 */ 53#define HV_MWAIT_AVAILABLE (1u << 0) 54#define HV_GUEST_DEBUGGING_AVAILABLE (1u << 1) 55#define HV_PERF_MONITOR_AVAILABLE (1u << 2) 56#define HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1u << 3) 57#define HV_HYPERCALL_XMM_INPUT_AVAILABLE (1u << 4) 58#define HV_GUEST_IDLE_STATE_AVAILABLE (1u << 5) 59#define HV_FREQUENCY_MSRS_AVAILABLE (1u << 8) 60#define HV_GUEST_CRASH_MSR_AVAILABLE (1u << 10) 61#define HV_FEATURE_DEBUG_MSRS_AVAILABLE (1u << 11) 62#define HV_EXT_GVA_RANGES_FLUSH_AVAILABLE (1u << 14) 63#define HV_STIMER_DIRECT_MODE_AVAILABLE (1u << 19) 64 65/* 66 * HV_CPUID_FEATURES.EBX bits 67 */ 68#define HV_PARTITION_DEBUGGING_ALLOWED (1u << 12) 69 70/* 71 * HV_CPUID_ENLIGHTMENT_INFO.EAX bits 72 */ 73#define HV_AS_SWITCH_RECOMMENDED (1u << 0) 74#define HV_LOCAL_TLB_FLUSH_RECOMMENDED (1u << 1) 75#define HV_REMOTE_TLB_FLUSH_RECOMMENDED (1u << 2) 76#define HV_APIC_ACCESS_RECOMMENDED (1u << 3) 77#define HV_SYSTEM_RESET_RECOMMENDED (1u << 4) 78#define HV_RELAXED_TIMING_RECOMMENDED (1u << 5) 79#define HV_DEPRECATING_AEOI_RECOMMENDED (1u << 9) 80#define HV_CLUSTER_IPI_RECOMMENDED (1u << 10) 81#define HV_EX_PROCESSOR_MASKS_RECOMMENDED (1u << 11) 82#define HV_ENLIGHTENED_VMCS_RECOMMENDED (1u << 14) 83#define HV_NO_NONARCH_CORESHARING (1u << 18) 84 85/* 86 * HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES.EAX bits 87 */ 88#define HV_SYNDBG_CAP_ALLOW_KERNEL_DEBUGGING (1u << 1) 89 90/* 91 * HV_CPUID_NESTED_FEATURES.EAX bits 92 */ 93#define HV_NESTED_DIRECT_FLUSH (1u << 17) 94#define HV_NESTED_MSR_BITMAP (1u << 19) 95 96/* 97 * Basic virtualized MSRs 98 */ 99#define HV_X64_MSR_GUEST_OS_ID 0x40000000 100#define HV_X64_MSR_HYPERCALL 0x40000001 101#define HV_X64_MSR_VP_INDEX 0x40000002 102#define HV_X64_MSR_RESET 0x40000003 103#define HV_X64_MSR_VP_RUNTIME 0x40000010 104#define HV_X64_MSR_TIME_REF_COUNT 0x40000020 105#define HV_X64_MSR_REFERENCE_TSC 0x40000021 106#define HV_X64_MSR_TSC_FREQUENCY 0x40000022 107#define HV_X64_MSR_APIC_FREQUENCY 0x40000023 108 109/* 110 * Virtual APIC MSRs 111 */ 112#define HV_X64_MSR_EOI 0x40000070 113#define HV_X64_MSR_ICR 0x40000071 114#define HV_X64_MSR_TPR 0x40000072 115#define HV_X64_MSR_APIC_ASSIST_PAGE 0x40000073 116 117/* 118 * Synthetic interrupt controller MSRs 119 */ 120#define HV_X64_MSR_SCONTROL 0x40000080 121#define HV_X64_MSR_SVERSION 0x40000081 122#define HV_X64_MSR_SIEFP 0x40000082 123#define HV_X64_MSR_SIMP 0x40000083 124#define HV_X64_MSR_EOM 0x40000084 125#define HV_X64_MSR_SINT0 0x40000090 126#define HV_X64_MSR_SINT1 0x40000091 127#define HV_X64_MSR_SINT2 0x40000092 128#define HV_X64_MSR_SINT3 0x40000093 129#define HV_X64_MSR_SINT4 0x40000094 130#define HV_X64_MSR_SINT5 0x40000095 131#define HV_X64_MSR_SINT6 0x40000096 132#define HV_X64_MSR_SINT7 0x40000097 133#define HV_X64_MSR_SINT8 0x40000098 134#define HV_X64_MSR_SINT9 0x40000099 135#define HV_X64_MSR_SINT10 0x4000009A 136#define HV_X64_MSR_SINT11 0x4000009B 137#define HV_X64_MSR_SINT12 0x4000009C 138#define HV_X64_MSR_SINT13 0x4000009D 139#define HV_X64_MSR_SINT14 0x4000009E 140#define HV_X64_MSR_SINT15 0x4000009F 141 142/* 143 * Synthetic timer MSRs 144 */ 145#define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 146#define HV_X64_MSR_STIMER0_COUNT 0x400000B1 147#define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 148#define HV_X64_MSR_STIMER1_COUNT 0x400000B3 149#define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 150#define HV_X64_MSR_STIMER2_COUNT 0x400000B5 151#define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 152#define HV_X64_MSR_STIMER3_COUNT 0x400000B7 153 154/* 155 * Hyper-V Synthetic debug options MSR 156 */ 157#define HV_X64_MSR_SYNDBG_CONTROL 0x400000F1 158#define HV_X64_MSR_SYNDBG_STATUS 0x400000F2 159#define HV_X64_MSR_SYNDBG_SEND_BUFFER 0x400000F3 160#define HV_X64_MSR_SYNDBG_RECV_BUFFER 0x400000F4 161#define HV_X64_MSR_SYNDBG_PENDING_BUFFER 0x400000F5 162#define HV_X64_MSR_SYNDBG_OPTIONS 0x400000FF 163 164#define HV_X64_SYNDBG_OPTION_USE_HCALLS BIT(2) 165 166/* 167 * Guest crash notification MSRs 168 */ 169#define HV_X64_MSR_CRASH_P0 0x40000100 170#define HV_X64_MSR_CRASH_P1 0x40000101 171#define HV_X64_MSR_CRASH_P2 0x40000102 172#define HV_X64_MSR_CRASH_P3 0x40000103 173#define HV_X64_MSR_CRASH_P4 0x40000104 174#define HV_CRASH_PARAMS (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0 + 1) 175#define HV_X64_MSR_CRASH_CTL 0x40000105 176#define HV_CRASH_CTL_NOTIFY (1ull << 63) 177 178/* 179 * Reenlightenment notification MSRs 180 */ 181#define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 182#define HV_REENLIGHTENMENT_ENABLE_BIT (1u << 16) 183#define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 184#define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 185 186/* 187 * Hypercall MSR bits 188 */ 189#define HV_HYPERCALL_ENABLE (1u << 0) 190 191/* 192 * Synthetic interrupt controller definitions 193 */ 194#define HV_SYNIC_VERSION 1 195#define HV_SYNIC_ENABLE (1u << 0) 196#define HV_SIMP_ENABLE (1u << 0) 197#define HV_SIEFP_ENABLE (1u << 0) 198#define HV_SINT_MASKED (1u << 16) 199#define HV_SINT_AUTO_EOI (1u << 17) 200#define HV_SINT_VECTOR_MASK 0xff 201 202#define HV_STIMER_COUNT 4 203 204/* 205 * Synthetic debugger control definitions 206 */ 207#define HV_SYNDBG_CONTROL_SEND (1u << 0) 208#define HV_SYNDBG_CONTROL_RECV (1u << 1) 209#define HV_SYNDBG_CONTROL_SEND_SIZE(ctl) ((ctl >> 16) & 0xffff) 210#define HV_SYNDBG_STATUS_INVALID (0) 211#define HV_SYNDBG_STATUS_SEND_SUCCESS (1u << 0) 212#define HV_SYNDBG_STATUS_RECV_SUCCESS (1u << 2) 213#define HV_SYNDBG_STATUS_RESET (1u << 3) 214#define HV_SYNDBG_STATUS_SET_SIZE(st, sz) (st | (sz << 16)) 215 216#endif 217