1#ifndef SVM_H 2#define SVM_H 3 4#define TLB_CONTROL_DO_NOTHING 0 5#define TLB_CONTROL_FLUSH_ALL_ASID 1 6 7#define V_TPR_MASK 0x0f 8 9#define V_IRQ_SHIFT 8 10#define V_IRQ_MASK (1 << V_IRQ_SHIFT) 11 12#define V_GIF_ENABLED_SHIFT 25 13#define V_GIF_ENABLED_MASK (1 << V_GIF_ENABLED_SHIFT) 14 15#define V_GIF_SHIFT 9 16#define V_GIF_MASK (1 << V_GIF_SHIFT) 17 18#define V_INTR_PRIO_SHIFT 16 19#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT) 20 21#define V_IGN_TPR_SHIFT 20 22#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT) 23 24#define V_INTR_MASKING_SHIFT 24 25#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT) 26 27#define V_VMLOAD_VMSAVE_ENABLED_MASK (1 << 1) 28 29#define SVM_INTERRUPT_SHADOW_MASK 1 30 31#define SVM_IOIO_STR_SHIFT 2 32#define SVM_IOIO_REP_SHIFT 3 33#define SVM_IOIO_SIZE_SHIFT 4 34#define SVM_IOIO_ASIZE_SHIFT 7 35 36#define SVM_IOIO_TYPE_MASK 1 37#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT) 38#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT) 39#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT) 40#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT) 41 42#define SVM_EVTINJ_VEC_MASK 0xff 43 44#define SVM_EVTINJ_TYPE_SHIFT 8 45#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT) 46 47#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT) 48#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT) 49#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT) 50#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT) 51 52#define SVM_EVTINJ_VALID (1 << 31) 53#define SVM_EVTINJ_VALID_ERR (1 << 11) 54 55#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK 56 57#define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR 58#define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI 59#define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT 60#define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT 61 62#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID 63#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR 64 65#define SVM_EXIT_READ_CR0 0x000 66#define SVM_EXIT_READ_CR3 0x003 67#define SVM_EXIT_READ_CR4 0x004 68#define SVM_EXIT_READ_CR8 0x008 69#define SVM_EXIT_WRITE_CR0 0x010 70#define SVM_EXIT_WRITE_CR3 0x013 71#define SVM_EXIT_WRITE_CR4 0x014 72#define SVM_EXIT_WRITE_CR8 0x018 73#define SVM_EXIT_READ_DR0 0x020 74#define SVM_EXIT_READ_DR1 0x021 75#define SVM_EXIT_READ_DR2 0x022 76#define SVM_EXIT_READ_DR3 0x023 77#define SVM_EXIT_READ_DR4 0x024 78#define SVM_EXIT_READ_DR5 0x025 79#define SVM_EXIT_READ_DR6 0x026 80#define SVM_EXIT_READ_DR7 0x027 81#define SVM_EXIT_WRITE_DR0 0x030 82#define SVM_EXIT_WRITE_DR1 0x031 83#define SVM_EXIT_WRITE_DR2 0x032 84#define SVM_EXIT_WRITE_DR3 0x033 85#define SVM_EXIT_WRITE_DR4 0x034 86#define SVM_EXIT_WRITE_DR5 0x035 87#define SVM_EXIT_WRITE_DR6 0x036 88#define SVM_EXIT_WRITE_DR7 0x037 89#define SVM_EXIT_EXCP_BASE 0x040 90#define SVM_EXIT_INTR 0x060 91#define SVM_EXIT_NMI 0x061 92#define SVM_EXIT_SMI 0x062 93#define SVM_EXIT_INIT 0x063 94#define SVM_EXIT_VINTR 0x064 95#define SVM_EXIT_CR0_SEL_WRITE 0x065 96#define SVM_EXIT_IDTR_READ 0x066 97#define SVM_EXIT_GDTR_READ 0x067 98#define SVM_EXIT_LDTR_READ 0x068 99#define SVM_EXIT_TR_READ 0x069 100#define SVM_EXIT_IDTR_WRITE 0x06a 101#define SVM_EXIT_GDTR_WRITE 0x06b 102#define SVM_EXIT_LDTR_WRITE 0x06c 103#define SVM_EXIT_TR_WRITE 0x06d 104#define SVM_EXIT_RDTSC 0x06e 105#define SVM_EXIT_RDPMC 0x06f 106#define SVM_EXIT_PUSHF 0x070 107#define SVM_EXIT_POPF 0x071 108#define SVM_EXIT_CPUID 0x072 109#define SVM_EXIT_RSM 0x073 110#define SVM_EXIT_IRET 0x074 111#define SVM_EXIT_SWINT 0x075 112#define SVM_EXIT_INVD 0x076 113#define SVM_EXIT_PAUSE 0x077 114#define SVM_EXIT_HLT 0x078 115#define SVM_EXIT_INVLPG 0x079 116#define SVM_EXIT_INVLPGA 0x07a 117#define SVM_EXIT_IOIO 0x07b 118#define SVM_EXIT_MSR 0x07c 119#define SVM_EXIT_TASK_SWITCH 0x07d 120#define SVM_EXIT_FERR_FREEZE 0x07e 121#define SVM_EXIT_SHUTDOWN 0x07f 122#define SVM_EXIT_VMRUN 0x080 123#define SVM_EXIT_VMMCALL 0x081 124#define SVM_EXIT_VMLOAD 0x082 125#define SVM_EXIT_VMSAVE 0x083 126#define SVM_EXIT_STGI 0x084 127#define SVM_EXIT_CLGI 0x085 128#define SVM_EXIT_SKINIT 0x086 129#define SVM_EXIT_RDTSCP 0x087 130#define SVM_EXIT_ICEBP 0x088 131#define SVM_EXIT_WBINVD 0x089 132/* only included in documentation, maybe wrong */ 133#define SVM_EXIT_MONITOR 0x08a 134#define SVM_EXIT_MWAIT 0x08b 135#define SVM_EXIT_NPF 0x400 136 137#define SVM_EXIT_ERR -1 138 139#define SVM_CR0_SELECTIVE_MASK (1 << 3 | 1) /* TS and MP */ 140 141#define SVM_NPT_ENABLED (1 << 0) 142 143#define SVM_NPTEXIT_GPA (1ULL << 32) 144#define SVM_NPTEXIT_GPT (1ULL << 33) 145 146#define SVM_CR0_RESERVED_MASK 0xffffffff00000000U 147 148#define SVM_MSRPM_SIZE (1ULL << 13) 149#define SVM_IOPM_SIZE ((1ULL << 13) + 1) 150 151struct QEMU_PACKED vmcb_control_area { 152 uint16_t intercept_cr_read; 153 uint16_t intercept_cr_write; 154 uint16_t intercept_dr_read; 155 uint16_t intercept_dr_write; 156 uint32_t intercept_exceptions; 157 uint64_t intercept; 158 uint8_t reserved_1[44]; 159 uint64_t iopm_base_pa; 160 uint64_t msrpm_base_pa; 161 uint64_t tsc_offset; 162 uint32_t asid; 163 uint8_t tlb_ctl; 164 uint8_t reserved_2[3]; 165 uint32_t int_ctl; 166 uint32_t int_vector; 167 uint32_t int_state; 168 uint8_t reserved_3[4]; 169 uint64_t exit_code; 170 uint64_t exit_info_1; 171 uint64_t exit_info_2; 172 uint32_t exit_int_info; 173 uint32_t exit_int_info_err; 174 uint64_t nested_ctl; 175 uint8_t reserved_4[16]; 176 uint32_t event_inj; 177 uint32_t event_inj_err; 178 uint64_t nested_cr3; 179 uint64_t lbr_ctl; 180 uint8_t reserved_5[832]; 181}; 182 183struct QEMU_PACKED vmcb_seg { 184 uint16_t selector; 185 uint16_t attrib; 186 uint32_t limit; 187 uint64_t base; 188}; 189 190struct QEMU_PACKED vmcb_save_area { 191 struct vmcb_seg es; 192 struct vmcb_seg cs; 193 struct vmcb_seg ss; 194 struct vmcb_seg ds; 195 struct vmcb_seg fs; 196 struct vmcb_seg gs; 197 struct vmcb_seg gdtr; 198 struct vmcb_seg ldtr; 199 struct vmcb_seg idtr; 200 struct vmcb_seg tr; 201 uint8_t reserved_1[43]; 202 uint8_t cpl; 203 uint8_t reserved_2[4]; 204 uint64_t efer; 205 uint8_t reserved_3[112]; 206 uint64_t cr4; 207 uint64_t cr3; 208 uint64_t cr0; 209 uint64_t dr7; 210 uint64_t dr6; 211 uint64_t rflags; 212 uint64_t rip; 213 uint8_t reserved_4[88]; 214 uint64_t rsp; 215 uint8_t reserved_5[24]; 216 uint64_t rax; 217 uint64_t star; 218 uint64_t lstar; 219 uint64_t cstar; 220 uint64_t sfmask; 221 uint64_t kernel_gs_base; 222 uint64_t sysenter_cs; 223 uint64_t sysenter_esp; 224 uint64_t sysenter_eip; 225 uint64_t cr2; 226 uint8_t reserved_6[32]; 227 uint64_t g_pat; 228 uint64_t dbgctl; 229 uint64_t br_from; 230 uint64_t br_to; 231 uint64_t last_excp_from; 232 uint64_t last_excp_to; 233}; 234 235struct QEMU_PACKED vmcb { 236 struct vmcb_control_area control; 237 struct vmcb_save_area save; 238}; 239 240#endif 241