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20#ifndef I386_HELPER_TCG_H
21#define I386_HELPER_TCG_H
22
23#include "exec/exec-all.h"
24
25
26#define TARGET_MAX_INSN_SIZE 16
27
28#if defined(TARGET_X86_64)
29# define TCG_PHYS_ADDR_BITS 40
30#else
31# define TCG_PHYS_ADDR_BITS 36
32#endif
33
34QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADDR_SPACE_BITS);
35
36
37
38
39
40void x86_cpu_do_interrupt(CPUState *cpu);
41#ifndef CONFIG_USER_ONLY
42bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
43#endif
44
45
46#ifdef CONFIG_USER_ONLY
47void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr,
48 MMUAccessType access_type,
49 bool maperr, uintptr_t ra);
50#else
51bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
52 MMUAccessType access_type, int mmu_idx,
53 bool probe, uintptr_t retaddr);
54#endif
55
56void breakpoint_handler(CPUState *cs);
57
58
59static inline target_long lshift(target_long x, int n)
60{
61 if (n >= 0) {
62 return x << n;
63 } else {
64 return x >> (-n);
65 }
66}
67
68
69void tcg_x86_init(void);
70
71
72G_NORETURN void raise_exception(CPUX86State *env, int exception_index);
73G_NORETURN void raise_exception_ra(CPUX86State *env, int exception_index,
74 uintptr_t retaddr);
75G_NORETURN void raise_exception_err(CPUX86State *env, int exception_index,
76 int error_code);
77G_NORETURN void raise_exception_err_ra(CPUX86State *env, int exception_index,
78 int error_code, uintptr_t retaddr);
79G_NORETURN void raise_interrupt(CPUX86State *nenv, int intno, int is_int,
80 int error_code, int next_eip_addend);
81
82
83extern const uint8_t parity_table[256];
84
85
86void cpu_load_eflags(CPUX86State *env, int eflags, int update_mask);
87G_NORETURN void do_pause(CPUX86State *env);
88
89
90#ifndef CONFIG_USER_ONLY
91G_NORETURN void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code,
92 uint64_t exit_info_1, uintptr_t retaddr);
93void do_vmexit(CPUX86State *env);
94#endif
95
96
97void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
98void do_interrupt_all(X86CPU *cpu, int intno, int is_int,
99 int error_code, target_ulong next_eip, int is_hw);
100void handle_even_inj(CPUX86State *env, int intno, int is_int,
101 int error_code, int is_hw, int rm);
102int exception_has_error_code(int intno);
103
104
105void do_smm_enter(X86CPU *cpu);
106
107
108bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update);
109
110#endif
111