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8#include "qemu/osdep.h"
9#include "cpu.h"
10#include "tcg/tcg-op.h"
11#include "exec/translator.h"
12#include "exec/helper-proto.h"
13#include "exec/helper-gen.h"
14
15#include "exec/translator.h"
16#include "exec/log.h"
17#include "qemu/qemu-print.h"
18#include "fpu/softfloat.h"
19#include "translate.h"
20#include "internals.h"
21
22
23TCGv cpu_gpr[32], cpu_pc;
24static TCGv cpu_lladdr, cpu_llval;
25TCGv_i64 cpu_fpr[32];
26
27#include "exec/gen-icount.h"
28
29#define DISAS_STOP DISAS_TARGET_0
30#define DISAS_EXIT DISAS_TARGET_1
31#define DISAS_EXIT_UPDATE DISAS_TARGET_2
32
33static inline int plus_1(DisasContext *ctx, int x)
34{
35 return x + 1;
36}
37
38static inline int shl_2(DisasContext *ctx, int x)
39{
40 return x << 2;
41}
42
43
44
45
46
47static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
48{
49 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
50}
51
52void generate_exception(DisasContext *ctx, int excp)
53{
54 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
55 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
56 ctx->base.is_jmp = DISAS_NORETURN;
57}
58
59static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
60{
61 if (translator_use_goto_tb(&ctx->base, dest)) {
62 tcg_gen_goto_tb(n);
63 tcg_gen_movi_tl(cpu_pc, dest);
64 tcg_gen_exit_tb(ctx->base.tb, n);
65 } else {
66 tcg_gen_movi_tl(cpu_pc, dest);
67 tcg_gen_lookup_and_goto_ptr();
68 }
69}
70
71static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,
72 CPUState *cs)
73{
74 int64_t bound;
75 DisasContext *ctx = container_of(dcbase, DisasContext, base);
76
77 ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
78 ctx->mem_idx = ctx->base.tb->flags;
79
80
81 bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
82 ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
83
84 ctx->ntemp = 0;
85 memset(ctx->temp, 0, sizeof(ctx->temp));
86
87 ctx->zero = tcg_constant_tl(0);
88}
89
90static void loongarch_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
91{
92}
93
94static void loongarch_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
95{
96 DisasContext *ctx = container_of(dcbase, DisasContext, base);
97
98 tcg_gen_insn_start(ctx->base.pc_next);
99}
100
101
102
103
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106
107
108
109static TCGv temp_new(DisasContext *ctx)
110{
111 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
112 return ctx->temp[ctx->ntemp++] = tcg_temp_new();
113}
114
115static TCGv gpr_src(DisasContext *ctx, int reg_num, DisasExtend src_ext)
116{
117 TCGv t;
118
119 if (reg_num == 0) {
120 return ctx->zero;
121 }
122
123 switch (src_ext) {
124 case EXT_NONE:
125 return cpu_gpr[reg_num];
126 case EXT_SIGN:
127 t = temp_new(ctx);
128 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
129 return t;
130 case EXT_ZERO:
131 t = temp_new(ctx);
132 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
133 return t;
134 }
135 g_assert_not_reached();
136}
137
138static TCGv gpr_dst(DisasContext *ctx, int reg_num, DisasExtend dst_ext)
139{
140 if (reg_num == 0 || dst_ext) {
141 return temp_new(ctx);
142 }
143 return cpu_gpr[reg_num];
144}
145
146static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext)
147{
148 if (reg_num != 0) {
149 switch (dst_ext) {
150 case EXT_NONE:
151 tcg_gen_mov_tl(cpu_gpr[reg_num], t);
152 break;
153 case EXT_SIGN:
154 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
155 break;
156 case EXT_ZERO:
157 tcg_gen_ext32u_tl(cpu_gpr[reg_num], t);
158 break;
159 default:
160 g_assert_not_reached();
161 }
162 }
163}
164
165#include "decode-insns.c.inc"
166#include "insn_trans/trans_arith.c.inc"
167#include "insn_trans/trans_shift.c.inc"
168#include "insn_trans/trans_bit.c.inc"
169#include "insn_trans/trans_memory.c.inc"
170#include "insn_trans/trans_atomic.c.inc"
171#include "insn_trans/trans_extra.c.inc"
172#include "insn_trans/trans_farith.c.inc"
173#include "insn_trans/trans_fcmp.c.inc"
174#include "insn_trans/trans_fcnv.c.inc"
175#include "insn_trans/trans_fmov.c.inc"
176#include "insn_trans/trans_fmemory.c.inc"
177#include "insn_trans/trans_branch.c.inc"
178#include "insn_trans/trans_privileged.c.inc"
179
180static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
181{
182 CPULoongArchState *env = cs->env_ptr;
183 DisasContext *ctx = container_of(dcbase, DisasContext, base);
184
185 ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
186
187 if (!decode(ctx, ctx->opcode)) {
188 qemu_log_mask(LOG_UNIMP, "Error: unknown opcode. "
189 TARGET_FMT_lx ": 0x%x\n",
190 ctx->base.pc_next, ctx->opcode);
191 generate_exception(ctx, EXCCODE_INE);
192 }
193
194 for (int i = ctx->ntemp - 1; i >= 0; --i) {
195 tcg_temp_free(ctx->temp[i]);
196 ctx->temp[i] = NULL;
197 }
198 ctx->ntemp = 0;
199
200 ctx->base.pc_next += 4;
201}
202
203static void loongarch_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
204{
205 DisasContext *ctx = container_of(dcbase, DisasContext, base);
206
207 switch (ctx->base.is_jmp) {
208 case DISAS_STOP:
209 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
210 tcg_gen_lookup_and_goto_ptr();
211 break;
212 case DISAS_TOO_MANY:
213 gen_goto_tb(ctx, 0, ctx->base.pc_next);
214 break;
215 case DISAS_NORETURN:
216 break;
217 case DISAS_EXIT_UPDATE:
218 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
219 QEMU_FALLTHROUGH;
220 case DISAS_EXIT:
221 tcg_gen_exit_tb(NULL, 0);
222 break;
223 default:
224 g_assert_not_reached();
225 }
226}
227
228static void loongarch_tr_disas_log(const DisasContextBase *dcbase,
229 CPUState *cpu, FILE *logfile)
230{
231 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
232 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
233}
234
235static const TranslatorOps loongarch_tr_ops = {
236 .init_disas_context = loongarch_tr_init_disas_context,
237 .tb_start = loongarch_tr_tb_start,
238 .insn_start = loongarch_tr_insn_start,
239 .translate_insn = loongarch_tr_translate_insn,
240 .tb_stop = loongarch_tr_tb_stop,
241 .disas_log = loongarch_tr_disas_log,
242};
243
244void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
245{
246 DisasContext ctx;
247
248 translator_loop(&loongarch_tr_ops, &ctx.base, cs, tb, max_insns);
249}
250
251void loongarch_translate_init(void)
252{
253 int i;
254
255 cpu_gpr[0] = NULL;
256 for (i = 1; i < 32; i++) {
257 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
258 offsetof(CPULoongArchState, gpr[i]),
259 regnames[i]);
260 }
261
262 for (i = 0; i < 32; i++) {
263 int off = offsetof(CPULoongArchState, fpr[i]);
264 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, off, fregnames[i]);
265 }
266
267 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPULoongArchState, pc), "pc");
268 cpu_lladdr = tcg_global_mem_new(cpu_env,
269 offsetof(CPULoongArchState, lladdr), "lladdr");
270 cpu_llval = tcg_global_mem_new(cpu_env,
271 offsetof(CPULoongArchState, llval), "llval");
272}
273
274void restore_state_to_opc(CPULoongArchState *env, TranslationBlock *tb,
275 target_ulong *data)
276{
277 env->pc = data[0];
278}
279