1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21#include "qemu/osdep.h"
22#include "disas/dis-asm.h"
23#include "exec/gdbstub.h"
24#include "kvm_ppc.h"
25#include "sysemu/cpus.h"
26#include "sysemu/hw_accel.h"
27#include "sysemu/tcg.h"
28#include "cpu-models.h"
29#include "mmu-hash32.h"
30#include "mmu-hash64.h"
31#include "qemu/error-report.h"
32#include "qemu/module.h"
33#include "qemu/qemu-print.h"
34#include "qapi/error.h"
35#include "qapi/qmp/qnull.h"
36#include "qapi/visitor.h"
37#include "hw/qdev-properties.h"
38#include "hw/ppc/ppc.h"
39#include "mmu-book3s-v3.h"
40#include "qemu/cutils.h"
41#include "disas/capstone.h"
42#include "fpu/softfloat.h"
43#include "qapi/qapi-commands-machine-target.h"
44
45#include "helper_regs.h"
46#include "internal.h"
47#include "spr_common.h"
48#include "power8-pmu.h"
49
50#ifndef CONFIG_USER_ONLY
51#include "hw/boards.h"
52#endif
53
54
55
56
57static inline void vscr_init(CPUPPCState *env, uint32_t val)
58{
59
60 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
61 ppc_store_vscr(env, val);
62}
63
64static void register_745_sprs(CPUPPCState *env)
65{
66
67 spr_register(env, SPR_SPRG4, "SPRG4",
68 SPR_NOACCESS, SPR_NOACCESS,
69 &spr_read_generic, &spr_write_generic,
70 0x00000000);
71 spr_register(env, SPR_SPRG5, "SPRG5",
72 SPR_NOACCESS, SPR_NOACCESS,
73 &spr_read_generic, &spr_write_generic,
74 0x00000000);
75 spr_register(env, SPR_SPRG6, "SPRG6",
76 SPR_NOACCESS, SPR_NOACCESS,
77 &spr_read_generic, &spr_write_generic,
78 0x00000000);
79 spr_register(env, SPR_SPRG7, "SPRG7",
80 SPR_NOACCESS, SPR_NOACCESS,
81 &spr_read_generic, &spr_write_generic,
82 0x00000000);
83
84
85 spr_register(env, SPR_HID0, "HID0",
86 SPR_NOACCESS, SPR_NOACCESS,
87 &spr_read_generic, &spr_write_generic,
88 0x00000000);
89
90 spr_register(env, SPR_HID1, "HID1",
91 SPR_NOACCESS, SPR_NOACCESS,
92 &spr_read_generic, &spr_write_generic,
93 0x00000000);
94
95 spr_register(env, SPR_HID2, "HID2",
96 SPR_NOACCESS, SPR_NOACCESS,
97 &spr_read_generic, &spr_write_generic,
98 0x00000000);
99}
100
101static void register_755_sprs(CPUPPCState *env)
102{
103
104 spr_register(env, SPR_L2CR, "L2CR",
105 SPR_NOACCESS, SPR_NOACCESS,
106 &spr_read_generic, spr_access_nop,
107 0x00000000);
108
109 spr_register(env, SPR_L2PMCR, "L2PMCR",
110 SPR_NOACCESS, SPR_NOACCESS,
111 &spr_read_generic, &spr_write_generic,
112 0x00000000);
113}
114
115
116static void register_7xx_sprs(CPUPPCState *env)
117{
118
119 spr_register_kvm(env, SPR_DABR, "DABR",
120 SPR_NOACCESS, SPR_NOACCESS,
121 &spr_read_generic, &spr_write_generic,
122 KVM_REG_PPC_DABR, 0x00000000);
123
124 spr_register(env, SPR_IABR, "IABR",
125 SPR_NOACCESS, SPR_NOACCESS,
126 &spr_read_generic, &spr_write_generic,
127 0x00000000);
128
129 spr_register(env, SPR_ICTC, "ICTC",
130 SPR_NOACCESS, SPR_NOACCESS,
131 &spr_read_generic, &spr_write_generic,
132 0x00000000);
133
134 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
135 SPR_NOACCESS, SPR_NOACCESS,
136 &spr_read_generic, &spr_write_generic,
137 0x00000000);
138
139 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
140 SPR_NOACCESS, SPR_NOACCESS,
141 &spr_read_generic, &spr_write_generic,
142 0x00000000);
143
144 spr_register(env, SPR_7XX_PMC1, "PMC1",
145 SPR_NOACCESS, SPR_NOACCESS,
146 &spr_read_generic, &spr_write_generic,
147 0x00000000);
148
149 spr_register(env, SPR_7XX_PMC2, "PMC2",
150 SPR_NOACCESS, SPR_NOACCESS,
151 &spr_read_generic, &spr_write_generic,
152 0x00000000);
153
154 spr_register(env, SPR_7XX_PMC3, "PMC3",
155 SPR_NOACCESS, SPR_NOACCESS,
156 &spr_read_generic, &spr_write_generic,
157 0x00000000);
158
159 spr_register(env, SPR_7XX_PMC4, "PMC4",
160 SPR_NOACCESS, SPR_NOACCESS,
161 &spr_read_generic, &spr_write_generic,
162 0x00000000);
163
164 spr_register(env, SPR_7XX_SIAR, "SIAR",
165 SPR_NOACCESS, SPR_NOACCESS,
166 &spr_read_generic, SPR_NOACCESS,
167 0x00000000);
168
169 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
170 &spr_read_ureg, SPR_NOACCESS,
171 &spr_read_ureg, SPR_NOACCESS,
172 0x00000000);
173
174 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
175 &spr_read_ureg, SPR_NOACCESS,
176 &spr_read_ureg, SPR_NOACCESS,
177 0x00000000);
178
179 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
180 &spr_read_ureg, SPR_NOACCESS,
181 &spr_read_ureg, SPR_NOACCESS,
182 0x00000000);
183
184 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
185 &spr_read_ureg, SPR_NOACCESS,
186 &spr_read_ureg, SPR_NOACCESS,
187 0x00000000);
188
189 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
190 &spr_read_ureg, SPR_NOACCESS,
191 &spr_read_ureg, SPR_NOACCESS,
192 0x00000000);
193
194 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
195 &spr_read_ureg, SPR_NOACCESS,
196 &spr_read_ureg, SPR_NOACCESS,
197 0x00000000);
198
199 spr_register(env, SPR_7XX_USIAR, "USIAR",
200 &spr_read_ureg, SPR_NOACCESS,
201 &spr_read_ureg, SPR_NOACCESS,
202 0x00000000);
203
204 spr_register(env, SPR_EAR, "EAR",
205 SPR_NOACCESS, SPR_NOACCESS,
206 &spr_read_generic, &spr_write_generic,
207 0x00000000);
208
209
210 spr_register(env, SPR_HID0, "HID0",
211 SPR_NOACCESS, SPR_NOACCESS,
212 &spr_read_generic, &spr_write_generic,
213 0x00000000);
214
215 spr_register(env, SPR_HID1, "HID1",
216 SPR_NOACCESS, SPR_NOACCESS,
217 &spr_read_generic, &spr_write_generic,
218 0x00000000);
219}
220
221#ifdef TARGET_PPC64
222static void register_amr_sprs(CPUPPCState *env)
223{
224#ifndef CONFIG_USER_ONLY
225
226
227
228
229
230
231
232 spr_register(env, SPR_UAMR, "UAMR",
233 &spr_read_generic, &spr_write_amr,
234 &spr_read_generic, &spr_write_amr,
235 0);
236 spr_register_kvm_hv(env, SPR_AMR, "AMR",
237 SPR_NOACCESS, SPR_NOACCESS,
238 &spr_read_generic, &spr_write_amr,
239 &spr_read_generic, &spr_write_generic,
240 KVM_REG_PPC_AMR, 0);
241 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
242 SPR_NOACCESS, SPR_NOACCESS,
243 &spr_read_generic, &spr_write_uamor,
244 &spr_read_generic, &spr_write_generic,
245 KVM_REG_PPC_UAMOR, 0);
246 spr_register_hv(env, SPR_AMOR, "AMOR",
247 SPR_NOACCESS, SPR_NOACCESS,
248 SPR_NOACCESS, SPR_NOACCESS,
249 &spr_read_generic, &spr_write_generic,
250 0);
251#endif
252}
253
254static void register_iamr_sprs(CPUPPCState *env)
255{
256#ifndef CONFIG_USER_ONLY
257 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
258 SPR_NOACCESS, SPR_NOACCESS,
259 &spr_read_generic, &spr_write_iamr,
260 &spr_read_generic, &spr_write_generic,
261 KVM_REG_PPC_IAMR, 0);
262#endif
263}
264#endif
265
266
267static void register_604_sprs(CPUPPCState *env)
268{
269
270 spr_register(env, SPR_PIR, "PIR",
271 SPR_NOACCESS, SPR_NOACCESS,
272 &spr_read_generic, &spr_write_pir,
273 0x00000000);
274
275 spr_register(env, SPR_IABR, "IABR",
276 SPR_NOACCESS, SPR_NOACCESS,
277 &spr_read_generic, &spr_write_generic,
278 0x00000000);
279
280 spr_register_kvm(env, SPR_DABR, "DABR",
281 SPR_NOACCESS, SPR_NOACCESS,
282 &spr_read_generic, &spr_write_generic,
283 KVM_REG_PPC_DABR, 0x00000000);
284
285 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
286 SPR_NOACCESS, SPR_NOACCESS,
287 &spr_read_generic, &spr_write_generic,
288 0x00000000);
289
290 spr_register(env, SPR_7XX_PMC1, "PMC1",
291 SPR_NOACCESS, SPR_NOACCESS,
292 &spr_read_generic, &spr_write_generic,
293 0x00000000);
294
295 spr_register(env, SPR_7XX_PMC2, "PMC2",
296 SPR_NOACCESS, SPR_NOACCESS,
297 &spr_read_generic, &spr_write_generic,
298 0x00000000);
299
300 spr_register(env, SPR_7XX_SIAR, "SIAR",
301 SPR_NOACCESS, SPR_NOACCESS,
302 &spr_read_generic, SPR_NOACCESS,
303 0x00000000);
304
305 spr_register(env, SPR_SDA, "SDA",
306 SPR_NOACCESS, SPR_NOACCESS,
307 &spr_read_generic, SPR_NOACCESS,
308 0x00000000);
309
310 spr_register(env, SPR_EAR, "EAR",
311 SPR_NOACCESS, SPR_NOACCESS,
312 &spr_read_generic, &spr_write_generic,
313 0x00000000);
314
315
316 spr_register(env, SPR_HID0, "HID0",
317 SPR_NOACCESS, SPR_NOACCESS,
318 &spr_read_generic, &spr_write_generic,
319 0x00000000);
320}
321
322static void register_604e_sprs(CPUPPCState *env)
323{
324 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
325 SPR_NOACCESS, SPR_NOACCESS,
326 &spr_read_generic, &spr_write_generic,
327 0x00000000);
328
329 spr_register(env, SPR_7XX_PMC3, "PMC3",
330 SPR_NOACCESS, SPR_NOACCESS,
331 &spr_read_generic, &spr_write_generic,
332 0x00000000);
333
334 spr_register(env, SPR_7XX_PMC4, "PMC4",
335 SPR_NOACCESS, SPR_NOACCESS,
336 &spr_read_generic, &spr_write_generic,
337 0x00000000);
338
339 spr_register(env, SPR_HID1, "HID1",
340 SPR_NOACCESS, SPR_NOACCESS,
341 &spr_read_generic, &spr_write_generic,
342 0x00000000);
343}
344
345
346static void register_603_sprs(CPUPPCState *env)
347{
348
349 spr_register(env, SPR_EAR, "EAR",
350 SPR_NOACCESS, SPR_NOACCESS,
351 &spr_read_generic, &spr_write_generic,
352 0x00000000);
353
354 spr_register(env, SPR_IABR, "IABR",
355 SPR_NOACCESS, SPR_NOACCESS,
356 &spr_read_generic, &spr_write_generic,
357 0x00000000);
358
359 spr_register(env, SPR_HID0, "HID0",
360 SPR_NOACCESS, SPR_NOACCESS,
361 &spr_read_generic, &spr_write_generic,
362 0x00000000);
363
364 spr_register(env, SPR_HID1, "HID1",
365 SPR_NOACCESS, SPR_NOACCESS,
366 &spr_read_generic, &spr_write_generic,
367 0x00000000);
368}
369
370static void register_e300_sprs(CPUPPCState *env)
371{
372
373 spr_register(env, SPR_HID2, "HID2",
374 SPR_NOACCESS, SPR_NOACCESS,
375 &spr_read_generic, &spr_write_generic,
376 0x00000000);
377
378 spr_register(env, SPR_DABR, "DABR",
379 SPR_NOACCESS, SPR_NOACCESS,
380 &spr_read_generic, &spr_write_generic,
381 0x00000000);
382
383 spr_register(env, SPR_DABR2, "DABR2",
384 SPR_NOACCESS, SPR_NOACCESS,
385 &spr_read_generic, &spr_write_generic,
386 0x00000000);
387
388 spr_register(env, SPR_IABR2, "IABR2",
389 SPR_NOACCESS, SPR_NOACCESS,
390 &spr_read_generic, &spr_write_generic,
391 0x00000000);
392
393 spr_register(env, SPR_IBCR, "IBCR",
394 SPR_NOACCESS, SPR_NOACCESS,
395 &spr_read_generic, &spr_write_generic,
396 0x00000000);
397
398 spr_register(env, SPR_DBCR, "DBCR",
399 SPR_NOACCESS, SPR_NOACCESS,
400 &spr_read_generic, &spr_write_generic,
401 0x00000000);
402}
403
404
405static void register_G2_sprs(CPUPPCState *env)
406{
407
408
409 spr_register(env, SPR_MBAR, "MBAR",
410 SPR_NOACCESS, SPR_NOACCESS,
411 &spr_read_generic, &spr_write_generic,
412 0x00000000);
413
414 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
415 SPR_NOACCESS, SPR_NOACCESS,
416 &spr_read_generic, &spr_write_generic,
417 0x00000000);
418 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
419 SPR_NOACCESS, SPR_NOACCESS,
420 &spr_read_generic, &spr_write_generic,
421 0x00000000);
422
423 spr_register(env, SPR_DABR, "DABR",
424 SPR_NOACCESS, SPR_NOACCESS,
425 &spr_read_generic, &spr_write_generic,
426 0x00000000);
427
428 spr_register(env, SPR_DABR2, "DABR2",
429 SPR_NOACCESS, SPR_NOACCESS,
430 &spr_read_generic, &spr_write_generic,
431 0x00000000);
432
433 spr_register(env, SPR_IABR, "IABR",
434 SPR_NOACCESS, SPR_NOACCESS,
435 &spr_read_generic, &spr_write_generic,
436 0x00000000);
437
438 spr_register(env, SPR_IABR2, "IABR2",
439 SPR_NOACCESS, SPR_NOACCESS,
440 &spr_read_generic, &spr_write_generic,
441 0x00000000);
442
443 spr_register(env, SPR_IBCR, "IBCR",
444 SPR_NOACCESS, SPR_NOACCESS,
445 &spr_read_generic, &spr_write_generic,
446 0x00000000);
447
448 spr_register(env, SPR_DBCR, "DBCR",
449 SPR_NOACCESS, SPR_NOACCESS,
450 &spr_read_generic, &spr_write_generic,
451 0x00000000);
452
453
454 spr_register(env, SPR_EAR, "EAR",
455 SPR_NOACCESS, SPR_NOACCESS,
456 &spr_read_generic, &spr_write_generic,
457 0x00000000);
458
459 spr_register(env, SPR_HID0, "HID0",
460 SPR_NOACCESS, SPR_NOACCESS,
461 &spr_read_generic, &spr_write_generic,
462 0x00000000);
463
464 spr_register(env, SPR_HID1, "HID1",
465 SPR_NOACCESS, SPR_NOACCESS,
466 &spr_read_generic, &spr_write_generic,
467 0x00000000);
468
469 spr_register(env, SPR_HID2, "HID2",
470 SPR_NOACCESS, SPR_NOACCESS,
471 &spr_read_generic, &spr_write_generic,
472 0x00000000);
473
474
475 spr_register(env, SPR_SPRG4, "SPRG4",
476 SPR_NOACCESS, SPR_NOACCESS,
477 &spr_read_generic, &spr_write_generic,
478 0x00000000);
479 spr_register(env, SPR_SPRG5, "SPRG5",
480 SPR_NOACCESS, SPR_NOACCESS,
481 &spr_read_generic, &spr_write_generic,
482 0x00000000);
483 spr_register(env, SPR_SPRG6, "SPRG6",
484 SPR_NOACCESS, SPR_NOACCESS,
485 &spr_read_generic, &spr_write_generic,
486 0x00000000);
487 spr_register(env, SPR_SPRG7, "SPRG7",
488 SPR_NOACCESS, SPR_NOACCESS,
489 &spr_read_generic, &spr_write_generic,
490 0x00000000);
491}
492
493static void register_74xx_sprs(CPUPPCState *env)
494{
495
496 spr_register_kvm(env, SPR_DABR, "DABR",
497 SPR_NOACCESS, SPR_NOACCESS,
498 &spr_read_generic, &spr_write_generic,
499 KVM_REG_PPC_DABR, 0x00000000);
500
501 spr_register(env, SPR_IABR, "IABR",
502 SPR_NOACCESS, SPR_NOACCESS,
503 &spr_read_generic, &spr_write_generic,
504 0x00000000);
505
506 spr_register(env, SPR_ICTC, "ICTC",
507 SPR_NOACCESS, SPR_NOACCESS,
508 &spr_read_generic, &spr_write_generic,
509 0x00000000);
510
511 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
512 SPR_NOACCESS, SPR_NOACCESS,
513 &spr_read_generic, &spr_write_generic,
514 0x00000000);
515
516 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
517 SPR_NOACCESS, SPR_NOACCESS,
518 &spr_read_generic, &spr_write_generic,
519 0x00000000);
520
521 spr_register(env, SPR_7XX_PMC1, "PMC1",
522 SPR_NOACCESS, SPR_NOACCESS,
523 &spr_read_generic, &spr_write_generic,
524 0x00000000);
525
526 spr_register(env, SPR_7XX_PMC2, "PMC2",
527 SPR_NOACCESS, SPR_NOACCESS,
528 &spr_read_generic, &spr_write_generic,
529 0x00000000);
530
531 spr_register(env, SPR_7XX_PMC3, "PMC3",
532 SPR_NOACCESS, SPR_NOACCESS,
533 &spr_read_generic, &spr_write_generic,
534 0x00000000);
535
536 spr_register(env, SPR_7XX_PMC4, "PMC4",
537 SPR_NOACCESS, SPR_NOACCESS,
538 &spr_read_generic, &spr_write_generic,
539 0x00000000);
540
541 spr_register(env, SPR_7XX_SIAR, "SIAR",
542 SPR_NOACCESS, SPR_NOACCESS,
543 &spr_read_generic, SPR_NOACCESS,
544 0x00000000);
545
546 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
547 &spr_read_ureg, SPR_NOACCESS,
548 &spr_read_ureg, SPR_NOACCESS,
549 0x00000000);
550
551 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
552 &spr_read_ureg, SPR_NOACCESS,
553 &spr_read_ureg, SPR_NOACCESS,
554 0x00000000);
555
556 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
557 &spr_read_ureg, SPR_NOACCESS,
558 &spr_read_ureg, SPR_NOACCESS,
559 0x00000000);
560
561 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
562 &spr_read_ureg, SPR_NOACCESS,
563 &spr_read_ureg, SPR_NOACCESS,
564 0x00000000);
565
566 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
567 &spr_read_ureg, SPR_NOACCESS,
568 &spr_read_ureg, SPR_NOACCESS,
569 0x00000000);
570
571 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
572 &spr_read_ureg, SPR_NOACCESS,
573 &spr_read_ureg, SPR_NOACCESS,
574 0x00000000);
575
576 spr_register(env, SPR_7XX_USIAR, "USIAR",
577 &spr_read_ureg, SPR_NOACCESS,
578 &spr_read_ureg, SPR_NOACCESS,
579 0x00000000);
580
581 spr_register(env, SPR_EAR, "EAR",
582 SPR_NOACCESS, SPR_NOACCESS,
583 &spr_read_generic, &spr_write_generic,
584 0x00000000);
585
586
587 spr_register(env, SPR_PIR, "PIR",
588 SPR_NOACCESS, SPR_NOACCESS,
589 &spr_read_generic, &spr_write_pir,
590 0x00000000);
591
592 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
593 SPR_NOACCESS, SPR_NOACCESS,
594 &spr_read_generic, &spr_write_generic,
595 0x00000000);
596
597 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
598 &spr_read_ureg, SPR_NOACCESS,
599 &spr_read_ureg, SPR_NOACCESS,
600 0x00000000);
601
602 spr_register(env, SPR_BAMR, "BAMR",
603 SPR_NOACCESS, SPR_NOACCESS,
604 &spr_read_generic, &spr_write_generic,
605 0x00000000);
606
607 spr_register(env, SPR_MSSCR0, "MSSCR0",
608 SPR_NOACCESS, SPR_NOACCESS,
609 &spr_read_generic, &spr_write_generic,
610 0x00000000);
611
612 spr_register(env, SPR_HID0, "HID0",
613 SPR_NOACCESS, SPR_NOACCESS,
614 &spr_read_generic, &spr_write_generic,
615 0x00000000);
616
617 spr_register(env, SPR_HID1, "HID1",
618 SPR_NOACCESS, SPR_NOACCESS,
619 &spr_read_generic, &spr_write_generic,
620 0x00000000);
621
622 spr_register(env, SPR_VRSAVE, "VRSAVE",
623 &spr_read_generic, &spr_write_generic,
624 &spr_read_generic, &spr_write_generic,
625 0x00000000);
626
627 spr_register(env, SPR_L2CR, "L2CR",
628 SPR_NOACCESS, SPR_NOACCESS,
629 &spr_read_generic, spr_access_nop,
630 0x00000000);
631}
632
633static void register_l3_ctrl(CPUPPCState *env)
634{
635
636 spr_register(env, SPR_L3CR, "L3CR",
637 SPR_NOACCESS, SPR_NOACCESS,
638 &spr_read_generic, &spr_write_generic,
639 0x00000000);
640
641 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
642 SPR_NOACCESS, SPR_NOACCESS,
643 &spr_read_generic, &spr_write_generic,
644 0x00000000);
645
646 spr_register(env, SPR_L3PM, "L3PM",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_generic, &spr_write_generic,
649 0x00000000);
650}
651
652
653static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
654{
655 const char *ivor_names[64] = {
656 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
657 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
658 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
659 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
660 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
661 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
662 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
663 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
664 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
665 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
666 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
667 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
668 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
669 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
670 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
671 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
672 };
673#define SPR_BOOKE_IVORxx (-1)
674 int ivor_sprn[64] = {
675 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
676 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
677 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
678 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
679 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
680 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
681 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
682 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
683 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
684 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
685 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
686 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
687 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
688 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
689 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
690 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
691 };
692 int i;
693
694
695 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_generic, &spr_write_generic,
698 0x00000000);
699 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
700 SPR_NOACCESS, SPR_NOACCESS,
701 &spr_read_generic, &spr_write_generic,
702 0x00000000);
703
704 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
705 SPR_NOACCESS, SPR_NOACCESS,
706 &spr_read_generic, &spr_write_generic,
707 0x00000000);
708
709 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_generic, &spr_write_generic,
712 0x00000000);
713
714 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_generic, &spr_write_generic,
717 0x00000000);
718
719 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_generic, &spr_write_generic,
722 0x00000000);
723
724 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_generic, &spr_write_40x_dbcr0,
727 0x00000000);
728
729 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
730 SPR_NOACCESS, SPR_NOACCESS,
731 &spr_read_generic, &spr_write_generic,
732 0x00000000);
733
734 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_generic, &spr_write_generic,
737 0x00000000);
738 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_generic, &spr_write_generic,
741 0x00000000);
742 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
743 SPR_NOACCESS, SPR_NOACCESS,
744 &spr_read_generic, &spr_write_generic,
745 0x00000000);
746
747 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
748 SPR_NOACCESS, SPR_NOACCESS,
749 &spr_read_generic, &spr_write_clear,
750 0x00000000);
751 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_generic, &spr_write_generic,
754 0x00000000);
755 spr_register(env, SPR_BOOKE_ESR, "ESR",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_generic, &spr_write_generic,
758 0x00000000);
759 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_generic, &spr_write_excp_prefix,
762 0x00000000);
763
764 for (i = 0; i < 64; i++) {
765 if (ivor_mask & (1ULL << i)) {
766 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
767 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
768 exit(1);
769 }
770 spr_register(env, ivor_sprn[i], ivor_names[i],
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_generic, &spr_write_excp_vector,
773 0x00000000);
774 }
775 }
776 spr_register(env, SPR_BOOKE_PID, "PID",
777 SPR_NOACCESS, SPR_NOACCESS,
778 &spr_read_generic, &spr_write_booke_pid,
779 0x00000000);
780 spr_register(env, SPR_BOOKE_TCR, "TCR",
781 SPR_NOACCESS, SPR_NOACCESS,
782 &spr_read_generic, &spr_write_booke_tcr,
783 0x00000000);
784 spr_register(env, SPR_BOOKE_TSR, "TSR",
785 SPR_NOACCESS, SPR_NOACCESS,
786 &spr_read_generic, &spr_write_booke_tsr,
787 0x00000000);
788
789 spr_register(env, SPR_DECR, "DECR",
790 SPR_NOACCESS, SPR_NOACCESS,
791 &spr_read_decr, &spr_write_decr,
792 0x00000000);
793 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
794 SPR_NOACCESS, SPR_NOACCESS,
795 SPR_NOACCESS, &spr_write_generic,
796 0x00000000);
797
798 spr_register(env, SPR_USPRG0, "USPRG0",
799 &spr_read_generic, &spr_write_generic,
800 &spr_read_generic, &spr_write_generic,
801 0x00000000);
802 spr_register(env, SPR_SPRG4, "SPRG4",
803 SPR_NOACCESS, SPR_NOACCESS,
804 &spr_read_generic, &spr_write_generic,
805 0x00000000);
806 spr_register(env, SPR_SPRG5, "SPRG5",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_generic, &spr_write_generic,
809 0x00000000);
810 spr_register(env, SPR_SPRG6, "SPRG6",
811 SPR_NOACCESS, SPR_NOACCESS,
812 &spr_read_generic, &spr_write_generic,
813 0x00000000);
814 spr_register(env, SPR_SPRG7, "SPRG7",
815 SPR_NOACCESS, SPR_NOACCESS,
816 &spr_read_generic, &spr_write_generic,
817 0x00000000);
818 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
819 SPR_NOACCESS, SPR_NOACCESS,
820 &spr_read_generic, &spr_write_generic,
821 0x00000000);
822 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
823 SPR_NOACCESS, SPR_NOACCESS,
824 &spr_read_generic, &spr_write_generic,
825 0x00000000);
826}
827
828#if !defined(CONFIG_USER_ONLY)
829static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
830 uint32_t maxsize, uint32_t flags,
831 uint32_t nentries)
832{
833 return (assoc << TLBnCFG_ASSOC_SHIFT) |
834 (minsize << TLBnCFG_MINSIZE_SHIFT) |
835 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
836 flags | nentries;
837}
838#endif
839
840
841static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
842 uint32_t *tlbncfg, uint32_t mmucfg)
843{
844#if !defined(CONFIG_USER_ONLY)
845 const char *mas_names[8] = {
846 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
847 };
848 int mas_sprn[8] = {
849 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
850 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
851 };
852 int i;
853
854
855 for (i = 0; i < 8; i++) {
856 if (mas_mask & (1 << i)) {
857 spr_register(env, mas_sprn[i], mas_names[i],
858 SPR_NOACCESS, SPR_NOACCESS,
859 &spr_read_generic,
860 (i == 2 && (env->insns_flags & PPC_64B))
861 ? &spr_write_generic : &spr_write_generic32,
862 0x00000000);
863 }
864 }
865 if (env->nb_pids > 1) {
866 spr_register(env, SPR_BOOKE_PID1, "PID1",
867 SPR_NOACCESS, SPR_NOACCESS,
868 &spr_read_generic, &spr_write_booke_pid,
869 0x00000000);
870 }
871 if (env->nb_pids > 2) {
872 spr_register(env, SPR_BOOKE_PID2, "PID2",
873 SPR_NOACCESS, SPR_NOACCESS,
874 &spr_read_generic, &spr_write_booke_pid,
875 0x00000000);
876 }
877
878 spr_register(env, SPR_BOOKE_EPLC, "EPLC",
879 SPR_NOACCESS, SPR_NOACCESS,
880 &spr_read_generic, &spr_write_eplc,
881 0x00000000);
882 spr_register(env, SPR_BOOKE_EPSC, "EPSC",
883 SPR_NOACCESS, SPR_NOACCESS,
884 &spr_read_generic, &spr_write_epsc,
885 0x00000000);
886
887 spr_register(env, SPR_MMUCFG, "MMUCFG",
888 SPR_NOACCESS, SPR_NOACCESS,
889 &spr_read_generic, SPR_NOACCESS,
890 mmucfg);
891 switch (env->nb_ways) {
892 case 4:
893 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
894 SPR_NOACCESS, SPR_NOACCESS,
895 &spr_read_generic, SPR_NOACCESS,
896 tlbncfg[3]);
897
898 case 3:
899 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
900 SPR_NOACCESS, SPR_NOACCESS,
901 &spr_read_generic, SPR_NOACCESS,
902 tlbncfg[2]);
903
904 case 2:
905 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
906 SPR_NOACCESS, SPR_NOACCESS,
907 &spr_read_generic, SPR_NOACCESS,
908 tlbncfg[1]);
909
910 case 1:
911 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
912 SPR_NOACCESS, SPR_NOACCESS,
913 &spr_read_generic, SPR_NOACCESS,
914 tlbncfg[0]);
915
916 case 0:
917 default:
918 break;
919 }
920#endif
921}
922
923
924static void register_440_sprs(CPUPPCState *env)
925{
926
927 spr_register(env, SPR_440_DNV0, "DNV0",
928 SPR_NOACCESS, SPR_NOACCESS,
929 &spr_read_generic, &spr_write_generic,
930 0x00000000);
931
932 spr_register(env, SPR_440_DNV1, "DNV1",
933 SPR_NOACCESS, SPR_NOACCESS,
934 &spr_read_generic, &spr_write_generic,
935 0x00000000);
936
937 spr_register(env, SPR_440_DNV2, "DNV2",
938 SPR_NOACCESS, SPR_NOACCESS,
939 &spr_read_generic, &spr_write_generic,
940 0x00000000);
941
942 spr_register(env, SPR_440_DNV3, "DNV3",
943 SPR_NOACCESS, SPR_NOACCESS,
944 &spr_read_generic, &spr_write_generic,
945 0x00000000);
946
947 spr_register(env, SPR_440_DTV0, "DTV0",
948 SPR_NOACCESS, SPR_NOACCESS,
949 &spr_read_generic, &spr_write_generic,
950 0x00000000);
951
952 spr_register(env, SPR_440_DTV1, "DTV1",
953 SPR_NOACCESS, SPR_NOACCESS,
954 &spr_read_generic, &spr_write_generic,
955 0x00000000);
956
957 spr_register(env, SPR_440_DTV2, "DTV2",
958 SPR_NOACCESS, SPR_NOACCESS,
959 &spr_read_generic, &spr_write_generic,
960 0x00000000);
961
962 spr_register(env, SPR_440_DTV3, "DTV3",
963 SPR_NOACCESS, SPR_NOACCESS,
964 &spr_read_generic, &spr_write_generic,
965 0x00000000);
966
967 spr_register(env, SPR_440_DVLIM, "DVLIM",
968 SPR_NOACCESS, SPR_NOACCESS,
969 &spr_read_generic, &spr_write_generic,
970 0x00000000);
971
972 spr_register(env, SPR_440_INV0, "INV0",
973 SPR_NOACCESS, SPR_NOACCESS,
974 &spr_read_generic, &spr_write_generic,
975 0x00000000);
976
977 spr_register(env, SPR_440_INV1, "INV1",
978 SPR_NOACCESS, SPR_NOACCESS,
979 &spr_read_generic, &spr_write_generic,
980 0x00000000);
981
982 spr_register(env, SPR_440_INV2, "INV2",
983 SPR_NOACCESS, SPR_NOACCESS,
984 &spr_read_generic, &spr_write_generic,
985 0x00000000);
986
987 spr_register(env, SPR_440_INV3, "INV3",
988 SPR_NOACCESS, SPR_NOACCESS,
989 &spr_read_generic, &spr_write_generic,
990 0x00000000);
991
992 spr_register(env, SPR_440_ITV0, "ITV0",
993 SPR_NOACCESS, SPR_NOACCESS,
994 &spr_read_generic, &spr_write_generic,
995 0x00000000);
996
997 spr_register(env, SPR_440_ITV1, "ITV1",
998 SPR_NOACCESS, SPR_NOACCESS,
999 &spr_read_generic, &spr_write_generic,
1000 0x00000000);
1001
1002 spr_register(env, SPR_440_ITV2, "ITV2",
1003 SPR_NOACCESS, SPR_NOACCESS,
1004 &spr_read_generic, &spr_write_generic,
1005 0x00000000);
1006
1007 spr_register(env, SPR_440_ITV3, "ITV3",
1008 SPR_NOACCESS, SPR_NOACCESS,
1009 &spr_read_generic, &spr_write_generic,
1010 0x00000000);
1011
1012 spr_register(env, SPR_440_IVLIM, "IVLIM",
1013 SPR_NOACCESS, SPR_NOACCESS,
1014 &spr_read_generic, &spr_write_generic,
1015 0x00000000);
1016
1017 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1018 SPR_NOACCESS, SPR_NOACCESS,
1019 &spr_read_generic, SPR_NOACCESS,
1020 0x00000000);
1021
1022 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1023 SPR_NOACCESS, SPR_NOACCESS,
1024 &spr_read_generic, SPR_NOACCESS,
1025 0x00000000);
1026
1027 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1028 SPR_NOACCESS, SPR_NOACCESS,
1029 &spr_read_generic, SPR_NOACCESS,
1030 0x00000000);
1031
1032 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1033 SPR_NOACCESS, SPR_NOACCESS,
1034 &spr_read_generic, SPR_NOACCESS,
1035 0x00000000);
1036
1037 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1038 SPR_NOACCESS, SPR_NOACCESS,
1039 &spr_read_generic, SPR_NOACCESS,
1040 0x00000000);
1041
1042 spr_register(env, SPR_440_DBDR, "DBDR",
1043 SPR_NOACCESS, SPR_NOACCESS,
1044 &spr_read_generic, &spr_write_generic,
1045 0x00000000);
1046
1047 spr_register(env, SPR_4xx_CCR0, "CCR0",
1048 SPR_NOACCESS, SPR_NOACCESS,
1049 &spr_read_generic, &spr_write_generic,
1050 0x00000000);
1051 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1052 SPR_NOACCESS, SPR_NOACCESS,
1053 &spr_read_generic, SPR_NOACCESS,
1054 0x00000000);
1055
1056 spr_register(env, SPR_440_MMUCR, "MMUCR",
1057 SPR_NOACCESS, SPR_NOACCESS,
1058 &spr_read_generic, &spr_write_generic,
1059 0x00000000);
1060
1061
1062 spr_register(env, SPR_BOOKE_PIR, "PIR",
1063 SPR_NOACCESS, SPR_NOACCESS,
1064 &spr_read_generic, &spr_write_pir,
1065 0x00000000);
1066
1067 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1068 SPR_NOACCESS, SPR_NOACCESS,
1069 &spr_read_generic, &spr_write_generic,
1070 0x00000000);
1071
1072 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1073 SPR_NOACCESS, SPR_NOACCESS,
1074 &spr_read_generic, &spr_write_generic,
1075 0x00000000);
1076
1077 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1078 SPR_NOACCESS, SPR_NOACCESS,
1079 &spr_read_generic, &spr_write_generic,
1080 0x00000000);
1081
1082 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1083 SPR_NOACCESS, SPR_NOACCESS,
1084 &spr_read_generic, &spr_write_generic,
1085 0x00000000);
1086}
1087
1088
1089static void register_40x_sprs(CPUPPCState *env)
1090{
1091
1092
1093 spr_register(env, SPR_40x_DCCR, "DCCR",
1094 SPR_NOACCESS, SPR_NOACCESS,
1095 &spr_read_generic, &spr_write_generic,
1096 0x00000000);
1097
1098 spr_register(env, SPR_40x_ICCR, "ICCR",
1099 SPR_NOACCESS, SPR_NOACCESS,
1100 &spr_read_generic, &spr_write_generic,
1101 0x00000000);
1102
1103 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1104 SPR_NOACCESS, SPR_NOACCESS,
1105 &spr_read_generic, SPR_NOACCESS,
1106 0x00000000);
1107
1108 spr_register(env, SPR_40x_DEAR, "DEAR",
1109 SPR_NOACCESS, SPR_NOACCESS,
1110 &spr_read_generic, &spr_write_generic,
1111 0x00000000);
1112 spr_register(env, SPR_40x_ESR, "ESR",
1113 SPR_NOACCESS, SPR_NOACCESS,
1114 &spr_read_generic, &spr_write_generic,
1115 0x00000000);
1116 spr_register(env, SPR_40x_EVPR, "EVPR",
1117 SPR_NOACCESS, SPR_NOACCESS,
1118 &spr_read_generic, &spr_write_excp_prefix,
1119 0x00000000);
1120 spr_register(env, SPR_40x_SRR2, "SRR2",
1121 &spr_read_generic, &spr_write_generic,
1122 &spr_read_generic, &spr_write_generic,
1123 0x00000000);
1124 spr_register(env, SPR_40x_SRR3, "SRR3",
1125 &spr_read_generic, &spr_write_generic,
1126 &spr_read_generic, &spr_write_generic,
1127 0x00000000);
1128
1129 spr_register(env, SPR_40x_PIT, "PIT",
1130 SPR_NOACCESS, SPR_NOACCESS,
1131 &spr_read_40x_pit, &spr_write_40x_pit,
1132 0x00000000);
1133 spr_register(env, SPR_40x_TCR, "TCR",
1134 SPR_NOACCESS, SPR_NOACCESS,
1135 &spr_read_generic, &spr_write_40x_tcr,
1136 0x00000000);
1137 spr_register(env, SPR_40x_TSR, "TSR",
1138 SPR_NOACCESS, SPR_NOACCESS,
1139 &spr_read_generic, &spr_write_40x_tsr,
1140 0x00000000);
1141}
1142
1143
1144static void register_405_sprs(CPUPPCState *env)
1145{
1146
1147 spr_register(env, SPR_40x_PID, "PID",
1148 SPR_NOACCESS, SPR_NOACCESS,
1149 &spr_read_generic, &spr_write_40x_pid,
1150 0x00000000);
1151 spr_register(env, SPR_4xx_CCR0, "CCR0",
1152 SPR_NOACCESS, SPR_NOACCESS,
1153 &spr_read_generic, &spr_write_generic,
1154 0x00700000);
1155
1156 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1157 SPR_NOACCESS, SPR_NOACCESS,
1158 &spr_read_generic, &spr_write_40x_dbcr0,
1159 0x00000000);
1160
1161 spr_register(env, SPR_405_DBCR1, "DBCR1",
1162 SPR_NOACCESS, SPR_NOACCESS,
1163 &spr_read_generic, &spr_write_generic,
1164 0x00000000);
1165
1166 spr_register(env, SPR_40x_DBSR, "DBSR",
1167 SPR_NOACCESS, SPR_NOACCESS,
1168 &spr_read_generic, &spr_write_clear,
1169
1170 0x00000300);
1171
1172 spr_register(env, SPR_40x_DAC1, "DAC1",
1173 SPR_NOACCESS, SPR_NOACCESS,
1174 &spr_read_generic, &spr_write_generic,
1175 0x00000000);
1176 spr_register(env, SPR_40x_DAC2, "DAC2",
1177 SPR_NOACCESS, SPR_NOACCESS,
1178 &spr_read_generic, &spr_write_generic,
1179 0x00000000);
1180
1181 spr_register(env, SPR_405_DVC1, "DVC1",
1182 SPR_NOACCESS, SPR_NOACCESS,
1183 &spr_read_generic, &spr_write_generic,
1184 0x00000000);
1185
1186 spr_register(env, SPR_405_DVC2, "DVC2",
1187 SPR_NOACCESS, SPR_NOACCESS,
1188 &spr_read_generic, &spr_write_generic,
1189 0x00000000);
1190
1191 spr_register(env, SPR_40x_IAC1, "IAC1",
1192 SPR_NOACCESS, SPR_NOACCESS,
1193 &spr_read_generic, &spr_write_generic,
1194 0x00000000);
1195 spr_register(env, SPR_40x_IAC2, "IAC2",
1196 SPR_NOACCESS, SPR_NOACCESS,
1197 &spr_read_generic, &spr_write_generic,
1198 0x00000000);
1199
1200 spr_register(env, SPR_405_IAC3, "IAC3",
1201 SPR_NOACCESS, SPR_NOACCESS,
1202 &spr_read_generic, &spr_write_generic,
1203 0x00000000);
1204
1205 spr_register(env, SPR_405_IAC4, "IAC4",
1206 SPR_NOACCESS, SPR_NOACCESS,
1207 &spr_read_generic, &spr_write_generic,
1208 0x00000000);
1209
1210 spr_register(env, SPR_405_SLER, "SLER",
1211 SPR_NOACCESS, SPR_NOACCESS,
1212 &spr_read_generic, &spr_write_40x_sler,
1213 0x00000000);
1214 spr_register(env, SPR_40x_ZPR, "ZPR",
1215 SPR_NOACCESS, SPR_NOACCESS,
1216 &spr_read_generic, &spr_write_generic,
1217 0x00000000);
1218
1219 spr_register(env, SPR_405_SU0R, "SU0R",
1220 SPR_NOACCESS, SPR_NOACCESS,
1221 &spr_read_generic, &spr_write_generic,
1222 0x00000000);
1223
1224 spr_register(env, SPR_USPRG0, "USPRG0",
1225 &spr_read_ureg, SPR_NOACCESS,
1226 &spr_read_ureg, SPR_NOACCESS,
1227 0x00000000);
1228 spr_register(env, SPR_SPRG4, "SPRG4",
1229 SPR_NOACCESS, SPR_NOACCESS,
1230 &spr_read_generic, &spr_write_generic,
1231 0x00000000);
1232 spr_register(env, SPR_SPRG5, "SPRG5",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 spr_read_generic, &spr_write_generic,
1235 0x00000000);
1236 spr_register(env, SPR_SPRG6, "SPRG6",
1237 SPR_NOACCESS, SPR_NOACCESS,
1238 spr_read_generic, &spr_write_generic,
1239 0x00000000);
1240 spr_register(env, SPR_SPRG7, "SPRG7",
1241 SPR_NOACCESS, SPR_NOACCESS,
1242 spr_read_generic, &spr_write_generic,
1243 0x00000000);
1244
1245
1246
1247 spr_register(env, SPR_40x_SGR, "SGR",
1248 SPR_NOACCESS, SPR_NOACCESS,
1249 &spr_read_generic, &spr_write_generic,
1250 0xFFFFFFFF);
1251
1252 spr_register(env, SPR_40x_DCWR, "DCWR",
1253 SPR_NOACCESS, SPR_NOACCESS,
1254 &spr_read_generic, &spr_write_generic,
1255 0x00000000);
1256}
1257
1258
1259static void register_5xx_8xx_sprs(CPUPPCState *env)
1260{
1261
1262 spr_register_kvm(env, SPR_DSISR, "DSISR",
1263 SPR_NOACCESS, SPR_NOACCESS,
1264 &spr_read_generic, &spr_write_generic,
1265 KVM_REG_PPC_DSISR, 0x00000000);
1266 spr_register_kvm(env, SPR_DAR, "DAR",
1267 SPR_NOACCESS, SPR_NOACCESS,
1268 &spr_read_generic, &spr_write_generic,
1269 KVM_REG_PPC_DAR, 0x00000000);
1270
1271 spr_register(env, SPR_DECR, "DECR",
1272 SPR_NOACCESS, SPR_NOACCESS,
1273 &spr_read_decr, &spr_write_decr,
1274 0x00000000);
1275
1276 spr_register(env, SPR_MPC_EIE, "EIE",
1277 SPR_NOACCESS, SPR_NOACCESS,
1278 &spr_read_generic, &spr_write_generic,
1279 0x00000000);
1280
1281 spr_register(env, SPR_MPC_EID, "EID",
1282 SPR_NOACCESS, SPR_NOACCESS,
1283 &spr_read_generic, &spr_write_generic,
1284 0x00000000);
1285
1286 spr_register(env, SPR_MPC_NRI, "NRI",
1287 SPR_NOACCESS, SPR_NOACCESS,
1288 &spr_read_generic, &spr_write_generic,
1289 0x00000000);
1290
1291 spr_register(env, SPR_MPC_CMPA, "CMPA",
1292 SPR_NOACCESS, SPR_NOACCESS,
1293 &spr_read_generic, &spr_write_generic,
1294 0x00000000);
1295
1296 spr_register(env, SPR_MPC_CMPB, "CMPB",
1297 SPR_NOACCESS, SPR_NOACCESS,
1298 &spr_read_generic, &spr_write_generic,
1299 0x00000000);
1300
1301 spr_register(env, SPR_MPC_CMPC, "CMPC",
1302 SPR_NOACCESS, SPR_NOACCESS,
1303 &spr_read_generic, &spr_write_generic,
1304 0x00000000);
1305
1306 spr_register(env, SPR_MPC_CMPD, "CMPD",
1307 SPR_NOACCESS, SPR_NOACCESS,
1308 &spr_read_generic, &spr_write_generic,
1309 0x00000000);
1310
1311 spr_register(env, SPR_MPC_ECR, "ECR",
1312 SPR_NOACCESS, SPR_NOACCESS,
1313 &spr_read_generic, &spr_write_generic,
1314 0x00000000);
1315
1316 spr_register(env, SPR_MPC_DER, "DER",
1317 SPR_NOACCESS, SPR_NOACCESS,
1318 &spr_read_generic, &spr_write_generic,
1319 0x00000000);
1320
1321 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
1322 SPR_NOACCESS, SPR_NOACCESS,
1323 &spr_read_generic, &spr_write_generic,
1324 0x00000000);
1325
1326 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
1327 SPR_NOACCESS, SPR_NOACCESS,
1328 &spr_read_generic, &spr_write_generic,
1329 0x00000000);
1330
1331 spr_register(env, SPR_MPC_CMPE, "CMPE",
1332 SPR_NOACCESS, SPR_NOACCESS,
1333 &spr_read_generic, &spr_write_generic,
1334 0x00000000);
1335
1336 spr_register(env, SPR_MPC_CMPF, "CMPF",
1337 SPR_NOACCESS, SPR_NOACCESS,
1338 &spr_read_generic, &spr_write_generic,
1339 0x00000000);
1340
1341 spr_register(env, SPR_MPC_CMPG, "CMPG",
1342 SPR_NOACCESS, SPR_NOACCESS,
1343 &spr_read_generic, &spr_write_generic,
1344 0x00000000);
1345
1346 spr_register(env, SPR_MPC_CMPH, "CMPH",
1347 SPR_NOACCESS, SPR_NOACCESS,
1348 &spr_read_generic, &spr_write_generic,
1349 0x00000000);
1350
1351 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
1352 SPR_NOACCESS, SPR_NOACCESS,
1353 &spr_read_generic, &spr_write_generic,
1354 0x00000000);
1355
1356 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
1357 SPR_NOACCESS, SPR_NOACCESS,
1358 &spr_read_generic, &spr_write_generic,
1359 0x00000000);
1360
1361 spr_register(env, SPR_MPC_BAR, "BAR",
1362 SPR_NOACCESS, SPR_NOACCESS,
1363 &spr_read_generic, &spr_write_generic,
1364 0x00000000);
1365
1366 spr_register(env, SPR_MPC_DPDR, "DPDR",
1367 SPR_NOACCESS, SPR_NOACCESS,
1368 &spr_read_generic, &spr_write_generic,
1369 0x00000000);
1370
1371 spr_register(env, SPR_MPC_IMMR, "IMMR",
1372 SPR_NOACCESS, SPR_NOACCESS,
1373 &spr_read_generic, &spr_write_generic,
1374 0x00000000);
1375}
1376
1377static void register_5xx_sprs(CPUPPCState *env)
1378{
1379 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
1380 SPR_NOACCESS, SPR_NOACCESS,
1381 &spr_read_generic, &spr_write_generic,
1382 0x00000000);
1383
1384 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
1385 SPR_NOACCESS, SPR_NOACCESS,
1386 &spr_read_generic, &spr_write_generic,
1387 0x00000000);
1388
1389 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
1390 SPR_NOACCESS, SPR_NOACCESS,
1391 &spr_read_generic, &spr_write_generic,
1392 0x00000000);
1393
1394 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
1395 SPR_NOACCESS, SPR_NOACCESS,
1396 &spr_read_generic, &spr_write_generic,
1397 0x00000000);
1398
1399 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
1400 SPR_NOACCESS, SPR_NOACCESS,
1401 &spr_read_generic, &spr_write_generic,
1402 0x00000000);
1403
1404 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
1405 SPR_NOACCESS, SPR_NOACCESS,
1406 &spr_read_generic, &spr_write_generic,
1407 0x00000000);
1408
1409 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
1410 SPR_NOACCESS, SPR_NOACCESS,
1411 &spr_read_generic, &spr_write_generic,
1412 0x00000000);
1413
1414 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
1415 SPR_NOACCESS, SPR_NOACCESS,
1416 &spr_read_generic, &spr_write_generic,
1417 0x00000000);
1418
1419 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
1420 SPR_NOACCESS, SPR_NOACCESS,
1421 &spr_read_generic, &spr_write_generic,
1422 0x00000000);
1423
1424 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
1425 SPR_NOACCESS, SPR_NOACCESS,
1426 &spr_read_generic, &spr_write_generic,
1427 0x00000000);
1428
1429 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
1430 SPR_NOACCESS, SPR_NOACCESS,
1431 &spr_read_generic, &spr_write_generic,
1432 0x00000000);
1433
1434 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
1435 SPR_NOACCESS, SPR_NOACCESS,
1436 &spr_read_generic, &spr_write_generic,
1437 0x00000000);
1438
1439 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
1440 SPR_NOACCESS, SPR_NOACCESS,
1441 &spr_read_generic, &spr_write_generic,
1442 0x00000000);
1443
1444 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
1445 SPR_NOACCESS, SPR_NOACCESS,
1446 &spr_read_generic, &spr_write_generic,
1447 0x00000000);
1448
1449 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
1450 SPR_NOACCESS, SPR_NOACCESS,
1451 &spr_read_generic, &spr_write_generic,
1452 0x00000000);
1453
1454 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
1455 SPR_NOACCESS, SPR_NOACCESS,
1456 &spr_read_generic, &spr_write_generic,
1457 0x00000000);
1458
1459 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
1460 SPR_NOACCESS, SPR_NOACCESS,
1461 &spr_read_generic, &spr_write_generic,
1462 0x00000000);
1463
1464 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
1465 SPR_NOACCESS, SPR_NOACCESS,
1466 &spr_read_generic, &spr_write_generic,
1467 0x00000000);
1468
1469 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
1470 SPR_NOACCESS, SPR_NOACCESS,
1471 &spr_read_generic, &spr_write_generic,
1472 0x00000000);
1473
1474 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
1475 SPR_NOACCESS, SPR_NOACCESS,
1476 &spr_read_generic, &spr_write_generic,
1477 0x00000000);
1478
1479 spr_register(env, SPR_RCPU_FPECR, "FPECR",
1480 SPR_NOACCESS, SPR_NOACCESS,
1481 &spr_read_generic, &spr_write_generic,
1482 0x00000000);
1483}
1484
1485static void register_8xx_sprs(CPUPPCState *env)
1486{
1487
1488 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
1489 SPR_NOACCESS, SPR_NOACCESS,
1490 &spr_read_generic, &spr_write_generic,
1491 0x00000000);
1492
1493 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
1494 SPR_NOACCESS, SPR_NOACCESS,
1495 &spr_read_generic, &spr_write_generic,
1496 0x00000000);
1497
1498 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
1499 SPR_NOACCESS, SPR_NOACCESS,
1500 &spr_read_generic, &spr_write_generic,
1501 0x00000000);
1502
1503 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
1504 SPR_NOACCESS, SPR_NOACCESS,
1505 &spr_read_generic, &spr_write_generic,
1506 0x00000000);
1507
1508 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
1509 SPR_NOACCESS, SPR_NOACCESS,
1510 &spr_read_generic, &spr_write_generic,
1511 0x00000000);
1512
1513 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
1514 SPR_NOACCESS, SPR_NOACCESS,
1515 &spr_read_generic, &spr_write_generic,
1516 0x00000000);
1517
1518 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
1519 SPR_NOACCESS, SPR_NOACCESS,
1520 &spr_read_generic, &spr_write_generic,
1521 0x00000000);
1522
1523 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
1524 SPR_NOACCESS, SPR_NOACCESS,
1525 &spr_read_generic, &spr_write_generic,
1526 0x00000000);
1527
1528 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
1529 SPR_NOACCESS, SPR_NOACCESS,
1530 &spr_read_generic, &spr_write_generic,
1531 0x00000000);
1532
1533 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
1534 SPR_NOACCESS, SPR_NOACCESS,
1535 &spr_read_generic, &spr_write_generic,
1536 0x00000000);
1537
1538 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
1539 SPR_NOACCESS, SPR_NOACCESS,
1540 &spr_read_generic, &spr_write_generic,
1541 0x00000000);
1542
1543 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
1544 SPR_NOACCESS, SPR_NOACCESS,
1545 &spr_read_generic, &spr_write_generic,
1546 0x00000000);
1547
1548 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, &spr_write_generic,
1551 0x00000000);
1552
1553 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
1554 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, &spr_write_generic,
1556 0x00000000);
1557
1558 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
1559 SPR_NOACCESS, SPR_NOACCESS,
1560 &spr_read_generic, &spr_write_generic,
1561 0x00000000);
1562
1563 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
1564 SPR_NOACCESS, SPR_NOACCESS,
1565 &spr_read_generic, &spr_write_generic,
1566 0x00000000);
1567
1568 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
1569 SPR_NOACCESS, SPR_NOACCESS,
1570 &spr_read_generic, &spr_write_generic,
1571 0x00000000);
1572
1573 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
1574 SPR_NOACCESS, SPR_NOACCESS,
1575 &spr_read_generic, &spr_write_generic,
1576 0x00000000);
1577
1578 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
1579 SPR_NOACCESS, SPR_NOACCESS,
1580 &spr_read_generic, &spr_write_generic,
1581 0x00000000);
1582
1583 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
1584 SPR_NOACCESS, SPR_NOACCESS,
1585 &spr_read_generic, &spr_write_generic,
1586 0x00000000);
1587
1588 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
1589 SPR_NOACCESS, SPR_NOACCESS,
1590 &spr_read_generic, &spr_write_generic,
1591 0x00000000);
1592
1593 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
1594 SPR_NOACCESS, SPR_NOACCESS,
1595 &spr_read_generic, &spr_write_generic,
1596 0x00000000);
1597
1598 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
1599 SPR_NOACCESS, SPR_NOACCESS,
1600 &spr_read_generic, &spr_write_generic,
1601 0x00000000);
1602
1603 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
1604 SPR_NOACCESS, SPR_NOACCESS,
1605 &spr_read_generic, &spr_write_generic,
1606 0x00000000);
1607
1608 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
1609 SPR_NOACCESS, SPR_NOACCESS,
1610 &spr_read_generic, &spr_write_generic,
1611 0x00000000);
1612}
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644static void init_excp_4xx_softmmu(CPUPPCState *env)
1645{
1646#if !defined(CONFIG_USER_ONLY)
1647 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
1648 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1649 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1650 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1651 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1652 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1653 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1654 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1655 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
1656 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
1657 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
1658 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
1659 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
1660 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
1661 env->ivor_mask = 0x0000FFF0UL;
1662 env->ivpr_mask = 0xFFFF0000UL;
1663
1664 env->hreset_vector = 0xFFFFFFFCUL;
1665#endif
1666}
1667
1668static void init_excp_MPC5xx(CPUPPCState *env)
1669{
1670#if !defined(CONFIG_USER_ONLY)
1671 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1672 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1673 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1674 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1675 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1676 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1677 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1678 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1679 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1680 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1681 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1682 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1683 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1684 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1685 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1686 env->ivor_mask = 0x0000FFF0UL;
1687 env->ivpr_mask = 0xFFFF0000UL;
1688
1689 env->hreset_vector = 0x00000100UL;
1690#endif
1691}
1692
1693static void init_excp_MPC8xx(CPUPPCState *env)
1694{
1695#if !defined(CONFIG_USER_ONLY)
1696 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1697 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1698 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1699 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1700 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1701 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1702 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1703 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1704 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1705 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1706 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1707 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1708 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1709 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
1710 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
1711 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
1712 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
1713 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1714 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1715 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1716 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1717 env->ivor_mask = 0x0000FFF0UL;
1718 env->ivpr_mask = 0xFFFF0000UL;
1719
1720 env->hreset_vector = 0x00000100UL;
1721#endif
1722}
1723
1724static void init_excp_G2(CPUPPCState *env)
1725{
1726#if !defined(CONFIG_USER_ONLY)
1727 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1728 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1729 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1730 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1731 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1732 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1733 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1734 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1735 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1736 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
1737 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1738 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1739 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1740 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1741 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1742 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1743 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1744
1745 env->hreset_vector = 0x00000100UL;
1746#endif
1747}
1748
1749static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
1750{
1751#if !defined(CONFIG_USER_ONLY)
1752 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
1753 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1754 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1755 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1756 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1757 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1758 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1759 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1760 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1761 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1762 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1763 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1764 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1765 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1766 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1767 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1768 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
1769
1770
1771
1772
1773
1774 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
1775 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
1776
1777 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
1778 env->ivor_mask = 0x0000FFF7UL;
1779 env->ivpr_mask = ivpr_mask;
1780
1781 env->hreset_vector = 0xFFFFFFFCUL;
1782#endif
1783}
1784
1785static void init_excp_BookE(CPUPPCState *env)
1786{
1787#if !defined(CONFIG_USER_ONLY)
1788 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1789 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1790 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1791 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1792 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1793 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1794 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1795 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1796 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1797 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1798 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1799 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1800 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1801 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1802 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1803 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
1804 env->ivor_mask = 0x0000FFF0UL;
1805 env->ivpr_mask = 0xFFFF0000UL;
1806
1807 env->hreset_vector = 0xFFFFFFFCUL;
1808#endif
1809}
1810
1811static void init_excp_603(CPUPPCState *env)
1812{
1813#if !defined(CONFIG_USER_ONLY)
1814 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1815 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1816 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1817 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1818 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1819 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1820 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1821 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1822 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1823 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1824 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1825 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1826 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1827 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1828 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1829 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1830
1831 env->hreset_vector = 0x00000100UL;
1832#endif
1833}
1834
1835static void init_excp_604(CPUPPCState *env)
1836{
1837#if !defined(CONFIG_USER_ONLY)
1838 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1839 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1840 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1841 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1842 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1843 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1844 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1845 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1846 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1847 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1848 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1849 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1850 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1851 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1852
1853 env->hreset_vector = 0x00000100UL;
1854#endif
1855}
1856
1857static void init_excp_7x0(CPUPPCState *env)
1858{
1859#if !defined(CONFIG_USER_ONLY)
1860 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1861 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1862 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1863 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1864 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1865 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1866 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1867 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1868 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1869 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1870 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1871 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1872 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1873 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1874 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1875
1876 env->hreset_vector = 0x00000100UL;
1877#endif
1878}
1879
1880static void init_excp_750cl(CPUPPCState *env)
1881{
1882#if !defined(CONFIG_USER_ONLY)
1883 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1884 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1885 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1886 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1887 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1888 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1889 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1890 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1891 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1892 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1893 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1894 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1895 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1896 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1897
1898 env->hreset_vector = 0x00000100UL;
1899#endif
1900}
1901
1902static void init_excp_750cx(CPUPPCState *env)
1903{
1904#if !defined(CONFIG_USER_ONLY)
1905 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1906 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1907 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1908 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1909 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1910 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1911 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1912 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1913 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1914 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1915 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1916 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1917 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1918 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1919
1920 env->hreset_vector = 0x00000100UL;
1921#endif
1922}
1923
1924
1925static void init_excp_7x5(CPUPPCState *env)
1926{
1927#if !defined(CONFIG_USER_ONLY)
1928 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1929 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1930 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1931 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1932 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1933 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1934 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1935 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1936 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1937 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1938 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1939 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1940 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1941 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1942 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1943 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1944 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1945 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1946
1947 env->hreset_vector = 0x00000100UL;
1948#endif
1949}
1950
1951static void init_excp_7400(CPUPPCState *env)
1952{
1953#if !defined(CONFIG_USER_ONLY)
1954 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1955 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1956 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1957 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1958 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1959 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1960 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1961 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1962 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1963 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1964 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1965 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1966 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
1967 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1968 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1969 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
1970 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1971
1972 env->hreset_vector = 0x00000100UL;
1973#endif
1974}
1975
1976static void init_excp_7450(CPUPPCState *env)
1977{
1978#if !defined(CONFIG_USER_ONLY)
1979 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1980 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1981 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1982 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1983 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1984 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1985 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1986 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1987 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1988 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1989 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1990 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1991 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
1992 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1993 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1994 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
1995
1996 env->hreset_vector = 0x00000100UL;
1997#endif
1998}
1999
2000#if defined(TARGET_PPC64)
2001static void init_excp_970(CPUPPCState *env)
2002{
2003#if !defined(CONFIG_USER_ONLY)
2004 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2005 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2006 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2007 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2008 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2009 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2010 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2011 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2012 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2013 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2014 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2015 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2016 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2017 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2018 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2019 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2020 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2021 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2022 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2023 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2024
2025 env->hreset_vector = 0x0000000000000100ULL;
2026#endif
2027}
2028
2029static void init_excp_POWER7(CPUPPCState *env)
2030{
2031#if !defined(CONFIG_USER_ONLY)
2032 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2033 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2034 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2035 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2036 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2037 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2038 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2039 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2040 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2041 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2042 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2043 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2044 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2045 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2046 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
2047 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
2048 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
2049 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
2050 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2051 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2052 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
2053
2054 env->hreset_vector = 0x0000000000000100ULL;
2055#endif
2056}
2057
2058static void init_excp_POWER8(CPUPPCState *env)
2059{
2060 init_excp_POWER7(env);
2061
2062#if !defined(CONFIG_USER_ONLY)
2063 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
2064 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
2065 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
2066 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
2067
2068
2069 env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0;
2070 env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0;
2071#endif
2072}
2073
2074static void init_excp_POWER9(CPUPPCState *env)
2075{
2076 init_excp_POWER8(env);
2077
2078#if !defined(CONFIG_USER_ONLY)
2079 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
2080 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000;
2081#endif
2082}
2083
2084static void init_excp_POWER10(CPUPPCState *env)
2085{
2086 init_excp_POWER9(env);
2087}
2088
2089#endif
2090
2091static int check_pow_hid0(CPUPPCState *env)
2092{
2093 if (env->spr[SPR_HID0] & 0x00E00000) {
2094 return 1;
2095 }
2096
2097 return 0;
2098}
2099
2100static int check_pow_hid0_74xx(CPUPPCState *env)
2101{
2102 if (env->spr[SPR_HID0] & 0x00600000) {
2103 return 1;
2104 }
2105
2106 return 0;
2107}
2108
2109static void init_proc_405(CPUPPCState *env)
2110{
2111 register_40x_sprs(env);
2112 register_405_sprs(env);
2113 register_usprgh_sprs(env);
2114
2115
2116#if !defined(CONFIG_USER_ONLY)
2117 env->nb_tlb = 64;
2118 env->nb_ways = 1;
2119 env->id_tlbs = 0;
2120 env->tlb_type = TLB_EMB;
2121#endif
2122 init_excp_4xx_softmmu(env);
2123 env->dcache_line_size = 32;
2124 env->icache_line_size = 32;
2125
2126 ppc40x_irq_init(env_archcpu(env));
2127
2128 SET_FIT_PERIOD(8, 12, 16, 20);
2129 SET_WDT_PERIOD(16, 20, 24, 28);
2130}
2131
2132POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
2133{
2134 DeviceClass *dc = DEVICE_CLASS(oc);
2135 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2136
2137 dc->desc = "PowerPC 405";
2138 pcc->init_proc = init_proc_405;
2139 pcc->check_pow = check_pow_nocheck;
2140 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2141 PPC_DCR | PPC_WRTEE |
2142 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2143 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2144 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2145 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2146 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
2147 pcc->msr_mask = (1ull << MSR_WE) |
2148 (1ull << MSR_CE) |
2149 (1ull << MSR_EE) |
2150 (1ull << MSR_PR) |
2151 (1ull << MSR_FP) |
2152 (1ull << MSR_ME) |
2153 (1ull << MSR_DWE) |
2154 (1ull << MSR_DE) |
2155 (1ull << MSR_IR) |
2156 (1ull << MSR_DR);
2157 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
2158 pcc->excp_model = POWERPC_EXCP_40x;
2159 pcc->bus_model = PPC_FLAGS_INPUT_405;
2160 pcc->bfd_mach = bfd_mach_ppc_403;
2161 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2162 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2163}
2164
2165static void init_proc_440EP(CPUPPCState *env)
2166{
2167 register_BookE_sprs(env, 0x000000000000FFFFULL);
2168 register_440_sprs(env);
2169 register_usprgh_sprs(env);
2170
2171 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2172 SPR_NOACCESS, SPR_NOACCESS,
2173 &spr_read_generic, &spr_write_generic,
2174 0x00000000);
2175 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2176 SPR_NOACCESS, SPR_NOACCESS,
2177 &spr_read_generic, &spr_write_generic,
2178 0x00000000);
2179 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2180 SPR_NOACCESS, SPR_NOACCESS,
2181 &spr_read_generic, &spr_write_generic,
2182 0x00000000);
2183
2184 spr_register(env, SPR_440_CCR1, "CCR1",
2185 SPR_NOACCESS, SPR_NOACCESS,
2186 &spr_read_generic, &spr_write_generic,
2187 0x00000000);
2188
2189#if !defined(CONFIG_USER_ONLY)
2190 env->nb_tlb = 64;
2191 env->nb_ways = 1;
2192 env->id_tlbs = 0;
2193 env->tlb_type = TLB_EMB;
2194#endif
2195 init_excp_BookE(env);
2196 env->dcache_line_size = 32;
2197 env->icache_line_size = 32;
2198 ppc40x_irq_init(env_archcpu(env));
2199
2200 SET_FIT_PERIOD(12, 16, 20, 24);
2201 SET_WDT_PERIOD(20, 24, 28, 32);
2202}
2203
2204POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
2205{
2206 DeviceClass *dc = DEVICE_CLASS(oc);
2207 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2208
2209 dc->desc = "PowerPC 440 EP";
2210 pcc->init_proc = init_proc_440EP;
2211 pcc->check_pow = check_pow_nocheck;
2212 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2213 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2214 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2215 PPC_FLOAT_STFIWX |
2216 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2217 PPC_CACHE | PPC_CACHE_ICBI |
2218 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2219 PPC_MEM_TLBSYNC | PPC_MFTB |
2220 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2221 PPC_440_SPEC;
2222 pcc->msr_mask = (1ull << MSR_POW) |
2223 (1ull << MSR_CE) |
2224 (1ull << MSR_EE) |
2225 (1ull << MSR_PR) |
2226 (1ull << MSR_FP) |
2227 (1ull << MSR_ME) |
2228 (1ull << MSR_FE0) |
2229 (1ull << MSR_DWE) |
2230 (1ull << MSR_DE) |
2231 (1ull << MSR_FE1) |
2232 (1ull << MSR_IR) |
2233 (1ull << MSR_DR);
2234 pcc->mmu_model = POWERPC_MMU_BOOKE;
2235 pcc->excp_model = POWERPC_EXCP_BOOKE;
2236 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2237 pcc->bfd_mach = bfd_mach_ppc_403;
2238 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2239 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2240}
2241
2242POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
2243{
2244 DeviceClass *dc = DEVICE_CLASS(oc);
2245 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2246
2247 dc->desc = "PowerPC 460 EX";
2248 pcc->init_proc = init_proc_440EP;
2249 pcc->check_pow = check_pow_nocheck;
2250 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2251 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2252 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2253 PPC_FLOAT_STFIWX |
2254 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
2255 PPC_CACHE | PPC_CACHE_ICBI |
2256 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2257 PPC_MEM_TLBSYNC | PPC_MFTB |
2258 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2259 PPC_440_SPEC;
2260 pcc->msr_mask = (1ull << MSR_POW) |
2261 (1ull << MSR_CE) |
2262 (1ull << MSR_EE) |
2263 (1ull << MSR_PR) |
2264 (1ull << MSR_FP) |
2265 (1ull << MSR_ME) |
2266 (1ull << MSR_FE0) |
2267 (1ull << MSR_DWE) |
2268 (1ull << MSR_DE) |
2269 (1ull << MSR_FE1) |
2270 (1ull << MSR_IR) |
2271 (1ull << MSR_DR);
2272 pcc->mmu_model = POWERPC_MMU_BOOKE;
2273 pcc->excp_model = POWERPC_EXCP_BOOKE;
2274 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2275 pcc->bfd_mach = bfd_mach_ppc_403;
2276 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2277 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2278}
2279
2280static void init_proc_440GP(CPUPPCState *env)
2281{
2282 register_BookE_sprs(env, 0x000000000000FFFFULL);
2283 register_440_sprs(env);
2284 register_usprgh_sprs(env);
2285
2286
2287#if !defined(CONFIG_USER_ONLY)
2288 env->nb_tlb = 64;
2289 env->nb_ways = 1;
2290 env->id_tlbs = 0;
2291 env->tlb_type = TLB_EMB;
2292#endif
2293 init_excp_BookE(env);
2294 env->dcache_line_size = 32;
2295 env->icache_line_size = 32;
2296
2297
2298 SET_FIT_PERIOD(12, 16, 20, 24);
2299 SET_WDT_PERIOD(20, 24, 28, 32);
2300}
2301
2302POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
2303{
2304 DeviceClass *dc = DEVICE_CLASS(oc);
2305 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2306
2307 dc->desc = "PowerPC 440 GP";
2308 pcc->init_proc = init_proc_440GP;
2309 pcc->check_pow = check_pow_nocheck;
2310 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2311 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
2312 PPC_CACHE | PPC_CACHE_ICBI |
2313 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2314 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
2315 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2316 PPC_440_SPEC;
2317 pcc->msr_mask = (1ull << MSR_POW) |
2318 (1ull << MSR_CE) |
2319 (1ull << MSR_EE) |
2320 (1ull << MSR_PR) |
2321 (1ull << MSR_FP) |
2322 (1ull << MSR_ME) |
2323 (1ull << MSR_FE0) |
2324 (1ull << MSR_DWE) |
2325 (1ull << MSR_DE) |
2326 (1ull << MSR_FE1) |
2327 (1ull << MSR_IR) |
2328 (1ull << MSR_DR);
2329 pcc->mmu_model = POWERPC_MMU_BOOKE;
2330 pcc->excp_model = POWERPC_EXCP_BOOKE;
2331 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2332 pcc->bfd_mach = bfd_mach_ppc_403;
2333 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2334 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2335}
2336
2337static void init_proc_440x5(CPUPPCState *env)
2338{
2339 register_BookE_sprs(env, 0x000000000000FFFFULL);
2340 register_440_sprs(env);
2341 register_usprgh_sprs(env);
2342
2343 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2344 SPR_NOACCESS, SPR_NOACCESS,
2345 &spr_read_generic, &spr_write_generic,
2346 0x00000000);
2347 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2348 SPR_NOACCESS, SPR_NOACCESS,
2349 &spr_read_generic, &spr_write_generic,
2350 0x00000000);
2351 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2352 SPR_NOACCESS, SPR_NOACCESS,
2353 &spr_read_generic, &spr_write_generic,
2354 0x00000000);
2355
2356 spr_register(env, SPR_440_CCR1, "CCR1",
2357 SPR_NOACCESS, SPR_NOACCESS,
2358 &spr_read_generic, &spr_write_generic,
2359 0x00000000);
2360
2361#if !defined(CONFIG_USER_ONLY)
2362 env->nb_tlb = 64;
2363 env->nb_ways = 1;
2364 env->id_tlbs = 0;
2365 env->tlb_type = TLB_EMB;
2366#endif
2367 init_excp_BookE(env);
2368 env->dcache_line_size = 32;
2369 env->icache_line_size = 32;
2370 ppc40x_irq_init(env_archcpu(env));
2371
2372 SET_FIT_PERIOD(12, 16, 20, 24);
2373 SET_WDT_PERIOD(20, 24, 28, 32);
2374}
2375
2376POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
2377{
2378 DeviceClass *dc = DEVICE_CLASS(oc);
2379 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2380
2381 dc->desc = "PowerPC 440x5";
2382 pcc->init_proc = init_proc_440x5;
2383 pcc->check_pow = check_pow_nocheck;
2384 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2385 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2386 PPC_CACHE | PPC_CACHE_ICBI |
2387 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2388 PPC_MEM_TLBSYNC | PPC_MFTB |
2389 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2390 PPC_440_SPEC;
2391 pcc->msr_mask = (1ull << MSR_POW) |
2392 (1ull << MSR_CE) |
2393 (1ull << MSR_EE) |
2394 (1ull << MSR_PR) |
2395 (1ull << MSR_FP) |
2396 (1ull << MSR_ME) |
2397 (1ull << MSR_FE0) |
2398 (1ull << MSR_DWE) |
2399 (1ull << MSR_DE) |
2400 (1ull << MSR_FE1) |
2401 (1ull << MSR_IR) |
2402 (1ull << MSR_DR);
2403 pcc->mmu_model = POWERPC_MMU_BOOKE;
2404 pcc->excp_model = POWERPC_EXCP_BOOKE;
2405 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2406 pcc->bfd_mach = bfd_mach_ppc_403;
2407 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2408 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2409}
2410
2411POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
2412{
2413 DeviceClass *dc = DEVICE_CLASS(oc);
2414 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2415
2416 dc->desc = "PowerPC 440x5 with double precision FPU";
2417 pcc->init_proc = init_proc_440x5;
2418 pcc->check_pow = check_pow_nocheck;
2419 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2420 PPC_FLOAT | PPC_FLOAT_FSQRT |
2421 PPC_FLOAT_STFIWX |
2422 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2423 PPC_CACHE | PPC_CACHE_ICBI |
2424 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2425 PPC_MEM_TLBSYNC | PPC_MFTB |
2426 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2427 PPC_440_SPEC;
2428 pcc->insns_flags2 = PPC2_FP_CVT_S64;
2429 pcc->msr_mask = (1ull << MSR_POW) |
2430 (1ull << MSR_CE) |
2431 (1ull << MSR_EE) |
2432 (1ull << MSR_PR) |
2433 (1ull << MSR_FP) |
2434 (1ull << MSR_ME) |
2435 (1ull << MSR_FE0) |
2436 (1ull << MSR_DWE) |
2437 (1ull << MSR_DE) |
2438 (1ull << MSR_FE1) |
2439 (1ull << MSR_IR) |
2440 (1ull << MSR_DR);
2441 pcc->mmu_model = POWERPC_MMU_BOOKE;
2442 pcc->excp_model = POWERPC_EXCP_BOOKE;
2443 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2444 pcc->bfd_mach = bfd_mach_ppc_403;
2445 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2446 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2447}
2448
2449static void init_proc_MPC5xx(CPUPPCState *env)
2450{
2451 register_5xx_8xx_sprs(env);
2452 register_5xx_sprs(env);
2453 init_excp_MPC5xx(env);
2454 env->dcache_line_size = 32;
2455 env->icache_line_size = 32;
2456
2457}
2458
2459POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
2460{
2461 DeviceClass *dc = DEVICE_CLASS(oc);
2462 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2463
2464 dc->desc = "Freescale 5xx cores (aka RCPU)";
2465 pcc->init_proc = init_proc_MPC5xx;
2466 pcc->check_pow = check_pow_none;
2467 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2468 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2469 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
2470 PPC_MFTB;
2471 pcc->msr_mask = (1ull << MSR_ILE) |
2472 (1ull << MSR_EE) |
2473 (1ull << MSR_PR) |
2474 (1ull << MSR_FP) |
2475 (1ull << MSR_ME) |
2476 (1ull << MSR_FE0) |
2477 (1ull << MSR_SE) |
2478 (1ull << MSR_DE) |
2479 (1ull << MSR_FE1) |
2480 (1ull << MSR_EP) |
2481 (1ull << MSR_RI) |
2482 (1ull << MSR_LE);
2483 pcc->mmu_model = POWERPC_MMU_REAL;
2484 pcc->excp_model = POWERPC_EXCP_6xx;
2485 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2486 pcc->bfd_mach = bfd_mach_ppc_505;
2487 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2488 POWERPC_FLAG_BUS_CLK;
2489}
2490
2491static void init_proc_MPC8xx(CPUPPCState *env)
2492{
2493 register_5xx_8xx_sprs(env);
2494 register_8xx_sprs(env);
2495 init_excp_MPC8xx(env);
2496 env->dcache_line_size = 32;
2497 env->icache_line_size = 32;
2498
2499}
2500
2501POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
2502{
2503 DeviceClass *dc = DEVICE_CLASS(oc);
2504 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2505
2506 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
2507 pcc->init_proc = init_proc_MPC8xx;
2508 pcc->check_pow = check_pow_none;
2509 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2510 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2511 PPC_CACHE_ICBI | PPC_MFTB;
2512 pcc->msr_mask = (1ull << MSR_ILE) |
2513 (1ull << MSR_EE) |
2514 (1ull << MSR_PR) |
2515 (1ull << MSR_FP) |
2516 (1ull << MSR_ME) |
2517 (1ull << MSR_SE) |
2518 (1ull << MSR_DE) |
2519 (1ull << MSR_EP) |
2520 (1ull << MSR_IR) |
2521 (1ull << MSR_DR) |
2522 (1ull << MSR_RI) |
2523 (1ull << MSR_LE);
2524 pcc->mmu_model = POWERPC_MMU_MPC8xx;
2525 pcc->excp_model = POWERPC_EXCP_6xx;
2526 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2527 pcc->bfd_mach = bfd_mach_ppc_860;
2528 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2529 POWERPC_FLAG_BUS_CLK;
2530}
2531
2532
2533
2534static void init_proc_G2(CPUPPCState *env)
2535{
2536 register_non_embedded_sprs(env);
2537 register_sdr1_sprs(env);
2538 register_G2_sprs(env);
2539
2540
2541 register_low_BATs(env);
2542 register_high_BATs(env);
2543 register_6xx_7xx_soft_tlb(env, 64, 2);
2544 init_excp_G2(env);
2545 env->dcache_line_size = 32;
2546 env->icache_line_size = 32;
2547
2548 ppc6xx_irq_init(env_archcpu(env));
2549}
2550
2551POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
2552{
2553 DeviceClass *dc = DEVICE_CLASS(oc);
2554 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2555
2556 dc->desc = "PowerPC G2";
2557 pcc->init_proc = init_proc_G2;
2558 pcc->check_pow = check_pow_hid0;
2559 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2560 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2561 PPC_FLOAT_STFIWX |
2562 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2563 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2564 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2565 PPC_SEGMENT | PPC_EXTERN;
2566 pcc->msr_mask = (1ull << MSR_POW) |
2567 (1ull << MSR_TGPR) |
2568 (1ull << MSR_EE) |
2569 (1ull << MSR_PR) |
2570 (1ull << MSR_FP) |
2571 (1ull << MSR_ME) |
2572 (1ull << MSR_FE0) |
2573 (1ull << MSR_SE) |
2574 (1ull << MSR_DE) |
2575 (1ull << MSR_FE1) |
2576 (1ull << MSR_AL) |
2577 (1ull << MSR_EP) |
2578 (1ull << MSR_IR) |
2579 (1ull << MSR_DR) |
2580 (1ull << MSR_RI);
2581 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
2582 pcc->excp_model = POWERPC_EXCP_6xx;
2583 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2584 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2585 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2586 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
2587}
2588
2589POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
2590{
2591 DeviceClass *dc = DEVICE_CLASS(oc);
2592 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2593
2594 dc->desc = "PowerPC G2LE";
2595 pcc->init_proc = init_proc_G2;
2596 pcc->check_pow = check_pow_hid0;
2597 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2598 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2599 PPC_FLOAT_STFIWX |
2600 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2601 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2602 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2603 PPC_SEGMENT | PPC_EXTERN;
2604 pcc->msr_mask = (1ull << MSR_POW) |
2605 (1ull << MSR_TGPR) |
2606 (1ull << MSR_ILE) |
2607 (1ull << MSR_EE) |
2608 (1ull << MSR_PR) |
2609 (1ull << MSR_FP) |
2610 (1ull << MSR_ME) |
2611 (1ull << MSR_FE0) |
2612 (1ull << MSR_SE) |
2613 (1ull << MSR_DE) |
2614 (1ull << MSR_FE1) |
2615 (1ull << MSR_AL) |
2616 (1ull << MSR_EP) |
2617 (1ull << MSR_IR) |
2618 (1ull << MSR_DR) |
2619 (1ull << MSR_RI) |
2620 (1ull << MSR_LE);
2621 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
2622 pcc->excp_model = POWERPC_EXCP_6xx;
2623 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2624 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2625 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2626 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
2627}
2628
2629static void init_proc_e200(CPUPPCState *env)
2630{
2631 register_BookE_sprs(env, 0x000000070000FFFFULL);
2632
2633 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
2634 &spr_read_spefscr, &spr_write_spefscr,
2635 &spr_read_spefscr, &spr_write_spefscr,
2636 0x00000000);
2637
2638 register_BookE206_sprs(env, 0x0000005D, NULL, 0);
2639 register_usprgh_sprs(env);
2640
2641 spr_register(env, SPR_HID0, "HID0",
2642 SPR_NOACCESS, SPR_NOACCESS,
2643 &spr_read_generic, &spr_write_generic,
2644 0x00000000);
2645
2646 spr_register(env, SPR_HID1, "HID1",
2647 SPR_NOACCESS, SPR_NOACCESS,
2648 &spr_read_generic, &spr_write_generic,
2649 0x00000000);
2650
2651 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
2652 SPR_NOACCESS, SPR_NOACCESS,
2653 &spr_read_generic, &spr_write_generic,
2654 0x00000000);
2655
2656 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
2657 SPR_NOACCESS, SPR_NOACCESS,
2658 &spr_read_generic, &spr_write_generic,
2659 0x00000000);
2660
2661 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
2662 SPR_NOACCESS, SPR_NOACCESS,
2663 &spr_read_generic, &spr_write_generic,
2664 0x00000000);
2665
2666 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
2667 SPR_NOACCESS, SPR_NOACCESS,
2668 &spr_read_generic, &spr_write_generic,
2669 0x00000000);
2670
2671 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
2672 SPR_NOACCESS, SPR_NOACCESS,
2673 &spr_read_generic, &spr_write_generic,
2674 0x00000000);
2675
2676 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
2677 &spr_read_generic, SPR_NOACCESS,
2678 &spr_read_generic, SPR_NOACCESS,
2679 0x00000000);
2680
2681 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
2682 SPR_NOACCESS, SPR_NOACCESS,
2683 &spr_read_generic, &spr_write_generic,
2684 0x00000000);
2685
2686 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
2687 SPR_NOACCESS, SPR_NOACCESS,
2688 &spr_read_generic, &spr_write_generic,
2689 0x00000000);
2690
2691 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
2692 SPR_NOACCESS, SPR_NOACCESS,
2693 &spr_read_generic, &spr_write_generic,
2694 0x00000000);
2695
2696 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
2697 SPR_NOACCESS, SPR_NOACCESS,
2698 &spr_read_generic, &spr_write_generic,
2699 0x00000000);
2700
2701 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
2702 SPR_NOACCESS, SPR_NOACCESS,
2703 &spr_read_generic, &spr_write_generic,
2704 0x00000000);
2705
2706 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
2707 SPR_NOACCESS, SPR_NOACCESS,
2708 &spr_read_generic, &spr_write_generic,
2709 0x00000000);
2710
2711 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
2712 SPR_NOACCESS, SPR_NOACCESS,
2713 &spr_read_generic, &spr_write_generic,
2714 0x00000000);
2715 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
2716 SPR_NOACCESS, SPR_NOACCESS,
2717 &spr_read_generic, &spr_write_generic,
2718 0x00000000);
2719 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
2720 SPR_NOACCESS, SPR_NOACCESS,
2721 &spr_read_generic, &spr_write_generic,
2722 0x00000000);
2723#if !defined(CONFIG_USER_ONLY)
2724 env->nb_tlb = 64;
2725 env->nb_ways = 1;
2726 env->id_tlbs = 0;
2727 env->tlb_type = TLB_EMB;
2728#endif
2729 init_excp_e200(env, 0xFFFF0000UL);
2730 env->dcache_line_size = 32;
2731 env->icache_line_size = 32;
2732
2733}
2734
2735POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
2736{
2737 DeviceClass *dc = DEVICE_CLASS(oc);
2738 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2739
2740 dc->desc = "e200 core";
2741 pcc->init_proc = init_proc_e200;
2742 pcc->check_pow = check_pow_hid0;
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
2754 PPC_SPE | PPC_SPE_SINGLE |
2755 PPC_WRTEE | PPC_RFDI |
2756 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
2757 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2758 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
2759 PPC_BOOKE;
2760 pcc->msr_mask = (1ull << MSR_UCLE) |
2761 (1ull << MSR_SPE) |
2762 (1ull << MSR_POW) |
2763 (1ull << MSR_CE) |
2764 (1ull << MSR_EE) |
2765 (1ull << MSR_PR) |
2766 (1ull << MSR_FP) |
2767 (1ull << MSR_ME) |
2768 (1ull << MSR_FE0) |
2769 (1ull << MSR_DWE) |
2770 (1ull << MSR_DE) |
2771 (1ull << MSR_FE1) |
2772 (1ull << MSR_IR) |
2773 (1ull << MSR_DR);
2774 pcc->mmu_model = POWERPC_MMU_BOOKE206;
2775 pcc->excp_model = POWERPC_EXCP_BOOKE;
2776 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2777 pcc->bfd_mach = bfd_mach_ppc_860;
2778 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
2779 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
2780 POWERPC_FLAG_BUS_CLK;
2781}
2782
2783enum fsl_e500_version {
2784 fsl_e500v1,
2785 fsl_e500v2,
2786 fsl_e500mc,
2787 fsl_e5500,
2788 fsl_e6500,
2789};
2790
2791static void init_proc_e500(CPUPPCState *env, int version)
2792{
2793 uint32_t tlbncfg[2];
2794 uint64_t ivor_mask;
2795 uint64_t ivpr_mask = 0xFFFF0000ULL;
2796 uint32_t l1cfg0 = 0x3800
2797 | 0x0020;
2798 uint32_t l1cfg1 = 0x3800
2799 | 0x0020;
2800 uint32_t mmucfg = 0;
2801#if !defined(CONFIG_USER_ONLY)
2802 int i;
2803#endif
2804
2805
2806
2807
2808
2809
2810 switch (version) {
2811 case fsl_e500v1:
2812 case fsl_e500v2:
2813 default:
2814 ivor_mask = 0x0000000F0000FFFFULL;
2815 break;
2816 case fsl_e500mc:
2817 case fsl_e5500:
2818 ivor_mask = 0x000003FE0000FFFFULL;
2819 break;
2820 case fsl_e6500:
2821 ivor_mask = 0x000003FF0000FFFFULL;
2822 break;
2823 }
2824 register_BookE_sprs(env, ivor_mask);
2825
2826 spr_register(env, SPR_USPRG3, "USPRG3",
2827 &spr_read_ureg, SPR_NOACCESS,
2828 &spr_read_ureg, SPR_NOACCESS,
2829 0x00000000);
2830
2831
2832 spr_register(env, SPR_BOOKE_PIR, "PIR",
2833 SPR_NOACCESS, SPR_NOACCESS,
2834 &spr_read_generic, &spr_write_pir,
2835 0x00000000);
2836
2837 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
2838 &spr_read_spefscr, &spr_write_spefscr,
2839 &spr_read_spefscr, &spr_write_spefscr,
2840 0x00000000);
2841#if !defined(CONFIG_USER_ONLY)
2842
2843 env->nb_pids = 3;
2844 env->nb_ways = 2;
2845 env->id_tlbs = 0;
2846 switch (version) {
2847 case fsl_e500v1:
2848 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
2849 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
2850 break;
2851 case fsl_e500v2:
2852 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
2853 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
2854 break;
2855 case fsl_e500mc:
2856 case fsl_e5500:
2857 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
2858 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
2859 break;
2860 case fsl_e6500:
2861 mmucfg = 0x6510B45;
2862 env->nb_pids = 1;
2863 tlbncfg[0] = 0x08052400;
2864 tlbncfg[1] = 0x40028040;
2865 break;
2866 default:
2867 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
2868 env->spr[SPR_PVR]);
2869 }
2870#endif
2871
2872 switch (version) {
2873 case fsl_e500v1:
2874 case fsl_e500v2:
2875 env->dcache_line_size = 32;
2876 env->icache_line_size = 32;
2877 break;
2878 case fsl_e500mc:
2879 case fsl_e5500:
2880 env->dcache_line_size = 64;
2881 env->icache_line_size = 64;
2882 l1cfg0 |= 0x1000000;
2883 l1cfg1 |= 0x1000000;
2884 break;
2885 case fsl_e6500:
2886 env->dcache_line_size = 32;
2887 env->icache_line_size = 32;
2888 l1cfg0 |= 0x0F83820;
2889 l1cfg1 |= 0x0B83820;
2890 break;
2891 default:
2892 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
2893 env->spr[SPR_PVR]);
2894 }
2895 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
2896 register_usprgh_sprs(env);
2897
2898 spr_register(env, SPR_HID0, "HID0",
2899 SPR_NOACCESS, SPR_NOACCESS,
2900 &spr_read_generic, &spr_write_generic,
2901 0x00000000);
2902
2903 spr_register(env, SPR_HID1, "HID1",
2904 SPR_NOACCESS, SPR_NOACCESS,
2905 &spr_read_generic, &spr_write_generic,
2906 0x00000000);
2907
2908 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
2909 SPR_NOACCESS, SPR_NOACCESS,
2910 &spr_read_generic, &spr_write_generic,
2911 0x00000000);
2912
2913 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
2914 SPR_NOACCESS, SPR_NOACCESS,
2915 &spr_read_generic, &spr_write_generic,
2916 0x00000000);
2917
2918 spr_register(env, SPR_Exxx_MCAR, "MCAR",
2919 SPR_NOACCESS, SPR_NOACCESS,
2920 &spr_read_generic, &spr_write_generic,
2921 0x00000000);
2922
2923 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2924 SPR_NOACCESS, SPR_NOACCESS,
2925 &spr_read_generic, &spr_write_generic,
2926 0x00000000);
2927
2928 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
2929 SPR_NOACCESS, SPR_NOACCESS,
2930 &spr_read_generic, &spr_write_generic,
2931 0x00000000);
2932
2933 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
2934 SPR_NOACCESS, SPR_NOACCESS,
2935 &spr_read_generic, &spr_write_generic,
2936 0x00000000);
2937
2938 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
2939 &spr_read_generic, SPR_NOACCESS,
2940 &spr_read_generic, SPR_NOACCESS,
2941 l1cfg0);
2942 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
2943 &spr_read_generic, SPR_NOACCESS,
2944 &spr_read_generic, SPR_NOACCESS,
2945 l1cfg1);
2946 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
2947 SPR_NOACCESS, SPR_NOACCESS,
2948 &spr_read_generic, &spr_write_e500_l1csr0,
2949 0x00000000);
2950 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
2951 SPR_NOACCESS, SPR_NOACCESS,
2952 &spr_read_generic, &spr_write_e500_l1csr1,
2953 0x00000000);
2954 if (version != fsl_e500v1 && version != fsl_e500v2) {
2955 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0",
2956 SPR_NOACCESS, SPR_NOACCESS,
2957 &spr_read_generic, &spr_write_e500_l2csr0,
2958 0x00000000);
2959 }
2960 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2961 SPR_NOACCESS, SPR_NOACCESS,
2962 &spr_read_generic, &spr_write_generic,
2963 0x00000000);
2964 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2965 SPR_NOACCESS, SPR_NOACCESS,
2966 &spr_read_generic, &spr_write_generic,
2967 0x00000000);
2968 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
2969 SPR_NOACCESS, SPR_NOACCESS,
2970 &spr_read_generic, &spr_write_booke206_mmucsr0,
2971 0x00000000);
2972 spr_register(env, SPR_BOOKE_EPR, "EPR",
2973 SPR_NOACCESS, SPR_NOACCESS,
2974 &spr_read_generic, SPR_NOACCESS,
2975 0x00000000);
2976
2977 if ((version == fsl_e5500) || (version == fsl_e6500)) {
2978 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
2979 SPR_NOACCESS, SPR_NOACCESS,
2980 &spr_read_generic, &spr_write_generic,
2981 0x00000000);
2982 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
2983 SPR_NOACCESS, SPR_NOACCESS,
2984 &spr_read_mas73, &spr_write_mas73,
2985 0x00000000);
2986 ivpr_mask = (target_ulong)~0xFFFFULL;
2987 }
2988
2989 if (version == fsl_e6500) {
2990
2991 spr_register(env, SPR_TIR, "TIR",
2992 SPR_NOACCESS, SPR_NOACCESS,
2993 &spr_read_generic, SPR_NOACCESS,
2994 0x00000000);
2995 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
2996 SPR_NOACCESS, SPR_NOACCESS,
2997 &spr_read_generic, SPR_NOACCESS,
2998 0x00000004);
2999 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
3000 SPR_NOACCESS, SPR_NOACCESS,
3001 &spr_read_generic, SPR_NOACCESS,
3002 0x7FFFFFFC);
3003 }
3004
3005#if !defined(CONFIG_USER_ONLY)
3006 env->nb_tlb = 0;
3007 env->tlb_type = TLB_MAS;
3008 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
3009 env->nb_tlb += booke206_tlb_size(env, i);
3010 }
3011#endif
3012
3013 init_excp_e200(env, ivpr_mask);
3014
3015 ppce500_irq_init(env_archcpu(env));
3016}
3017
3018static void init_proc_e500v1(CPUPPCState *env)
3019{
3020 init_proc_e500(env, fsl_e500v1);
3021}
3022
3023POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
3024{
3025 DeviceClass *dc = DEVICE_CLASS(oc);
3026 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3027
3028 dc->desc = "e500v1 core";
3029 pcc->init_proc = init_proc_e500v1;
3030 pcc->check_pow = check_pow_hid0;
3031 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3032 PPC_SPE | PPC_SPE_SINGLE |
3033 PPC_WRTEE | PPC_RFDI |
3034 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3035 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3036 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3037 pcc->insns_flags2 = PPC2_BOOKE206;
3038 pcc->msr_mask = (1ull << MSR_UCLE) |
3039 (1ull << MSR_SPE) |
3040 (1ull << MSR_POW) |
3041 (1ull << MSR_CE) |
3042 (1ull << MSR_EE) |
3043 (1ull << MSR_PR) |
3044 (1ull << MSR_FP) |
3045 (1ull << MSR_ME) |
3046 (1ull << MSR_FE0) |
3047 (1ull << MSR_DWE) |
3048 (1ull << MSR_DE) |
3049 (1ull << MSR_FE1) |
3050 (1ull << MSR_IR) |
3051 (1ull << MSR_DR);
3052 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3053 pcc->excp_model = POWERPC_EXCP_BOOKE;
3054 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3055 pcc->bfd_mach = bfd_mach_ppc_860;
3056 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3057 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3058 POWERPC_FLAG_BUS_CLK;
3059}
3060
3061static void init_proc_e500v2(CPUPPCState *env)
3062{
3063 init_proc_e500(env, fsl_e500v2);
3064}
3065
3066POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
3067{
3068 DeviceClass *dc = DEVICE_CLASS(oc);
3069 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3070
3071 dc->desc = "e500v2 core";
3072 pcc->init_proc = init_proc_e500v2;
3073 pcc->check_pow = check_pow_hid0;
3074 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3075 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
3076 PPC_WRTEE | PPC_RFDI |
3077 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3078 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3079 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3080 pcc->insns_flags2 = PPC2_BOOKE206;
3081 pcc->msr_mask = (1ull << MSR_UCLE) |
3082 (1ull << MSR_SPE) |
3083 (1ull << MSR_POW) |
3084 (1ull << MSR_CE) |
3085 (1ull << MSR_EE) |
3086 (1ull << MSR_PR) |
3087 (1ull << MSR_FP) |
3088 (1ull << MSR_ME) |
3089 (1ull << MSR_FE0) |
3090 (1ull << MSR_DWE) |
3091 (1ull << MSR_DE) |
3092 (1ull << MSR_FE1) |
3093 (1ull << MSR_IR) |
3094 (1ull << MSR_DR);
3095 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3096 pcc->excp_model = POWERPC_EXCP_BOOKE;
3097 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3098 pcc->bfd_mach = bfd_mach_ppc_860;
3099 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3100 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3101 POWERPC_FLAG_BUS_CLK;
3102}
3103
3104static void init_proc_e500mc(CPUPPCState *env)
3105{
3106 init_proc_e500(env, fsl_e500mc);
3107}
3108
3109POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
3110{
3111 DeviceClass *dc = DEVICE_CLASS(oc);
3112 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3113
3114 dc->desc = "e500mc core";
3115 pcc->init_proc = init_proc_e500mc;
3116 pcc->check_pow = check_pow_none;
3117 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3118 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3119 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3120 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3121 PPC_FLOAT | PPC_FLOAT_FRES |
3122 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3123 PPC_FLOAT_STFIWX | PPC_WAIT |
3124 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3125 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
3126 pcc->msr_mask = (1ull << MSR_GS) |
3127 (1ull << MSR_UCLE) |
3128 (1ull << MSR_CE) |
3129 (1ull << MSR_EE) |
3130 (1ull << MSR_PR) |
3131 (1ull << MSR_FP) |
3132 (1ull << MSR_ME) |
3133 (1ull << MSR_FE0) |
3134 (1ull << MSR_DE) |
3135 (1ull << MSR_FE1) |
3136 (1ull << MSR_IR) |
3137 (1ull << MSR_DR) |
3138 (1ull << MSR_PX) |
3139 (1ull << MSR_RI);
3140 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3141 pcc->excp_model = POWERPC_EXCP_BOOKE;
3142 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3143
3144 pcc->bfd_mach = bfd_mach_ppc_e500;
3145 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3146 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3147}
3148
3149#ifdef TARGET_PPC64
3150static void init_proc_e5500(CPUPPCState *env)
3151{
3152 init_proc_e500(env, fsl_e5500);
3153}
3154
3155POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
3156{
3157 DeviceClass *dc = DEVICE_CLASS(oc);
3158 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3159
3160 dc->desc = "e5500 core";
3161 pcc->init_proc = init_proc_e5500;
3162 pcc->check_pow = check_pow_none;
3163 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3164 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3165 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3166 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3167 PPC_FLOAT | PPC_FLOAT_FRES |
3168 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3169 PPC_FLOAT_STFIWX | PPC_WAIT |
3170 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3171 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
3172 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3173 PPC2_FP_CVT_S64;
3174 pcc->msr_mask = (1ull << MSR_CM) |
3175 (1ull << MSR_GS) |
3176 (1ull << MSR_UCLE) |
3177 (1ull << MSR_CE) |
3178 (1ull << MSR_EE) |
3179 (1ull << MSR_PR) |
3180 (1ull << MSR_FP) |
3181 (1ull << MSR_ME) |
3182 (1ull << MSR_FE0) |
3183 (1ull << MSR_DE) |
3184 (1ull << MSR_FE1) |
3185 (1ull << MSR_IR) |
3186 (1ull << MSR_DR) |
3187 (1ull << MSR_PX) |
3188 (1ull << MSR_RI);
3189 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3190 pcc->excp_model = POWERPC_EXCP_BOOKE;
3191 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3192
3193 pcc->bfd_mach = bfd_mach_ppc_e500;
3194 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3195 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3196}
3197
3198static void init_proc_e6500(CPUPPCState *env)
3199{
3200 init_proc_e500(env, fsl_e6500);
3201}
3202
3203POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
3204{
3205 DeviceClass *dc = DEVICE_CLASS(oc);
3206 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3207
3208 dc->desc = "e6500 core";
3209 pcc->init_proc = init_proc_e6500;
3210 pcc->check_pow = check_pow_none;
3211 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3212 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3213 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3214 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3215 PPC_FLOAT | PPC_FLOAT_FRES |
3216 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3217 PPC_FLOAT_STFIWX | PPC_WAIT |
3218 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3219 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
3220 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3221 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
3222 pcc->msr_mask = (1ull << MSR_CM) |
3223 (1ull << MSR_GS) |
3224 (1ull << MSR_UCLE) |
3225 (1ull << MSR_CE) |
3226 (1ull << MSR_EE) |
3227 (1ull << MSR_PR) |
3228 (1ull << MSR_FP) |
3229 (1ull << MSR_ME) |
3230 (1ull << MSR_FE0) |
3231 (1ull << MSR_DE) |
3232 (1ull << MSR_FE1) |
3233 (1ull << MSR_IS) |
3234 (1ull << MSR_DS) |
3235 (1ull << MSR_PX) |
3236 (1ull << MSR_RI) |
3237 (1ull << MSR_VR);
3238 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3239 pcc->excp_model = POWERPC_EXCP_BOOKE;
3240 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3241 pcc->bfd_mach = bfd_mach_ppc_e500;
3242 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3243 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
3244}
3245
3246#endif
3247
3248
3249static void init_proc_603(CPUPPCState *env)
3250{
3251 register_non_embedded_sprs(env);
3252 register_sdr1_sprs(env);
3253 register_603_sprs(env);
3254
3255
3256 register_low_BATs(env);
3257 register_6xx_7xx_soft_tlb(env, 64, 2);
3258 init_excp_603(env);
3259 env->dcache_line_size = 32;
3260 env->icache_line_size = 32;
3261
3262 ppc6xx_irq_init(env_archcpu(env));
3263}
3264
3265POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
3266{
3267 DeviceClass *dc = DEVICE_CLASS(oc);
3268 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3269
3270 dc->desc = "PowerPC 603";
3271 pcc->init_proc = init_proc_603;
3272 pcc->check_pow = check_pow_hid0;
3273 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3274 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3275 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3276 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3277 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3278 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3279 PPC_SEGMENT | PPC_EXTERN;
3280 pcc->msr_mask = (1ull << MSR_POW) |
3281 (1ull << MSR_TGPR) |
3282 (1ull << MSR_ILE) |
3283 (1ull << MSR_EE) |
3284 (1ull << MSR_PR) |
3285 (1ull << MSR_FP) |
3286 (1ull << MSR_ME) |
3287 (1ull << MSR_FE0) |
3288 (1ull << MSR_SE) |
3289 (1ull << MSR_DE) |
3290 (1ull << MSR_FE1) |
3291 (1ull << MSR_EP) |
3292 (1ull << MSR_IR) |
3293 (1ull << MSR_DR) |
3294 (1ull << MSR_RI) |
3295 (1ull << MSR_LE);
3296 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3297 pcc->excp_model = POWERPC_EXCP_6xx;
3298 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3299 pcc->bfd_mach = bfd_mach_ppc_603;
3300 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3301 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3302}
3303
3304POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
3305{
3306 DeviceClass *dc = DEVICE_CLASS(oc);
3307 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3308
3309 dc->desc = "PowerPC 603e";
3310 pcc->init_proc = init_proc_603;
3311 pcc->check_pow = check_pow_hid0;
3312 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3313 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3314 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3315 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3316 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3317 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3318 PPC_SEGMENT | PPC_EXTERN;
3319 pcc->msr_mask = (1ull << MSR_POW) |
3320 (1ull << MSR_TGPR) |
3321 (1ull << MSR_ILE) |
3322 (1ull << MSR_EE) |
3323 (1ull << MSR_PR) |
3324 (1ull << MSR_FP) |
3325 (1ull << MSR_ME) |
3326 (1ull << MSR_FE0) |
3327 (1ull << MSR_SE) |
3328 (1ull << MSR_DE) |
3329 (1ull << MSR_FE1) |
3330 (1ull << MSR_EP) |
3331 (1ull << MSR_IR) |
3332 (1ull << MSR_DR) |
3333 (1ull << MSR_RI) |
3334 (1ull << MSR_LE);
3335 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3336 pcc->excp_model = POWERPC_EXCP_6xx;
3337 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3338 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3339 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3340 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3341}
3342
3343static void init_proc_e300(CPUPPCState *env)
3344{
3345 init_proc_603(env);
3346 register_e300_sprs(env);
3347}
3348
3349POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
3350{
3351 DeviceClass *dc = DEVICE_CLASS(oc);
3352 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3353
3354 dc->desc = "e300 core";
3355 pcc->init_proc = init_proc_e300;
3356 pcc->check_pow = check_pow_hid0;
3357 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3358 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3359 PPC_FLOAT_STFIWX |
3360 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3361 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3362 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3363 PPC_SEGMENT | PPC_EXTERN;
3364 pcc->msr_mask = (1ull << MSR_POW) |
3365 (1ull << MSR_TGPR) |
3366 (1ull << MSR_ILE) |
3367 (1ull << MSR_EE) |
3368 (1ull << MSR_PR) |
3369 (1ull << MSR_FP) |
3370 (1ull << MSR_ME) |
3371 (1ull << MSR_FE0) |
3372 (1ull << MSR_SE) |
3373 (1ull << MSR_DE) |
3374 (1ull << MSR_FE1) |
3375 (1ull << MSR_AL) |
3376 (1ull << MSR_EP) |
3377 (1ull << MSR_IR) |
3378 (1ull << MSR_DR) |
3379 (1ull << MSR_RI) |
3380 (1ull << MSR_LE);
3381 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3382 pcc->excp_model = POWERPC_EXCP_6xx;
3383 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3384 pcc->bfd_mach = bfd_mach_ppc_603;
3385 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3386 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3387}
3388
3389static void init_proc_604(CPUPPCState *env)
3390{
3391 register_non_embedded_sprs(env);
3392 register_sdr1_sprs(env);
3393 register_604_sprs(env);
3394
3395
3396 register_low_BATs(env);
3397 init_excp_604(env);
3398 env->dcache_line_size = 32;
3399 env->icache_line_size = 32;
3400
3401 ppc6xx_irq_init(env_archcpu(env));
3402}
3403
3404POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
3405{
3406 DeviceClass *dc = DEVICE_CLASS(oc);
3407 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3408
3409 dc->desc = "PowerPC 604";
3410 pcc->init_proc = init_proc_604;
3411 pcc->check_pow = check_pow_nocheck;
3412 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3413 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3414 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3415 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3416 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3417 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3418 PPC_SEGMENT | PPC_EXTERN;
3419 pcc->msr_mask = (1ull << MSR_POW) |
3420 (1ull << MSR_ILE) |
3421 (1ull << MSR_EE) |
3422 (1ull << MSR_PR) |
3423 (1ull << MSR_FP) |
3424 (1ull << MSR_ME) |
3425 (1ull << MSR_FE0) |
3426 (1ull << MSR_SE) |
3427 (1ull << MSR_DE) |
3428 (1ull << MSR_FE1) |
3429 (1ull << MSR_EP) |
3430 (1ull << MSR_IR) |
3431 (1ull << MSR_DR) |
3432 (1ull << MSR_PMM) |
3433 (1ull << MSR_RI) |
3434 (1ull << MSR_LE);
3435 pcc->mmu_model = POWERPC_MMU_32B;
3436 pcc->excp_model = POWERPC_EXCP_6xx;
3437 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3438 pcc->bfd_mach = bfd_mach_ppc_604;
3439 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3440 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3441}
3442
3443static void init_proc_604E(CPUPPCState *env)
3444{
3445 init_proc_604(env);
3446 register_604e_sprs(env);
3447}
3448
3449POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
3450{
3451 DeviceClass *dc = DEVICE_CLASS(oc);
3452 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3453
3454 dc->desc = "PowerPC 604E";
3455 pcc->init_proc = init_proc_604E;
3456 pcc->check_pow = check_pow_nocheck;
3457 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3458 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3459 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3460 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3461 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3462 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3463 PPC_SEGMENT | PPC_EXTERN;
3464 pcc->msr_mask = (1ull << MSR_POW) |
3465 (1ull << MSR_ILE) |
3466 (1ull << MSR_EE) |
3467 (1ull << MSR_PR) |
3468 (1ull << MSR_FP) |
3469 (1ull << MSR_ME) |
3470 (1ull << MSR_FE0) |
3471 (1ull << MSR_SE) |
3472 (1ull << MSR_DE) |
3473 (1ull << MSR_FE1) |
3474 (1ull << MSR_EP) |
3475 (1ull << MSR_IR) |
3476 (1ull << MSR_DR) |
3477 (1ull << MSR_PMM) |
3478 (1ull << MSR_RI) |
3479 (1ull << MSR_LE);
3480 pcc->mmu_model = POWERPC_MMU_32B;
3481 pcc->excp_model = POWERPC_EXCP_6xx;
3482 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3483 pcc->bfd_mach = bfd_mach_ppc_604;
3484 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3485 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3486}
3487
3488static void init_proc_740(CPUPPCState *env)
3489{
3490 register_non_embedded_sprs(env);
3491 register_sdr1_sprs(env);
3492 register_7xx_sprs(env);
3493
3494 register_thrm_sprs(env);
3495
3496
3497 register_low_BATs(env);
3498 init_excp_7x0(env);
3499 env->dcache_line_size = 32;
3500 env->icache_line_size = 32;
3501
3502 ppc6xx_irq_init(env_archcpu(env));
3503}
3504
3505POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
3506{
3507 DeviceClass *dc = DEVICE_CLASS(oc);
3508 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3509
3510 dc->desc = "PowerPC 740";
3511 pcc->init_proc = init_proc_740;
3512 pcc->check_pow = check_pow_hid0;
3513 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3514 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3515 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3516 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3517 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3518 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3519 PPC_SEGMENT | PPC_EXTERN;
3520 pcc->msr_mask = (1ull << MSR_POW) |
3521 (1ull << MSR_ILE) |
3522 (1ull << MSR_EE) |
3523 (1ull << MSR_PR) |
3524 (1ull << MSR_FP) |
3525 (1ull << MSR_ME) |
3526 (1ull << MSR_FE0) |
3527 (1ull << MSR_SE) |
3528 (1ull << MSR_DE) |
3529 (1ull << MSR_FE1) |
3530 (1ull << MSR_EP) |
3531 (1ull << MSR_IR) |
3532 (1ull << MSR_DR) |
3533 (1ull << MSR_PMM) |
3534 (1ull << MSR_RI) |
3535 (1ull << MSR_LE);
3536 pcc->mmu_model = POWERPC_MMU_32B;
3537 pcc->excp_model = POWERPC_EXCP_7xx;
3538 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3539 pcc->bfd_mach = bfd_mach_ppc_750;
3540 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3541 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3542}
3543
3544static void init_proc_750(CPUPPCState *env)
3545{
3546 register_non_embedded_sprs(env);
3547 register_sdr1_sprs(env);
3548 register_7xx_sprs(env);
3549
3550 spr_register(env, SPR_L2CR, "L2CR",
3551 SPR_NOACCESS, SPR_NOACCESS,
3552 &spr_read_generic, spr_access_nop,
3553 0x00000000);
3554
3555 register_thrm_sprs(env);
3556
3557
3558 register_low_BATs(env);
3559
3560
3561
3562
3563 init_excp_7x0(env);
3564 env->dcache_line_size = 32;
3565 env->icache_line_size = 32;
3566
3567 ppc6xx_irq_init(env_archcpu(env));
3568}
3569
3570POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
3571{
3572 DeviceClass *dc = DEVICE_CLASS(oc);
3573 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3574
3575 dc->desc = "PowerPC 750";
3576 pcc->init_proc = init_proc_750;
3577 pcc->check_pow = check_pow_hid0;
3578 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3579 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3580 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3581 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3582 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3583 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3584 PPC_SEGMENT | PPC_EXTERN;
3585 pcc->msr_mask = (1ull << MSR_POW) |
3586 (1ull << MSR_ILE) |
3587 (1ull << MSR_EE) |
3588 (1ull << MSR_PR) |
3589 (1ull << MSR_FP) |
3590 (1ull << MSR_ME) |
3591 (1ull << MSR_FE0) |
3592 (1ull << MSR_SE) |
3593 (1ull << MSR_DE) |
3594 (1ull << MSR_FE1) |
3595 (1ull << MSR_EP) |
3596 (1ull << MSR_IR) |
3597 (1ull << MSR_DR) |
3598 (1ull << MSR_PMM) |
3599 (1ull << MSR_RI) |
3600 (1ull << MSR_LE);
3601 pcc->mmu_model = POWERPC_MMU_32B;
3602 pcc->excp_model = POWERPC_EXCP_7xx;
3603 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3604 pcc->bfd_mach = bfd_mach_ppc_750;
3605 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3606 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3607}
3608
3609static void init_proc_750cl(CPUPPCState *env)
3610{
3611 register_non_embedded_sprs(env);
3612 register_sdr1_sprs(env);
3613 register_7xx_sprs(env);
3614
3615 spr_register(env, SPR_L2CR, "L2CR",
3616 SPR_NOACCESS, SPR_NOACCESS,
3617 &spr_read_generic, spr_access_nop,
3618 0x00000000);
3619
3620
3621 spr_register(env, SPR_THRM1, "THRM1",
3622 SPR_NOACCESS, SPR_NOACCESS,
3623 &spr_read_generic, &spr_write_generic,
3624 0x00000000);
3625 spr_register(env, SPR_THRM2, "THRM2",
3626 SPR_NOACCESS, SPR_NOACCESS,
3627 &spr_read_generic, &spr_write_generic,
3628 0x00000000);
3629 spr_register(env, SPR_THRM3, "THRM3",
3630 SPR_NOACCESS, SPR_NOACCESS,
3631 &spr_read_generic, &spr_write_generic,
3632 0x00000000);
3633
3634 spr_register(env, SPR_750_TDCL, "TDCL",
3635 SPR_NOACCESS, SPR_NOACCESS,
3636 &spr_read_generic, &spr_write_generic,
3637 0x00000000);
3638 spr_register(env, SPR_750_TDCH, "TDCH",
3639 SPR_NOACCESS, SPR_NOACCESS,
3640 &spr_read_generic, &spr_write_generic,
3641 0x00000000);
3642
3643 spr_register(env, SPR_750_WPAR, "WPAR",
3644 SPR_NOACCESS, SPR_NOACCESS,
3645 &spr_read_generic, &spr_write_generic,
3646 0x00000000);
3647 spr_register(env, SPR_750_DMAL, "DMAL",
3648 SPR_NOACCESS, SPR_NOACCESS,
3649 &spr_read_generic, &spr_write_generic,
3650 0x00000000);
3651 spr_register(env, SPR_750_DMAU, "DMAU",
3652 SPR_NOACCESS, SPR_NOACCESS,
3653 &spr_read_generic, &spr_write_generic,
3654 0x00000000);
3655
3656 spr_register(env, SPR_750CL_HID2, "HID2",
3657 SPR_NOACCESS, SPR_NOACCESS,
3658 &spr_read_generic, &spr_write_generic,
3659 0x00000000);
3660
3661 spr_register(env, SPR_750CL_HID4, "HID4",
3662 SPR_NOACCESS, SPR_NOACCESS,
3663 &spr_read_generic, &spr_write_generic,
3664 0x00000000);
3665
3666 spr_register(env, SPR_750_GQR0, "GQR0",
3667 SPR_NOACCESS, SPR_NOACCESS,
3668 &spr_read_generic, &spr_write_generic,
3669 0x00000000);
3670
3671 spr_register(env, SPR_750_GQR1, "GQR1",
3672 SPR_NOACCESS, SPR_NOACCESS,
3673 &spr_read_generic, &spr_write_generic,
3674 0x00000000);
3675
3676 spr_register(env, SPR_750_GQR2, "GQR2",
3677 SPR_NOACCESS, SPR_NOACCESS,
3678 &spr_read_generic, &spr_write_generic,
3679 0x00000000);
3680
3681 spr_register(env, SPR_750_GQR3, "GQR3",
3682 SPR_NOACCESS, SPR_NOACCESS,
3683 &spr_read_generic, &spr_write_generic,
3684 0x00000000);
3685
3686 spr_register(env, SPR_750_GQR4, "GQR4",
3687 SPR_NOACCESS, SPR_NOACCESS,
3688 &spr_read_generic, &spr_write_generic,
3689 0x00000000);
3690
3691 spr_register(env, SPR_750_GQR5, "GQR5",
3692 SPR_NOACCESS, SPR_NOACCESS,
3693 &spr_read_generic, &spr_write_generic,
3694 0x00000000);
3695
3696 spr_register(env, SPR_750_GQR6, "GQR6",
3697 SPR_NOACCESS, SPR_NOACCESS,
3698 &spr_read_generic, &spr_write_generic,
3699 0x00000000);
3700
3701 spr_register(env, SPR_750_GQR7, "GQR7",
3702 SPR_NOACCESS, SPR_NOACCESS,
3703 &spr_read_generic, &spr_write_generic,
3704 0x00000000);
3705
3706 register_low_BATs(env);
3707
3708 register_high_BATs(env);
3709 init_excp_750cl(env);
3710 env->dcache_line_size = 32;
3711 env->icache_line_size = 32;
3712
3713 ppc6xx_irq_init(env_archcpu(env));
3714}
3715
3716POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
3717{
3718 DeviceClass *dc = DEVICE_CLASS(oc);
3719 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3720
3721 dc->desc = "PowerPC 750 CL";
3722 pcc->init_proc = init_proc_750cl;
3723 pcc->check_pow = check_pow_hid0;
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3764 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3765 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3766 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3767 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3768 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3769 PPC_SEGMENT | PPC_EXTERN;
3770 pcc->msr_mask = (1ull << MSR_POW) |
3771 (1ull << MSR_ILE) |
3772 (1ull << MSR_EE) |
3773 (1ull << MSR_PR) |
3774 (1ull << MSR_FP) |
3775 (1ull << MSR_ME) |
3776 (1ull << MSR_FE0) |
3777 (1ull << MSR_SE) |
3778 (1ull << MSR_DE) |
3779 (1ull << MSR_FE1) |
3780 (1ull << MSR_EP) |
3781 (1ull << MSR_IR) |
3782 (1ull << MSR_DR) |
3783 (1ull << MSR_PMM) |
3784 (1ull << MSR_RI) |
3785 (1ull << MSR_LE);
3786 pcc->mmu_model = POWERPC_MMU_32B;
3787 pcc->excp_model = POWERPC_EXCP_7xx;
3788 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3789 pcc->bfd_mach = bfd_mach_ppc_750;
3790 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3791 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3792}
3793
3794static void init_proc_750cx(CPUPPCState *env)
3795{
3796 register_non_embedded_sprs(env);
3797 register_sdr1_sprs(env);
3798 register_7xx_sprs(env);
3799
3800 spr_register(env, SPR_L2CR, "L2CR",
3801 SPR_NOACCESS, SPR_NOACCESS,
3802 &spr_read_generic, spr_access_nop,
3803 0x00000000);
3804
3805 register_thrm_sprs(env);
3806
3807 spr_register(env, SPR_SDA, "SDA",
3808 SPR_NOACCESS, SPR_NOACCESS,
3809 &spr_read_generic, &spr_write_generic,
3810 0x00000000);
3811
3812
3813 register_low_BATs(env);
3814
3815 register_high_BATs(env);
3816 init_excp_750cx(env);
3817 env->dcache_line_size = 32;
3818 env->icache_line_size = 32;
3819
3820 ppc6xx_irq_init(env_archcpu(env));
3821}
3822
3823POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
3824{
3825 DeviceClass *dc = DEVICE_CLASS(oc);
3826 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3827
3828 dc->desc = "PowerPC 750CX";
3829 pcc->init_proc = init_proc_750cx;
3830 pcc->check_pow = check_pow_hid0;
3831 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3832 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3833 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3834 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3835 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3836 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3837 PPC_SEGMENT | PPC_EXTERN;
3838 pcc->msr_mask = (1ull << MSR_POW) |
3839 (1ull << MSR_ILE) |
3840 (1ull << MSR_EE) |
3841 (1ull << MSR_PR) |
3842 (1ull << MSR_FP) |
3843 (1ull << MSR_ME) |
3844 (1ull << MSR_FE0) |
3845 (1ull << MSR_SE) |
3846 (1ull << MSR_DE) |
3847 (1ull << MSR_FE1) |
3848 (1ull << MSR_EP) |
3849 (1ull << MSR_IR) |
3850 (1ull << MSR_DR) |
3851 (1ull << MSR_PMM) |
3852 (1ull << MSR_RI) |
3853 (1ull << MSR_LE);
3854 pcc->mmu_model = POWERPC_MMU_32B;
3855 pcc->excp_model = POWERPC_EXCP_7xx;
3856 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3857 pcc->bfd_mach = bfd_mach_ppc_750;
3858 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3859 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3860}
3861
3862static void init_proc_750fx(CPUPPCState *env)
3863{
3864 register_non_embedded_sprs(env);
3865 register_sdr1_sprs(env);
3866 register_7xx_sprs(env);
3867
3868 spr_register(env, SPR_L2CR, "L2CR",
3869 SPR_NOACCESS, SPR_NOACCESS,
3870 &spr_read_generic, spr_access_nop,
3871 0x00000000);
3872
3873 register_thrm_sprs(env);
3874
3875 spr_register(env, SPR_750_THRM4, "THRM4",
3876 SPR_NOACCESS, SPR_NOACCESS,
3877 &spr_read_generic, &spr_write_generic,
3878 0x00000000);
3879
3880 spr_register(env, SPR_750FX_HID2, "HID2",
3881 SPR_NOACCESS, SPR_NOACCESS,
3882 &spr_read_generic, &spr_write_generic,
3883 0x00000000);
3884
3885 register_low_BATs(env);
3886
3887 register_high_BATs(env);
3888 init_excp_7x0(env);
3889 env->dcache_line_size = 32;
3890 env->icache_line_size = 32;
3891
3892 ppc6xx_irq_init(env_archcpu(env));
3893}
3894
3895POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
3896{
3897 DeviceClass *dc = DEVICE_CLASS(oc);
3898 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3899
3900 dc->desc = "PowerPC 750FX";
3901 pcc->init_proc = init_proc_750fx;
3902 pcc->check_pow = check_pow_hid0;
3903 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3904 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3905 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3906 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3907 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3908 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3909 PPC_SEGMENT | PPC_EXTERN;
3910 pcc->msr_mask = (1ull << MSR_POW) |
3911 (1ull << MSR_ILE) |
3912 (1ull << MSR_EE) |
3913 (1ull << MSR_PR) |
3914 (1ull << MSR_FP) |
3915 (1ull << MSR_ME) |
3916 (1ull << MSR_FE0) |
3917 (1ull << MSR_SE) |
3918 (1ull << MSR_DE) |
3919 (1ull << MSR_FE1) |
3920 (1ull << MSR_EP) |
3921 (1ull << MSR_IR) |
3922 (1ull << MSR_DR) |
3923 (1ull << MSR_PMM) |
3924 (1ull << MSR_RI) |
3925 (1ull << MSR_LE);
3926 pcc->mmu_model = POWERPC_MMU_32B;
3927 pcc->excp_model = POWERPC_EXCP_7xx;
3928 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3929 pcc->bfd_mach = bfd_mach_ppc_750;
3930 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3931 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3932}
3933
3934static void init_proc_750gx(CPUPPCState *env)
3935{
3936 register_non_embedded_sprs(env);
3937 register_sdr1_sprs(env);
3938 register_7xx_sprs(env);
3939
3940 spr_register(env, SPR_L2CR, "L2CR",
3941 SPR_NOACCESS, SPR_NOACCESS,
3942 &spr_read_generic, spr_access_nop,
3943 0x00000000);
3944
3945 register_thrm_sprs(env);
3946
3947 spr_register(env, SPR_750_THRM4, "THRM4",
3948 SPR_NOACCESS, SPR_NOACCESS,
3949 &spr_read_generic, &spr_write_generic,
3950 0x00000000);
3951
3952 spr_register(env, SPR_750FX_HID2, "HID2",
3953 SPR_NOACCESS, SPR_NOACCESS,
3954 &spr_read_generic, &spr_write_generic,
3955 0x00000000);
3956
3957 register_low_BATs(env);
3958
3959 register_high_BATs(env);
3960 init_excp_7x0(env);
3961 env->dcache_line_size = 32;
3962 env->icache_line_size = 32;
3963
3964 ppc6xx_irq_init(env_archcpu(env));
3965}
3966
3967POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
3968{
3969 DeviceClass *dc = DEVICE_CLASS(oc);
3970 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3971
3972 dc->desc = "PowerPC 750GX";
3973 pcc->init_proc = init_proc_750gx;
3974 pcc->check_pow = check_pow_hid0;
3975 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3976 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3977 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3978 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3979 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3980 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3981 PPC_SEGMENT | PPC_EXTERN;
3982 pcc->msr_mask = (1ull << MSR_POW) |
3983 (1ull << MSR_ILE) |
3984 (1ull << MSR_EE) |
3985 (1ull << MSR_PR) |
3986 (1ull << MSR_FP) |
3987 (1ull << MSR_ME) |
3988 (1ull << MSR_FE0) |
3989 (1ull << MSR_SE) |
3990 (1ull << MSR_DE) |
3991 (1ull << MSR_FE1) |
3992 (1ull << MSR_EP) |
3993 (1ull << MSR_IR) |
3994 (1ull << MSR_DR) |
3995 (1ull << MSR_PMM) |
3996 (1ull << MSR_RI) |
3997 (1ull << MSR_LE);
3998 pcc->mmu_model = POWERPC_MMU_32B;
3999 pcc->excp_model = POWERPC_EXCP_7xx;
4000 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4001 pcc->bfd_mach = bfd_mach_ppc_750;
4002 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4003 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4004}
4005
4006static void init_proc_745(CPUPPCState *env)
4007{
4008 register_non_embedded_sprs(env);
4009 register_sdr1_sprs(env);
4010 register_7xx_sprs(env);
4011 register_745_sprs(env);
4012
4013 register_thrm_sprs(env);
4014
4015
4016 register_low_BATs(env);
4017 register_high_BATs(env);
4018 register_6xx_7xx_soft_tlb(env, 64, 2);
4019 init_excp_7x5(env);
4020 env->dcache_line_size = 32;
4021 env->icache_line_size = 32;
4022
4023 ppc6xx_irq_init(env_archcpu(env));
4024}
4025
4026POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
4027{
4028 DeviceClass *dc = DEVICE_CLASS(oc);
4029 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4030
4031 dc->desc = "PowerPC 745";
4032 pcc->init_proc = init_proc_745;
4033 pcc->check_pow = check_pow_hid0;
4034 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4035 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4036 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4037 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4038 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4039 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4040 PPC_SEGMENT | PPC_EXTERN;
4041 pcc->msr_mask = (1ull << MSR_POW) |
4042 (1ull << MSR_ILE) |
4043 (1ull << MSR_EE) |
4044 (1ull << MSR_PR) |
4045 (1ull << MSR_FP) |
4046 (1ull << MSR_ME) |
4047 (1ull << MSR_FE0) |
4048 (1ull << MSR_SE) |
4049 (1ull << MSR_DE) |
4050 (1ull << MSR_FE1) |
4051 (1ull << MSR_EP) |
4052 (1ull << MSR_IR) |
4053 (1ull << MSR_DR) |
4054 (1ull << MSR_PMM) |
4055 (1ull << MSR_RI) |
4056 (1ull << MSR_LE);
4057 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4058 pcc->excp_model = POWERPC_EXCP_7xx;
4059 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4060 pcc->bfd_mach = bfd_mach_ppc_750;
4061 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4062 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4063}
4064
4065static void init_proc_755(CPUPPCState *env)
4066{
4067 init_proc_745(env);
4068 register_755_sprs(env);
4069}
4070
4071POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
4072{
4073 DeviceClass *dc = DEVICE_CLASS(oc);
4074 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4075
4076 dc->desc = "PowerPC 755";
4077 pcc->init_proc = init_proc_755;
4078 pcc->check_pow = check_pow_hid0;
4079 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4080 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4081 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4082 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4083 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4084 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4085 PPC_SEGMENT | PPC_EXTERN;
4086 pcc->msr_mask = (1ull << MSR_POW) |
4087 (1ull << MSR_ILE) |
4088 (1ull << MSR_EE) |
4089 (1ull << MSR_PR) |
4090 (1ull << MSR_FP) |
4091 (1ull << MSR_ME) |
4092 (1ull << MSR_FE0) |
4093 (1ull << MSR_SE) |
4094 (1ull << MSR_DE) |
4095 (1ull << MSR_FE1) |
4096 (1ull << MSR_EP) |
4097 (1ull << MSR_IR) |
4098 (1ull << MSR_DR) |
4099 (1ull << MSR_PMM) |
4100 (1ull << MSR_RI) |
4101 (1ull << MSR_LE);
4102 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4103 pcc->excp_model = POWERPC_EXCP_7xx;
4104 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4105 pcc->bfd_mach = bfd_mach_ppc_750;
4106 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4107 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4108}
4109
4110static void init_proc_7400(CPUPPCState *env)
4111{
4112 register_non_embedded_sprs(env);
4113 register_sdr1_sprs(env);
4114 register_74xx_sprs(env);
4115 vscr_init(env, 0x00010000);
4116
4117 spr_register(env, SPR_UBAMR, "UBAMR",
4118 &spr_read_ureg, SPR_NOACCESS,
4119 &spr_read_ureg, SPR_NOACCESS,
4120 0x00000000);
4121
4122 spr_register(env, SPR_MSSCR1, "MSSCR1",
4123 SPR_NOACCESS, SPR_NOACCESS,
4124 &spr_read_generic, &spr_write_generic,
4125 0x00000000);
4126
4127 register_thrm_sprs(env);
4128
4129 register_low_BATs(env);
4130 init_excp_7400(env);
4131 env->dcache_line_size = 32;
4132 env->icache_line_size = 32;
4133
4134 ppc6xx_irq_init(env_archcpu(env));
4135}
4136
4137POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
4138{
4139 DeviceClass *dc = DEVICE_CLASS(oc);
4140 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4141
4142 dc->desc = "PowerPC 7400 (aka G4)";
4143 pcc->init_proc = init_proc_7400;
4144 pcc->check_pow = check_pow_hid0;
4145 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4146 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4147 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4148 PPC_FLOAT_STFIWX |
4149 PPC_CACHE | PPC_CACHE_ICBI |
4150 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4151 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4152 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4153 PPC_MEM_TLBIA |
4154 PPC_SEGMENT | PPC_EXTERN |
4155 PPC_ALTIVEC;
4156 pcc->msr_mask = (1ull << MSR_VR) |
4157 (1ull << MSR_POW) |
4158 (1ull << MSR_ILE) |
4159 (1ull << MSR_EE) |
4160 (1ull << MSR_PR) |
4161 (1ull << MSR_FP) |
4162 (1ull << MSR_ME) |
4163 (1ull << MSR_FE0) |
4164 (1ull << MSR_SE) |
4165 (1ull << MSR_DE) |
4166 (1ull << MSR_FE1) |
4167 (1ull << MSR_EP) |
4168 (1ull << MSR_IR) |
4169 (1ull << MSR_DR) |
4170 (1ull << MSR_PMM) |
4171 (1ull << MSR_RI) |
4172 (1ull << MSR_LE);
4173 pcc->mmu_model = POWERPC_MMU_32B;
4174 pcc->excp_model = POWERPC_EXCP_74xx;
4175 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4176 pcc->bfd_mach = bfd_mach_ppc_7400;
4177 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4178 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4179 POWERPC_FLAG_BUS_CLK;
4180}
4181
4182static void init_proc_7410(CPUPPCState *env)
4183{
4184 register_non_embedded_sprs(env);
4185 register_sdr1_sprs(env);
4186 register_74xx_sprs(env);
4187 vscr_init(env, 0x00010000);
4188
4189 spr_register(env, SPR_UBAMR, "UBAMR",
4190 &spr_read_ureg, SPR_NOACCESS,
4191 &spr_read_ureg, SPR_NOACCESS,
4192 0x00000000);
4193
4194 register_thrm_sprs(env);
4195
4196
4197 spr_register(env, SPR_L2PMCR, "L2PMCR",
4198 SPR_NOACCESS, SPR_NOACCESS,
4199 &spr_read_generic, &spr_write_generic,
4200 0x00000000);
4201
4202
4203 spr_register(env, SPR_LDSTDB, "LDSTDB",
4204 SPR_NOACCESS, SPR_NOACCESS,
4205 &spr_read_generic, &spr_write_generic,
4206 0x00000000);
4207
4208 register_low_BATs(env);
4209 init_excp_7400(env);
4210 env->dcache_line_size = 32;
4211 env->icache_line_size = 32;
4212
4213 ppc6xx_irq_init(env_archcpu(env));
4214}
4215
4216POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
4217{
4218 DeviceClass *dc = DEVICE_CLASS(oc);
4219 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4220
4221 dc->desc = "PowerPC 7410 (aka G4)";
4222 pcc->init_proc = init_proc_7410;
4223 pcc->check_pow = check_pow_hid0;
4224 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4225 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4226 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4227 PPC_FLOAT_STFIWX |
4228 PPC_CACHE | PPC_CACHE_ICBI |
4229 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4230 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4231 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4232 PPC_MEM_TLBIA |
4233 PPC_SEGMENT | PPC_EXTERN |
4234 PPC_ALTIVEC;
4235 pcc->msr_mask = (1ull << MSR_VR) |
4236 (1ull << MSR_POW) |
4237 (1ull << MSR_ILE) |
4238 (1ull << MSR_EE) |
4239 (1ull << MSR_PR) |
4240 (1ull << MSR_FP) |
4241 (1ull << MSR_ME) |
4242 (1ull << MSR_FE0) |
4243 (1ull << MSR_SE) |
4244 (1ull << MSR_DE) |
4245 (1ull << MSR_FE1) |
4246 (1ull << MSR_EP) |
4247 (1ull << MSR_IR) |
4248 (1ull << MSR_DR) |
4249 (1ull << MSR_PMM) |
4250 (1ull << MSR_RI) |
4251 (1ull << MSR_LE);
4252 pcc->mmu_model = POWERPC_MMU_32B;
4253 pcc->excp_model = POWERPC_EXCP_74xx;
4254 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4255 pcc->bfd_mach = bfd_mach_ppc_7400;
4256 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4257 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4258 POWERPC_FLAG_BUS_CLK;
4259}
4260
4261static void init_proc_7440(CPUPPCState *env)
4262{
4263 register_non_embedded_sprs(env);
4264 register_sdr1_sprs(env);
4265 register_74xx_sprs(env);
4266 vscr_init(env, 0x00010000);
4267
4268 spr_register(env, SPR_UBAMR, "UBAMR",
4269 &spr_read_ureg, SPR_NOACCESS,
4270 &spr_read_ureg, SPR_NOACCESS,
4271 0x00000000);
4272
4273 spr_register(env, SPR_LDSTCR, "LDSTCR",
4274 SPR_NOACCESS, SPR_NOACCESS,
4275 &spr_read_generic, &spr_write_generic,
4276 0x00000000);
4277
4278 spr_register(env, SPR_ICTRL, "ICTRL",
4279 SPR_NOACCESS, SPR_NOACCESS,
4280 &spr_read_generic, &spr_write_generic,
4281 0x00000000);
4282
4283 spr_register(env, SPR_MSSSR0, "MSSSR0",
4284 SPR_NOACCESS, SPR_NOACCESS,
4285 &spr_read_generic, &spr_write_generic,
4286 0x00000000);
4287
4288 spr_register(env, SPR_7XX_PMC5, "PMC5",
4289 SPR_NOACCESS, SPR_NOACCESS,
4290 &spr_read_generic, &spr_write_generic,
4291 0x00000000);
4292
4293 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4294 &spr_read_ureg, SPR_NOACCESS,
4295 &spr_read_ureg, SPR_NOACCESS,
4296 0x00000000);
4297
4298 spr_register(env, SPR_7XX_PMC6, "PMC6",
4299 SPR_NOACCESS, SPR_NOACCESS,
4300 &spr_read_generic, &spr_write_generic,
4301 0x00000000);
4302
4303 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4304 &spr_read_ureg, SPR_NOACCESS,
4305 &spr_read_ureg, SPR_NOACCESS,
4306 0x00000000);
4307
4308 register_low_BATs(env);
4309 init_excp_7450(env);
4310 env->dcache_line_size = 32;
4311 env->icache_line_size = 32;
4312
4313 ppc6xx_irq_init(env_archcpu(env));
4314}
4315
4316POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
4317{
4318 DeviceClass *dc = DEVICE_CLASS(oc);
4319 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4320
4321 dc->desc = "PowerPC 7440 (aka G4)";
4322 pcc->init_proc = init_proc_7440;
4323 pcc->check_pow = check_pow_hid0_74xx;
4324 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4325 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4326 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4327 PPC_FLOAT_STFIWX |
4328 PPC_CACHE | PPC_CACHE_ICBI |
4329 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4330 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4331 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4332 PPC_MEM_TLBIA |
4333 PPC_SEGMENT | PPC_EXTERN |
4334 PPC_ALTIVEC;
4335 pcc->msr_mask = (1ull << MSR_VR) |
4336 (1ull << MSR_POW) |
4337 (1ull << MSR_ILE) |
4338 (1ull << MSR_EE) |
4339 (1ull << MSR_PR) |
4340 (1ull << MSR_FP) |
4341 (1ull << MSR_ME) |
4342 (1ull << MSR_FE0) |
4343 (1ull << MSR_SE) |
4344 (1ull << MSR_DE) |
4345 (1ull << MSR_FE1) |
4346 (1ull << MSR_EP) |
4347 (1ull << MSR_IR) |
4348 (1ull << MSR_DR) |
4349 (1ull << MSR_PMM) |
4350 (1ull << MSR_RI) |
4351 (1ull << MSR_LE);
4352 pcc->mmu_model = POWERPC_MMU_32B;
4353 pcc->excp_model = POWERPC_EXCP_74xx;
4354 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4355 pcc->bfd_mach = bfd_mach_ppc_7400;
4356 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4357 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4358 POWERPC_FLAG_BUS_CLK;
4359}
4360
4361static void init_proc_7450(CPUPPCState *env)
4362{
4363 register_non_embedded_sprs(env);
4364 register_sdr1_sprs(env);
4365 register_74xx_sprs(env);
4366 vscr_init(env, 0x00010000);
4367
4368 register_l3_ctrl(env);
4369
4370 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4371 SPR_NOACCESS, SPR_NOACCESS,
4372 &spr_read_generic, &spr_write_generic,
4373 0x00000000);
4374
4375 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4376 SPR_NOACCESS, SPR_NOACCESS,
4377 &spr_read_generic, &spr_write_generic,
4378 0x00000000);
4379
4380 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4381 SPR_NOACCESS, SPR_NOACCESS,
4382 &spr_read_generic, &spr_write_generic,
4383 0x00000000);
4384
4385 spr_register(env, SPR_L3OHCR, "L3OHCR",
4386 SPR_NOACCESS, SPR_NOACCESS,
4387 &spr_read_generic, &spr_write_generic,
4388 0x00000000);
4389
4390 spr_register(env, SPR_UBAMR, "UBAMR",
4391 &spr_read_ureg, SPR_NOACCESS,
4392 &spr_read_ureg, SPR_NOACCESS,
4393 0x00000000);
4394
4395 spr_register(env, SPR_LDSTCR, "LDSTCR",
4396 SPR_NOACCESS, SPR_NOACCESS,
4397 &spr_read_generic, &spr_write_generic,
4398 0x00000000);
4399
4400 spr_register(env, SPR_ICTRL, "ICTRL",
4401 SPR_NOACCESS, SPR_NOACCESS,
4402 &spr_read_generic, &spr_write_generic,
4403 0x00000000);
4404
4405 spr_register(env, SPR_MSSSR0, "MSSSR0",
4406 SPR_NOACCESS, SPR_NOACCESS,
4407 &spr_read_generic, &spr_write_generic,
4408 0x00000000);
4409
4410 spr_register(env, SPR_7XX_PMC5, "PMC5",
4411 SPR_NOACCESS, SPR_NOACCESS,
4412 &spr_read_generic, &spr_write_generic,
4413 0x00000000);
4414
4415 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4416 &spr_read_ureg, SPR_NOACCESS,
4417 &spr_read_ureg, SPR_NOACCESS,
4418 0x00000000);
4419
4420 spr_register(env, SPR_7XX_PMC6, "PMC6",
4421 SPR_NOACCESS, SPR_NOACCESS,
4422 &spr_read_generic, &spr_write_generic,
4423 0x00000000);
4424
4425 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4426 &spr_read_ureg, SPR_NOACCESS,
4427 &spr_read_ureg, SPR_NOACCESS,
4428 0x00000000);
4429
4430 register_low_BATs(env);
4431 init_excp_7450(env);
4432 env->dcache_line_size = 32;
4433 env->icache_line_size = 32;
4434
4435 ppc6xx_irq_init(env_archcpu(env));
4436}
4437
4438POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
4439{
4440 DeviceClass *dc = DEVICE_CLASS(oc);
4441 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4442
4443 dc->desc = "PowerPC 7450 (aka G4)";
4444 pcc->init_proc = init_proc_7450;
4445 pcc->check_pow = check_pow_hid0_74xx;
4446 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4447 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4448 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4449 PPC_FLOAT_STFIWX |
4450 PPC_CACHE | PPC_CACHE_ICBI |
4451 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4452 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4453 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4454 PPC_MEM_TLBIA |
4455 PPC_SEGMENT | PPC_EXTERN |
4456 PPC_ALTIVEC;
4457 pcc->msr_mask = (1ull << MSR_VR) |
4458 (1ull << MSR_POW) |
4459 (1ull << MSR_ILE) |
4460 (1ull << MSR_EE) |
4461 (1ull << MSR_PR) |
4462 (1ull << MSR_FP) |
4463 (1ull << MSR_ME) |
4464 (1ull << MSR_FE0) |
4465 (1ull << MSR_SE) |
4466 (1ull << MSR_DE) |
4467 (1ull << MSR_FE1) |
4468 (1ull << MSR_EP) |
4469 (1ull << MSR_IR) |
4470 (1ull << MSR_DR) |
4471 (1ull << MSR_PMM) |
4472 (1ull << MSR_RI) |
4473 (1ull << MSR_LE);
4474 pcc->mmu_model = POWERPC_MMU_32B;
4475 pcc->excp_model = POWERPC_EXCP_74xx;
4476 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4477 pcc->bfd_mach = bfd_mach_ppc_7400;
4478 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4479 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4480 POWERPC_FLAG_BUS_CLK;
4481}
4482
4483static void init_proc_7445(CPUPPCState *env)
4484{
4485 register_non_embedded_sprs(env);
4486 register_sdr1_sprs(env);
4487 register_74xx_sprs(env);
4488 vscr_init(env, 0x00010000);
4489
4490 spr_register(env, SPR_LDSTCR, "LDSTCR",
4491 SPR_NOACCESS, SPR_NOACCESS,
4492 &spr_read_generic, &spr_write_generic,
4493 0x00000000);
4494
4495 spr_register(env, SPR_ICTRL, "ICTRL",
4496 SPR_NOACCESS, SPR_NOACCESS,
4497 &spr_read_generic, &spr_write_generic,
4498 0x00000000);
4499
4500 spr_register(env, SPR_MSSSR0, "MSSSR0",
4501 SPR_NOACCESS, SPR_NOACCESS,
4502 &spr_read_generic, &spr_write_generic,
4503 0x00000000);
4504
4505 spr_register(env, SPR_7XX_PMC5, "PMC5",
4506 SPR_NOACCESS, SPR_NOACCESS,
4507 &spr_read_generic, &spr_write_generic,
4508 0x00000000);
4509
4510 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4511 &spr_read_ureg, SPR_NOACCESS,
4512 &spr_read_ureg, SPR_NOACCESS,
4513 0x00000000);
4514
4515 spr_register(env, SPR_7XX_PMC6, "PMC6",
4516 SPR_NOACCESS, SPR_NOACCESS,
4517 &spr_read_generic, &spr_write_generic,
4518 0x00000000);
4519
4520 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4521 &spr_read_ureg, SPR_NOACCESS,
4522 &spr_read_ureg, SPR_NOACCESS,
4523 0x00000000);
4524
4525 spr_register(env, SPR_SPRG4, "SPRG4",
4526 SPR_NOACCESS, SPR_NOACCESS,
4527 &spr_read_generic, &spr_write_generic,
4528 0x00000000);
4529 spr_register(env, SPR_USPRG4, "USPRG4",
4530 &spr_read_ureg, SPR_NOACCESS,
4531 &spr_read_ureg, SPR_NOACCESS,
4532 0x00000000);
4533 spr_register(env, SPR_SPRG5, "SPRG5",
4534 SPR_NOACCESS, SPR_NOACCESS,
4535 &spr_read_generic, &spr_write_generic,
4536 0x00000000);
4537 spr_register(env, SPR_USPRG5, "USPRG5",
4538 &spr_read_ureg, SPR_NOACCESS,
4539 &spr_read_ureg, SPR_NOACCESS,
4540 0x00000000);
4541 spr_register(env, SPR_SPRG6, "SPRG6",
4542 SPR_NOACCESS, SPR_NOACCESS,
4543 &spr_read_generic, &spr_write_generic,
4544 0x00000000);
4545 spr_register(env, SPR_USPRG6, "USPRG6",
4546 &spr_read_ureg, SPR_NOACCESS,
4547 &spr_read_ureg, SPR_NOACCESS,
4548 0x00000000);
4549 spr_register(env, SPR_SPRG7, "SPRG7",
4550 SPR_NOACCESS, SPR_NOACCESS,
4551 &spr_read_generic, &spr_write_generic,
4552 0x00000000);
4553 spr_register(env, SPR_USPRG7, "USPRG7",
4554 &spr_read_ureg, SPR_NOACCESS,
4555 &spr_read_ureg, SPR_NOACCESS,
4556 0x00000000);
4557
4558 register_low_BATs(env);
4559 register_high_BATs(env);
4560 init_excp_7450(env);
4561 env->dcache_line_size = 32;
4562 env->icache_line_size = 32;
4563
4564 ppc6xx_irq_init(env_archcpu(env));
4565}
4566
4567POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
4568{
4569 DeviceClass *dc = DEVICE_CLASS(oc);
4570 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4571
4572 dc->desc = "PowerPC 7445 (aka G4)";
4573 pcc->init_proc = init_proc_7445;
4574 pcc->check_pow = check_pow_hid0_74xx;
4575 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4576 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4577 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4578 PPC_FLOAT_STFIWX |
4579 PPC_CACHE | PPC_CACHE_ICBI |
4580 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4581 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4582 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4583 PPC_MEM_TLBIA |
4584 PPC_SEGMENT | PPC_EXTERN |
4585 PPC_ALTIVEC;
4586 pcc->msr_mask = (1ull << MSR_VR) |
4587 (1ull << MSR_POW) |
4588 (1ull << MSR_ILE) |
4589 (1ull << MSR_EE) |
4590 (1ull << MSR_PR) |
4591 (1ull << MSR_FP) |
4592 (1ull << MSR_ME) |
4593 (1ull << MSR_FE0) |
4594 (1ull << MSR_SE) |
4595 (1ull << MSR_DE) |
4596 (1ull << MSR_FE1) |
4597 (1ull << MSR_EP) |
4598 (1ull << MSR_IR) |
4599 (1ull << MSR_DR) |
4600 (1ull << MSR_PMM) |
4601 (1ull << MSR_RI) |
4602 (1ull << MSR_LE);
4603 pcc->mmu_model = POWERPC_MMU_32B;
4604 pcc->excp_model = POWERPC_EXCP_74xx;
4605 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4606 pcc->bfd_mach = bfd_mach_ppc_7400;
4607 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4608 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4609 POWERPC_FLAG_BUS_CLK;
4610}
4611
4612static void init_proc_7455(CPUPPCState *env)
4613{
4614 register_non_embedded_sprs(env);
4615 register_sdr1_sprs(env);
4616 register_74xx_sprs(env);
4617 vscr_init(env, 0x00010000);
4618
4619 register_l3_ctrl(env);
4620
4621 spr_register(env, SPR_LDSTCR, "LDSTCR",
4622 SPR_NOACCESS, SPR_NOACCESS,
4623 &spr_read_generic, &spr_write_generic,
4624 0x00000000);
4625
4626 spr_register(env, SPR_ICTRL, "ICTRL",
4627 SPR_NOACCESS, SPR_NOACCESS,
4628 &spr_read_generic, &spr_write_generic,
4629 0x00000000);
4630
4631 spr_register(env, SPR_MSSSR0, "MSSSR0",
4632 SPR_NOACCESS, SPR_NOACCESS,
4633 &spr_read_generic, &spr_write_generic,
4634 0x00000000);
4635
4636 spr_register(env, SPR_7XX_PMC5, "PMC5",
4637 SPR_NOACCESS, SPR_NOACCESS,
4638 &spr_read_generic, &spr_write_generic,
4639 0x00000000);
4640
4641 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4642 &spr_read_ureg, SPR_NOACCESS,
4643 &spr_read_ureg, SPR_NOACCESS,
4644 0x00000000);
4645
4646 spr_register(env, SPR_7XX_PMC6, "PMC6",
4647 SPR_NOACCESS, SPR_NOACCESS,
4648 &spr_read_generic, &spr_write_generic,
4649 0x00000000);
4650
4651 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4652 &spr_read_ureg, SPR_NOACCESS,
4653 &spr_read_ureg, SPR_NOACCESS,
4654 0x00000000);
4655
4656 spr_register(env, SPR_SPRG4, "SPRG4",
4657 SPR_NOACCESS, SPR_NOACCESS,
4658 &spr_read_generic, &spr_write_generic,
4659 0x00000000);
4660 spr_register(env, SPR_USPRG4, "USPRG4",
4661 &spr_read_ureg, SPR_NOACCESS,
4662 &spr_read_ureg, SPR_NOACCESS,
4663 0x00000000);
4664 spr_register(env, SPR_SPRG5, "SPRG5",
4665 SPR_NOACCESS, SPR_NOACCESS,
4666 &spr_read_generic, &spr_write_generic,
4667 0x00000000);
4668 spr_register(env, SPR_USPRG5, "USPRG5",
4669 &spr_read_ureg, SPR_NOACCESS,
4670 &spr_read_ureg, SPR_NOACCESS,
4671 0x00000000);
4672 spr_register(env, SPR_SPRG6, "SPRG6",
4673 SPR_NOACCESS, SPR_NOACCESS,
4674 &spr_read_generic, &spr_write_generic,
4675 0x00000000);
4676 spr_register(env, SPR_USPRG6, "USPRG6",
4677 &spr_read_ureg, SPR_NOACCESS,
4678 &spr_read_ureg, SPR_NOACCESS,
4679 0x00000000);
4680 spr_register(env, SPR_SPRG7, "SPRG7",
4681 SPR_NOACCESS, SPR_NOACCESS,
4682 &spr_read_generic, &spr_write_generic,
4683 0x00000000);
4684 spr_register(env, SPR_USPRG7, "USPRG7",
4685 &spr_read_ureg, SPR_NOACCESS,
4686 &spr_read_ureg, SPR_NOACCESS,
4687 0x00000000);
4688
4689 register_low_BATs(env);
4690 register_high_BATs(env);
4691 init_excp_7450(env);
4692 env->dcache_line_size = 32;
4693 env->icache_line_size = 32;
4694
4695 ppc6xx_irq_init(env_archcpu(env));
4696}
4697
4698POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
4699{
4700 DeviceClass *dc = DEVICE_CLASS(oc);
4701 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4702
4703 dc->desc = "PowerPC 7455 (aka G4)";
4704 pcc->init_proc = init_proc_7455;
4705 pcc->check_pow = check_pow_hid0_74xx;
4706 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4707 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4708 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4709 PPC_FLOAT_STFIWX |
4710 PPC_CACHE | PPC_CACHE_ICBI |
4711 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4712 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4713 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4714 PPC_MEM_TLBIA |
4715 PPC_SEGMENT | PPC_EXTERN |
4716 PPC_ALTIVEC;
4717 pcc->msr_mask = (1ull << MSR_VR) |
4718 (1ull << MSR_POW) |
4719 (1ull << MSR_ILE) |
4720 (1ull << MSR_EE) |
4721 (1ull << MSR_PR) |
4722 (1ull << MSR_FP) |
4723 (1ull << MSR_ME) |
4724 (1ull << MSR_FE0) |
4725 (1ull << MSR_SE) |
4726 (1ull << MSR_DE) |
4727 (1ull << MSR_FE1) |
4728 (1ull << MSR_EP) |
4729 (1ull << MSR_IR) |
4730 (1ull << MSR_DR) |
4731 (1ull << MSR_PMM) |
4732 (1ull << MSR_RI) |
4733 (1ull << MSR_LE);
4734 pcc->mmu_model = POWERPC_MMU_32B;
4735 pcc->excp_model = POWERPC_EXCP_74xx;
4736 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4737 pcc->bfd_mach = bfd_mach_ppc_7400;
4738 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4739 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4740 POWERPC_FLAG_BUS_CLK;
4741}
4742
4743static void init_proc_7457(CPUPPCState *env)
4744{
4745 register_non_embedded_sprs(env);
4746 register_sdr1_sprs(env);
4747 register_74xx_sprs(env);
4748 vscr_init(env, 0x00010000);
4749
4750 register_l3_ctrl(env);
4751
4752 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4753 SPR_NOACCESS, SPR_NOACCESS,
4754 &spr_read_generic, &spr_write_generic,
4755 0x00000000);
4756
4757 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4758 SPR_NOACCESS, SPR_NOACCESS,
4759 &spr_read_generic, &spr_write_generic,
4760 0x00000000);
4761
4762 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4763 SPR_NOACCESS, SPR_NOACCESS,
4764 &spr_read_generic, &spr_write_generic,
4765 0x00000000);
4766
4767 spr_register(env, SPR_L3OHCR, "L3OHCR",
4768 SPR_NOACCESS, SPR_NOACCESS,
4769 &spr_read_generic, &spr_write_generic,
4770 0x00000000);
4771
4772 spr_register(env, SPR_LDSTCR, "LDSTCR",
4773 SPR_NOACCESS, SPR_NOACCESS,
4774 &spr_read_generic, &spr_write_generic,
4775 0x00000000);
4776
4777 spr_register(env, SPR_ICTRL, "ICTRL",
4778 SPR_NOACCESS, SPR_NOACCESS,
4779 &spr_read_generic, &spr_write_generic,
4780 0x00000000);
4781
4782 spr_register(env, SPR_MSSSR0, "MSSSR0",
4783 SPR_NOACCESS, SPR_NOACCESS,
4784 &spr_read_generic, &spr_write_generic,
4785 0x00000000);
4786
4787 spr_register(env, SPR_7XX_PMC5, "PMC5",
4788 SPR_NOACCESS, SPR_NOACCESS,
4789 &spr_read_generic, &spr_write_generic,
4790 0x00000000);
4791
4792 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4793 &spr_read_ureg, SPR_NOACCESS,
4794 &spr_read_ureg, SPR_NOACCESS,
4795 0x00000000);
4796
4797 spr_register(env, SPR_7XX_PMC6, "PMC6",
4798 SPR_NOACCESS, SPR_NOACCESS,
4799 &spr_read_generic, &spr_write_generic,
4800 0x00000000);
4801
4802 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4803 &spr_read_ureg, SPR_NOACCESS,
4804 &spr_read_ureg, SPR_NOACCESS,
4805 0x00000000);
4806
4807 spr_register(env, SPR_SPRG4, "SPRG4",
4808 SPR_NOACCESS, SPR_NOACCESS,
4809 &spr_read_generic, &spr_write_generic,
4810 0x00000000);
4811 spr_register(env, SPR_USPRG4, "USPRG4",
4812 &spr_read_ureg, SPR_NOACCESS,
4813 &spr_read_ureg, SPR_NOACCESS,
4814 0x00000000);
4815 spr_register(env, SPR_SPRG5, "SPRG5",
4816 SPR_NOACCESS, SPR_NOACCESS,
4817 &spr_read_generic, &spr_write_generic,
4818 0x00000000);
4819 spr_register(env, SPR_USPRG5, "USPRG5",
4820 &spr_read_ureg, SPR_NOACCESS,
4821 &spr_read_ureg, SPR_NOACCESS,
4822 0x00000000);
4823 spr_register(env, SPR_SPRG6, "SPRG6",
4824 SPR_NOACCESS, SPR_NOACCESS,
4825 &spr_read_generic, &spr_write_generic,
4826 0x00000000);
4827 spr_register(env, SPR_USPRG6, "USPRG6",
4828 &spr_read_ureg, SPR_NOACCESS,
4829 &spr_read_ureg, SPR_NOACCESS,
4830 0x00000000);
4831 spr_register(env, SPR_SPRG7, "SPRG7",
4832 SPR_NOACCESS, SPR_NOACCESS,
4833 &spr_read_generic, &spr_write_generic,
4834 0x00000000);
4835 spr_register(env, SPR_USPRG7, "USPRG7",
4836 &spr_read_ureg, SPR_NOACCESS,
4837 &spr_read_ureg, SPR_NOACCESS,
4838 0x00000000);
4839
4840 register_low_BATs(env);
4841 register_high_BATs(env);
4842 init_excp_7450(env);
4843 env->dcache_line_size = 32;
4844 env->icache_line_size = 32;
4845
4846 ppc6xx_irq_init(env_archcpu(env));
4847}
4848
4849POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
4850{
4851 DeviceClass *dc = DEVICE_CLASS(oc);
4852 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4853
4854 dc->desc = "PowerPC 7457 (aka G4)";
4855 pcc->init_proc = init_proc_7457;
4856 pcc->check_pow = check_pow_hid0_74xx;
4857 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4858 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4859 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4860 PPC_FLOAT_STFIWX |
4861 PPC_CACHE | PPC_CACHE_ICBI |
4862 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4863 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4864 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4865 PPC_MEM_TLBIA |
4866 PPC_SEGMENT | PPC_EXTERN |
4867 PPC_ALTIVEC;
4868 pcc->msr_mask = (1ull << MSR_VR) |
4869 (1ull << MSR_POW) |
4870 (1ull << MSR_ILE) |
4871 (1ull << MSR_EE) |
4872 (1ull << MSR_PR) |
4873 (1ull << MSR_FP) |
4874 (1ull << MSR_ME) |
4875 (1ull << MSR_FE0) |
4876 (1ull << MSR_SE) |
4877 (1ull << MSR_DE) |
4878 (1ull << MSR_FE1) |
4879 (1ull << MSR_EP) |
4880 (1ull << MSR_IR) |
4881 (1ull << MSR_DR) |
4882 (1ull << MSR_PMM) |
4883 (1ull << MSR_RI) |
4884 (1ull << MSR_LE);
4885 pcc->mmu_model = POWERPC_MMU_32B;
4886 pcc->excp_model = POWERPC_EXCP_74xx;
4887 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4888 pcc->bfd_mach = bfd_mach_ppc_7400;
4889 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4890 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4891 POWERPC_FLAG_BUS_CLK;
4892}
4893
4894static void init_proc_e600(CPUPPCState *env)
4895{
4896 register_non_embedded_sprs(env);
4897 register_sdr1_sprs(env);
4898 register_74xx_sprs(env);
4899 vscr_init(env, 0x00010000);
4900
4901 spr_register(env, SPR_UBAMR, "UBAMR",
4902 &spr_read_ureg, SPR_NOACCESS,
4903 &spr_read_ureg, SPR_NOACCESS,
4904 0x00000000);
4905
4906 spr_register(env, SPR_LDSTCR, "LDSTCR",
4907 SPR_NOACCESS, SPR_NOACCESS,
4908 &spr_read_generic, &spr_write_generic,
4909 0x00000000);
4910
4911 spr_register(env, SPR_ICTRL, "ICTRL",
4912 SPR_NOACCESS, SPR_NOACCESS,
4913 &spr_read_generic, &spr_write_generic,
4914 0x00000000);
4915
4916 spr_register(env, SPR_MSSSR0, "MSSSR0",
4917 SPR_NOACCESS, SPR_NOACCESS,
4918 &spr_read_generic, &spr_write_generic,
4919 0x00000000);
4920
4921 spr_register(env, SPR_7XX_PMC5, "PMC5",
4922 SPR_NOACCESS, SPR_NOACCESS,
4923 &spr_read_generic, &spr_write_generic,
4924 0x00000000);
4925
4926 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4927 &spr_read_ureg, SPR_NOACCESS,
4928 &spr_read_ureg, SPR_NOACCESS,
4929 0x00000000);
4930
4931 spr_register(env, SPR_7XX_PMC6, "PMC6",
4932 SPR_NOACCESS, SPR_NOACCESS,
4933 &spr_read_generic, &spr_write_generic,
4934 0x00000000);
4935
4936 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4937 &spr_read_ureg, SPR_NOACCESS,
4938 &spr_read_ureg, SPR_NOACCESS,
4939 0x00000000);
4940
4941 spr_register(env, SPR_SPRG4, "SPRG4",
4942 SPR_NOACCESS, SPR_NOACCESS,
4943 &spr_read_generic, &spr_write_generic,
4944 0x00000000);
4945 spr_register(env, SPR_USPRG4, "USPRG4",
4946 &spr_read_ureg, SPR_NOACCESS,
4947 &spr_read_ureg, SPR_NOACCESS,
4948 0x00000000);
4949 spr_register(env, SPR_SPRG5, "SPRG5",
4950 SPR_NOACCESS, SPR_NOACCESS,
4951 &spr_read_generic, &spr_write_generic,
4952 0x00000000);
4953 spr_register(env, SPR_USPRG5, "USPRG5",
4954 &spr_read_ureg, SPR_NOACCESS,
4955 &spr_read_ureg, SPR_NOACCESS,
4956 0x00000000);
4957 spr_register(env, SPR_SPRG6, "SPRG6",
4958 SPR_NOACCESS, SPR_NOACCESS,
4959 &spr_read_generic, &spr_write_generic,
4960 0x00000000);
4961 spr_register(env, SPR_USPRG6, "USPRG6",
4962 &spr_read_ureg, SPR_NOACCESS,
4963 &spr_read_ureg, SPR_NOACCESS,
4964 0x00000000);
4965 spr_register(env, SPR_SPRG7, "SPRG7",
4966 SPR_NOACCESS, SPR_NOACCESS,
4967 &spr_read_generic, &spr_write_generic,
4968 0x00000000);
4969 spr_register(env, SPR_USPRG7, "USPRG7",
4970 &spr_read_ureg, SPR_NOACCESS,
4971 &spr_read_ureg, SPR_NOACCESS,
4972 0x00000000);
4973
4974 register_low_BATs(env);
4975 register_high_BATs(env);
4976 init_excp_7450(env);
4977 env->dcache_line_size = 32;
4978 env->icache_line_size = 32;
4979
4980 ppc6xx_irq_init(env_archcpu(env));
4981}
4982
4983POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
4984{
4985 DeviceClass *dc = DEVICE_CLASS(oc);
4986 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4987
4988 dc->desc = "PowerPC e600";
4989 pcc->init_proc = init_proc_e600;
4990 pcc->check_pow = check_pow_hid0_74xx;
4991 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4992 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4993 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4994 PPC_FLOAT_STFIWX |
4995 PPC_CACHE | PPC_CACHE_ICBI |
4996 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4997 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4998 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4999 PPC_MEM_TLBIA |
5000 PPC_SEGMENT | PPC_EXTERN |
5001 PPC_ALTIVEC;
5002 pcc->insns_flags2 = PPC_NONE;
5003 pcc->msr_mask = (1ull << MSR_VR) |
5004 (1ull << MSR_POW) |
5005 (1ull << MSR_ILE) |
5006 (1ull << MSR_EE) |
5007 (1ull << MSR_PR) |
5008 (1ull << MSR_FP) |
5009 (1ull << MSR_ME) |
5010 (1ull << MSR_FE0) |
5011 (1ull << MSR_SE) |
5012 (1ull << MSR_DE) |
5013 (1ull << MSR_FE1) |
5014 (1ull << MSR_EP) |
5015 (1ull << MSR_IR) |
5016 (1ull << MSR_DR) |
5017 (1ull << MSR_PMM) |
5018 (1ull << MSR_RI) |
5019 (1ull << MSR_LE);
5020 pcc->mmu_model = POWERPC_MMU_32B;
5021 pcc->excp_model = POWERPC_EXCP_74xx;
5022 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5023 pcc->bfd_mach = bfd_mach_ppc_7400;
5024 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5025 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5026 POWERPC_FLAG_BUS_CLK;
5027}
5028
5029#if defined(TARGET_PPC64)
5030#if defined(CONFIG_USER_ONLY)
5031#define POWERPC970_HID5_INIT 0x00000080
5032#else
5033#define POWERPC970_HID5_INIT 0x00000000
5034#endif
5035
5036static int check_pow_970(CPUPPCState *env)
5037{
5038 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
5039 return 1;
5040 }
5041
5042 return 0;
5043}
5044
5045static void register_970_hid_sprs(CPUPPCState *env)
5046{
5047
5048 spr_register(env, SPR_HID0, "HID0",
5049 SPR_NOACCESS, SPR_NOACCESS,
5050 &spr_read_generic, &spr_write_clear,
5051 0x60000000);
5052 spr_register(env, SPR_HID1, "HID1",
5053 SPR_NOACCESS, SPR_NOACCESS,
5054 &spr_read_generic, &spr_write_generic,
5055 0x00000000);
5056 spr_register(env, SPR_970_HID5, "HID5",
5057 SPR_NOACCESS, SPR_NOACCESS,
5058 &spr_read_generic, &spr_write_generic,
5059 POWERPC970_HID5_INIT);
5060}
5061
5062static void register_970_hior_sprs(CPUPPCState *env)
5063{
5064 spr_register(env, SPR_HIOR, "SPR_HIOR",
5065 SPR_NOACCESS, SPR_NOACCESS,
5066 &spr_read_hior, &spr_write_hior,
5067 0x00000000);
5068}
5069
5070static void register_book3s_ctrl_sprs(CPUPPCState *env)
5071{
5072 spr_register(env, SPR_CTRL, "SPR_CTRL",
5073 SPR_NOACCESS, SPR_NOACCESS,
5074 SPR_NOACCESS, &spr_write_CTRL,
5075 0x00000000);
5076 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
5077 &spr_read_ureg, SPR_NOACCESS,
5078 &spr_read_ureg, SPR_NOACCESS,
5079 0x00000000);
5080}
5081
5082static void register_book3s_altivec_sprs(CPUPPCState *env)
5083{
5084 if (!(env->insns_flags & PPC_ALTIVEC)) {
5085 return;
5086 }
5087
5088 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
5089 &spr_read_generic, &spr_write_generic,
5090 &spr_read_generic, &spr_write_generic,
5091 KVM_REG_PPC_VRSAVE, 0x00000000);
5092
5093}
5094
5095static void register_book3s_dbg_sprs(CPUPPCState *env)
5096{
5097
5098
5099
5100
5101
5102
5103
5104 spr_register_kvm(env, SPR_DABR, "DABR",
5105 SPR_NOACCESS, SPR_NOACCESS,
5106 &spr_read_generic, &spr_write_generic,
5107 KVM_REG_PPC_DABR, 0x00000000);
5108 spr_register_kvm(env, SPR_DABRX, "DABRX",
5109 SPR_NOACCESS, SPR_NOACCESS,
5110 &spr_read_generic, &spr_write_generic,
5111 KVM_REG_PPC_DABRX, 0x00000000);
5112}
5113
5114static void register_book3s_207_dbg_sprs(CPUPPCState *env)
5115{
5116 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0",
5117 SPR_NOACCESS, SPR_NOACCESS,
5118 SPR_NOACCESS, SPR_NOACCESS,
5119 &spr_read_generic, &spr_write_generic,
5120 KVM_REG_PPC_DAWR, 0x00000000);
5121 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0",
5122 SPR_NOACCESS, SPR_NOACCESS,
5123 SPR_NOACCESS, SPR_NOACCESS,
5124 &spr_read_generic, &spr_write_generic,
5125 KVM_REG_PPC_DAWRX, 0x00000000);
5126 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
5127 SPR_NOACCESS, SPR_NOACCESS,
5128 SPR_NOACCESS, SPR_NOACCESS,
5129 &spr_read_generic, &spr_write_generic,
5130 KVM_REG_PPC_CIABR, 0x00000000);
5131}
5132
5133static void register_970_dbg_sprs(CPUPPCState *env)
5134{
5135
5136 spr_register(env, SPR_IABR, "IABR",
5137 SPR_NOACCESS, SPR_NOACCESS,
5138 &spr_read_generic, &spr_write_generic,
5139 0x00000000);
5140}
5141
5142static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
5143{
5144 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
5145 SPR_NOACCESS, SPR_NOACCESS,
5146 &spr_read_generic, &spr_write_MMCR0,
5147 KVM_REG_PPC_MMCR0, 0x80000000);
5148 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
5149 SPR_NOACCESS, SPR_NOACCESS,
5150 &spr_read_generic, &spr_write_MMCR1,
5151 KVM_REG_PPC_MMCR1, 0x00000000);
5152 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
5153 SPR_NOACCESS, SPR_NOACCESS,
5154 &spr_read_generic, &spr_write_generic,
5155 KVM_REG_PPC_MMCRA, 0x00000000);
5156 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
5157 SPR_NOACCESS, SPR_NOACCESS,
5158 &spr_read_PMC, &spr_write_PMC,
5159 KVM_REG_PPC_PMC1, 0x00000000);
5160 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
5161 SPR_NOACCESS, SPR_NOACCESS,
5162 &spr_read_PMC, &spr_write_PMC,
5163 KVM_REG_PPC_PMC2, 0x00000000);
5164 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
5165 SPR_NOACCESS, SPR_NOACCESS,
5166 &spr_read_PMC, &spr_write_PMC,
5167 KVM_REG_PPC_PMC3, 0x00000000);
5168 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
5169 SPR_NOACCESS, SPR_NOACCESS,
5170 &spr_read_PMC, &spr_write_PMC,
5171 KVM_REG_PPC_PMC4, 0x00000000);
5172 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
5173 SPR_NOACCESS, SPR_NOACCESS,
5174 &spr_read_PMC, &spr_write_PMC,
5175 KVM_REG_PPC_PMC5, 0x00000000);
5176 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
5177 SPR_NOACCESS, SPR_NOACCESS,
5178 &spr_read_PMC, &spr_write_PMC,
5179 KVM_REG_PPC_PMC6, 0x00000000);
5180 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
5181 SPR_NOACCESS, SPR_NOACCESS,
5182 &spr_read_generic, &spr_write_generic,
5183 KVM_REG_PPC_SIAR, 0x00000000);
5184 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
5185 SPR_NOACCESS, SPR_NOACCESS,
5186 &spr_read_generic, &spr_write_generic,
5187 KVM_REG_PPC_SDAR, 0x00000000);
5188}
5189
5190static void register_book3s_pmu_user_sprs(CPUPPCState *env)
5191{
5192 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
5193 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg,
5194 &spr_read_ureg, &spr_write_ureg,
5195 0x80000000);
5196 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
5197 &spr_read_ureg, SPR_NOACCESS,
5198 &spr_read_ureg, &spr_write_ureg,
5199 0x00000000);
5200 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
5201 &spr_read_ureg, SPR_NOACCESS,
5202 &spr_read_ureg, &spr_write_ureg,
5203 0x00000000);
5204 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
5205 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5206 &spr_read_ureg, &spr_write_ureg,
5207 0x00000000);
5208 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
5209 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5210 &spr_read_ureg, &spr_write_ureg,
5211 0x00000000);
5212 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
5213 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5214 &spr_read_ureg, &spr_write_ureg,
5215 0x00000000);
5216 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
5217 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5218 &spr_read_ureg, &spr_write_ureg,
5219 0x00000000);
5220 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
5221 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5222 &spr_read_ureg, &spr_write_ureg,
5223 0x00000000);
5224 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
5225 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5226 &spr_read_ureg, &spr_write_ureg,
5227 0x00000000);
5228 spr_register(env, SPR_POWER_USIAR, "USIAR",
5229 &spr_read_ureg, SPR_NOACCESS,
5230 &spr_read_ureg, &spr_write_ureg,
5231 0x00000000);
5232 spr_register(env, SPR_POWER_USDAR, "USDAR",
5233 &spr_read_ureg, SPR_NOACCESS,
5234 &spr_read_ureg, &spr_write_ureg,
5235 0x00000000);
5236}
5237
5238static void register_970_pmu_sup_sprs(CPUPPCState *env)
5239{
5240 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
5241 SPR_NOACCESS, SPR_NOACCESS,
5242 &spr_read_generic, &spr_write_generic,
5243 KVM_REG_PPC_PMC7, 0x00000000);
5244 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
5245 SPR_NOACCESS, SPR_NOACCESS,
5246 &spr_read_generic, &spr_write_generic,
5247 KVM_REG_PPC_PMC8, 0x00000000);
5248}
5249
5250static void register_970_pmu_user_sprs(CPUPPCState *env)
5251{
5252 spr_register(env, SPR_970_UPMC7, "UPMC7",
5253 &spr_read_ureg, SPR_NOACCESS,
5254 &spr_read_ureg, &spr_write_ureg,
5255 0x00000000);
5256 spr_register(env, SPR_970_UPMC8, "UPMC8",
5257 &spr_read_ureg, SPR_NOACCESS,
5258 &spr_read_ureg, &spr_write_ureg,
5259 0x00000000);
5260}
5261
5262static void register_power8_pmu_sup_sprs(CPUPPCState *env)
5263{
5264 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
5265 SPR_NOACCESS, SPR_NOACCESS,
5266 &spr_read_generic, &spr_write_generic,
5267 KVM_REG_PPC_MMCR2, 0x00000000);
5268 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
5269 SPR_NOACCESS, SPR_NOACCESS,
5270 &spr_read_generic, &spr_write_generic,
5271 KVM_REG_PPC_MMCRS, 0x00000000);
5272 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
5273 SPR_NOACCESS, SPR_NOACCESS,
5274 &spr_read_generic, &spr_write_generic,
5275 KVM_REG_PPC_SIER, 0x00000000);
5276 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
5277 SPR_NOACCESS, SPR_NOACCESS,
5278 &spr_read_generic, &spr_write_generic,
5279 KVM_REG_PPC_SPMC1, 0x00000000);
5280 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
5281 SPR_NOACCESS, SPR_NOACCESS,
5282 &spr_read_generic, &spr_write_generic,
5283 KVM_REG_PPC_SPMC2, 0x00000000);
5284 spr_register_kvm(env, SPR_TACR, "TACR",
5285 SPR_NOACCESS, SPR_NOACCESS,
5286 &spr_read_generic, &spr_write_generic,
5287 KVM_REG_PPC_TACR, 0x00000000);
5288 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
5289 SPR_NOACCESS, SPR_NOACCESS,
5290 &spr_read_generic, &spr_write_generic,
5291 KVM_REG_PPC_TCSCR, 0x00000000);
5292 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
5293 SPR_NOACCESS, SPR_NOACCESS,
5294 &spr_read_generic, &spr_write_generic,
5295 KVM_REG_PPC_CSIGR, 0x00000000);
5296}
5297
5298static void register_power8_pmu_user_sprs(CPUPPCState *env)
5299{
5300 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
5301 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg,
5302 &spr_read_ureg, &spr_write_ureg,
5303 0x00000000);
5304 spr_register(env, SPR_POWER_USIER, "USIER",
5305 &spr_read_generic, SPR_NOACCESS,
5306 &spr_read_generic, &spr_write_generic,
5307 0x00000000);
5308}
5309
5310static void register_power5p_ear_sprs(CPUPPCState *env)
5311{
5312
5313 spr_register(env, SPR_EAR, "EAR",
5314 SPR_NOACCESS, SPR_NOACCESS,
5315 &spr_read_generic, &spr_write_generic,
5316 0x00000000);
5317}
5318
5319static void register_power5p_tb_sprs(CPUPPCState *env)
5320{
5321
5322 spr_register_hv(env, SPR_TBU40, "TBU40",
5323 SPR_NOACCESS, SPR_NOACCESS,
5324 SPR_NOACCESS, SPR_NOACCESS,
5325 SPR_NOACCESS, &spr_write_tbu40,
5326 0x00000000);
5327}
5328
5329static void register_970_lpar_sprs(CPUPPCState *env)
5330{
5331#if !defined(CONFIG_USER_ONLY)
5332
5333
5334
5335
5336
5337
5338
5339 spr_register(env, SPR_970_HID4, "HID4",
5340 SPR_NOACCESS, SPR_NOACCESS,
5341 &spr_read_generic, &spr_write_generic,
5342 0x00000000);
5343#endif
5344}
5345
5346static void register_power5p_lpar_sprs(CPUPPCState *env)
5347{
5348#if !defined(CONFIG_USER_ONLY)
5349
5350 spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
5351 SPR_NOACCESS, SPR_NOACCESS,
5352 SPR_NOACCESS, SPR_NOACCESS,
5353 &spr_read_generic, &spr_write_lpcr,
5354 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
5355 spr_register_hv(env, SPR_HDEC, "HDEC",
5356 SPR_NOACCESS, SPR_NOACCESS,
5357 SPR_NOACCESS, SPR_NOACCESS,
5358 &spr_read_hdecr, &spr_write_hdecr, 0);
5359#endif
5360}
5361
5362static void register_book3s_ids_sprs(CPUPPCState *env)
5363{
5364
5365
5366
5367 spr_register_hv(env, SPR_PIR, "PIR",
5368 SPR_NOACCESS, SPR_NOACCESS,
5369 &spr_read_generic, SPR_NOACCESS,
5370 &spr_read_generic, NULL,
5371 0x00000000);
5372 spr_register_hv(env, SPR_HID0, "HID0",
5373 SPR_NOACCESS, SPR_NOACCESS,
5374 SPR_NOACCESS, SPR_NOACCESS,
5375 &spr_read_generic, &spr_write_generic,
5376 0x00000000);
5377 spr_register_hv(env, SPR_TSCR, "TSCR",
5378 SPR_NOACCESS, SPR_NOACCESS,
5379 SPR_NOACCESS, SPR_NOACCESS,
5380 &spr_read_generic, &spr_write_generic,
5381 0x00000000);
5382 spr_register_hv(env, SPR_HMER, "HMER",
5383 SPR_NOACCESS, SPR_NOACCESS,
5384 SPR_NOACCESS, SPR_NOACCESS,
5385 &spr_read_generic, &spr_write_hmer,
5386 0x00000000);
5387 spr_register_hv(env, SPR_HMEER, "HMEER",
5388 SPR_NOACCESS, SPR_NOACCESS,
5389 SPR_NOACCESS, SPR_NOACCESS,
5390 &spr_read_generic, &spr_write_generic,
5391 0x00000000);
5392 spr_register_hv(env, SPR_TFMR, "TFMR",
5393 SPR_NOACCESS, SPR_NOACCESS,
5394 SPR_NOACCESS, SPR_NOACCESS,
5395 &spr_read_generic, &spr_write_generic,
5396 0x00000000);
5397 spr_register_hv(env, SPR_LPIDR, "LPIDR",
5398 SPR_NOACCESS, SPR_NOACCESS,
5399 SPR_NOACCESS, SPR_NOACCESS,
5400 &spr_read_generic, &spr_write_lpidr,
5401 0x00000000);
5402 spr_register_hv(env, SPR_HFSCR, "HFSCR",
5403 SPR_NOACCESS, SPR_NOACCESS,
5404 SPR_NOACCESS, SPR_NOACCESS,
5405 &spr_read_generic, &spr_write_generic,
5406 0x00000000);
5407 spr_register_hv(env, SPR_MMCRC, "MMCRC",
5408 SPR_NOACCESS, SPR_NOACCESS,
5409 SPR_NOACCESS, SPR_NOACCESS,
5410 &spr_read_generic, &spr_write_generic,
5411 0x00000000);
5412 spr_register_hv(env, SPR_MMCRH, "MMCRH",
5413 SPR_NOACCESS, SPR_NOACCESS,
5414 SPR_NOACCESS, SPR_NOACCESS,
5415 &spr_read_generic, &spr_write_generic,
5416 0x00000000);
5417 spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
5418 SPR_NOACCESS, SPR_NOACCESS,
5419 SPR_NOACCESS, SPR_NOACCESS,
5420 &spr_read_generic, &spr_write_generic,
5421 0x00000000);
5422 spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
5423 SPR_NOACCESS, SPR_NOACCESS,
5424 SPR_NOACCESS, SPR_NOACCESS,
5425 &spr_read_generic, &spr_write_generic,
5426 0x00000000);
5427 spr_register_hv(env, SPR_HSRR0, "HSRR0",
5428 SPR_NOACCESS, SPR_NOACCESS,
5429 SPR_NOACCESS, SPR_NOACCESS,
5430 &spr_read_generic, &spr_write_generic,
5431 0x00000000);
5432 spr_register_hv(env, SPR_HSRR1, "HSRR1",
5433 SPR_NOACCESS, SPR_NOACCESS,
5434 SPR_NOACCESS, SPR_NOACCESS,
5435 &spr_read_generic, &spr_write_generic,
5436 0x00000000);
5437 spr_register_hv(env, SPR_HDAR, "HDAR",
5438 SPR_NOACCESS, SPR_NOACCESS,
5439 SPR_NOACCESS, SPR_NOACCESS,
5440 &spr_read_generic, &spr_write_generic,
5441 0x00000000);
5442 spr_register_hv(env, SPR_HDSISR, "HDSISR",
5443 SPR_NOACCESS, SPR_NOACCESS,
5444 SPR_NOACCESS, SPR_NOACCESS,
5445 &spr_read_generic, &spr_write_generic,
5446 0x00000000);
5447 spr_register_hv(env, SPR_HRMOR, "HRMOR",
5448 SPR_NOACCESS, SPR_NOACCESS,
5449 SPR_NOACCESS, SPR_NOACCESS,
5450 &spr_read_generic, &spr_write_generic,
5451 0x00000000);
5452}
5453
5454static void register_rmor_sprs(CPUPPCState *env)
5455{
5456 spr_register_hv(env, SPR_RMOR, "RMOR",
5457 SPR_NOACCESS, SPR_NOACCESS,
5458 SPR_NOACCESS, SPR_NOACCESS,
5459 &spr_read_generic, &spr_write_generic,
5460 0x00000000);
5461}
5462
5463static void register_power8_ids_sprs(CPUPPCState *env)
5464{
5465
5466 spr_register(env, SPR_TIR, "TIR",
5467 SPR_NOACCESS, SPR_NOACCESS,
5468 &spr_read_generic, SPR_NOACCESS,
5469 0x00000000);
5470}
5471
5472static void register_book3s_purr_sprs(CPUPPCState *env)
5473{
5474#if !defined(CONFIG_USER_ONLY)
5475
5476 spr_register_kvm_hv(env, SPR_PURR, "PURR",
5477 &spr_read_purr, SPR_NOACCESS,
5478 &spr_read_purr, SPR_NOACCESS,
5479 &spr_read_purr, &spr_write_purr,
5480 KVM_REG_PPC_PURR, 0x00000000);
5481 spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
5482 &spr_read_purr, SPR_NOACCESS,
5483 &spr_read_purr, SPR_NOACCESS,
5484 &spr_read_purr, &spr_write_purr,
5485 KVM_REG_PPC_SPURR, 0x00000000);
5486#endif
5487}
5488
5489static void register_power6_dbg_sprs(CPUPPCState *env)
5490{
5491#if !defined(CONFIG_USER_ONLY)
5492 spr_register(env, SPR_CFAR, "SPR_CFAR",
5493 SPR_NOACCESS, SPR_NOACCESS,
5494 &spr_read_cfar, &spr_write_cfar,
5495 0x00000000);
5496#endif
5497}
5498
5499static void register_power5p_common_sprs(CPUPPCState *env)
5500{
5501 spr_register_kvm(env, SPR_PPR, "PPR",
5502 &spr_read_generic, &spr_write_generic,
5503 &spr_read_generic, &spr_write_generic,
5504 KVM_REG_PPC_PPR, 0x00000000);
5505}
5506
5507static void register_power6_common_sprs(CPUPPCState *env)
5508{
5509#if !defined(CONFIG_USER_ONLY)
5510 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
5511 SPR_NOACCESS, SPR_NOACCESS,
5512 &spr_read_generic, &spr_write_generic,
5513 KVM_REG_PPC_DSCR, 0x00000000);
5514#endif
5515
5516
5517
5518
5519 spr_register_hv(env, SPR_PCR, "PCR",
5520 SPR_NOACCESS, SPR_NOACCESS,
5521 SPR_NOACCESS, SPR_NOACCESS,
5522 &spr_read_generic, &spr_write_pcr,
5523 0x00000000);
5524}
5525
5526static void register_power8_tce_address_control_sprs(CPUPPCState *env)
5527{
5528 spr_register_kvm(env, SPR_TAR, "TAR",
5529 &spr_read_tar, &spr_write_tar,
5530 &spr_read_generic, &spr_write_generic,
5531 KVM_REG_PPC_TAR, 0x00000000);
5532}
5533
5534static void register_power8_tm_sprs(CPUPPCState *env)
5535{
5536 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
5537 &spr_read_tm, &spr_write_tm,
5538 &spr_read_tm, &spr_write_tm,
5539 KVM_REG_PPC_TFHAR, 0x00000000);
5540 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
5541 &spr_read_tm, &spr_write_tm,
5542 &spr_read_tm, &spr_write_tm,
5543 KVM_REG_PPC_TFIAR, 0x00000000);
5544 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
5545 &spr_read_tm, &spr_write_tm,
5546 &spr_read_tm, &spr_write_tm,
5547 KVM_REG_PPC_TEXASR, 0x00000000);
5548 spr_register(env, SPR_TEXASRU, "TEXASRU",
5549 &spr_read_tm_upper32, &spr_write_tm_upper32,
5550 &spr_read_tm_upper32, &spr_write_tm_upper32,
5551 0x00000000);
5552}
5553
5554static void register_power8_ebb_sprs(CPUPPCState *env)
5555{
5556 spr_register(env, SPR_BESCRS, "BESCRS",
5557 &spr_read_ebb, &spr_write_ebb,
5558 &spr_read_generic, &spr_write_generic,
5559 0x00000000);
5560 spr_register(env, SPR_BESCRSU, "BESCRSU",
5561 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
5562 &spr_read_prev_upper32, &spr_write_prev_upper32,
5563 0x00000000);
5564 spr_register(env, SPR_BESCRR, "BESCRR",
5565 &spr_read_ebb, &spr_write_ebb,
5566 &spr_read_generic, &spr_write_generic,
5567 0x00000000);
5568 spr_register(env, SPR_BESCRRU, "BESCRRU",
5569 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
5570 &spr_read_prev_upper32, &spr_write_prev_upper32,
5571 0x00000000);
5572 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
5573 &spr_read_ebb, &spr_write_ebb,
5574 &spr_read_generic, &spr_write_generic,
5575 KVM_REG_PPC_EBBHR, 0x00000000);
5576 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
5577 &spr_read_ebb, &spr_write_ebb,
5578 &spr_read_generic, &spr_write_generic,
5579 KVM_REG_PPC_EBBRR, 0x00000000);
5580 spr_register_kvm(env, SPR_BESCR, "BESCR",
5581 &spr_read_ebb, &spr_write_ebb,
5582 &spr_read_generic, &spr_write_generic,
5583 KVM_REG_PPC_BESCR, 0x00000000);
5584}
5585
5586
5587static void register_vtb_sprs(CPUPPCState *env)
5588{
5589 spr_register_kvm_hv(env, SPR_VTB, "VTB",
5590 SPR_NOACCESS, SPR_NOACCESS,
5591 &spr_read_vtb, SPR_NOACCESS,
5592 &spr_read_vtb, &spr_write_vtb,
5593 KVM_REG_PPC_VTB, 0x00000000);
5594}
5595
5596static void register_power8_fscr_sprs(CPUPPCState *env)
5597{
5598#if defined(CONFIG_USER_ONLY)
5599 target_ulong initval = 1ULL << FSCR_TAR;
5600#else
5601 target_ulong initval = 0;
5602#endif
5603 spr_register_kvm(env, SPR_FSCR, "FSCR",
5604 SPR_NOACCESS, SPR_NOACCESS,
5605 &spr_read_generic, &spr_write_generic,
5606 KVM_REG_PPC_FSCR, initval);
5607}
5608
5609static void register_power8_pspb_sprs(CPUPPCState *env)
5610{
5611 spr_register_kvm(env, SPR_PSPB, "PSPB",
5612 SPR_NOACCESS, SPR_NOACCESS,
5613 &spr_read_generic, &spr_write_generic32,
5614 KVM_REG_PPC_PSPB, 0);
5615}
5616
5617static void register_power8_dpdes_sprs(CPUPPCState *env)
5618{
5619#if !defined(CONFIG_USER_ONLY)
5620
5621 spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
5622 SPR_NOACCESS, SPR_NOACCESS,
5623 &spr_read_dpdes, SPR_NOACCESS,
5624 &spr_read_dpdes, &spr_write_dpdes,
5625 KVM_REG_PPC_DPDES, 0x00000000);
5626#endif
5627}
5628
5629static void register_power8_ic_sprs(CPUPPCState *env)
5630{
5631#if !defined(CONFIG_USER_ONLY)
5632 spr_register_hv(env, SPR_IC, "IC",
5633 SPR_NOACCESS, SPR_NOACCESS,
5634 &spr_read_generic, SPR_NOACCESS,
5635 &spr_read_generic, &spr_write_generic,
5636 0);
5637#endif
5638}
5639
5640static void register_power8_book4_sprs(CPUPPCState *env)
5641{
5642
5643#if !defined(CONFIG_USER_ONLY)
5644 spr_register_kvm(env, SPR_ACOP, "ACOP",
5645 SPR_NOACCESS, SPR_NOACCESS,
5646 &spr_read_generic, &spr_write_generic,
5647 KVM_REG_PPC_ACOP, 0);
5648 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
5649 SPR_NOACCESS, SPR_NOACCESS,
5650 &spr_read_generic, &spr_write_pidr,
5651 KVM_REG_PPC_PID, 0);
5652 spr_register_kvm(env, SPR_WORT, "WORT",
5653 SPR_NOACCESS, SPR_NOACCESS,
5654 &spr_read_generic, &spr_write_generic,
5655 KVM_REG_PPC_WORT, 0);
5656#endif
5657}
5658
5659static void register_power7_book4_sprs(CPUPPCState *env)
5660{
5661
5662#if !defined(CONFIG_USER_ONLY)
5663 spr_register_kvm(env, SPR_ACOP, "ACOP",
5664 SPR_NOACCESS, SPR_NOACCESS,
5665 &spr_read_generic, &spr_write_generic,
5666 KVM_REG_PPC_ACOP, 0);
5667 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
5668 SPR_NOACCESS, SPR_NOACCESS,
5669 &spr_read_generic, &spr_write_generic,
5670 KVM_REG_PPC_PID, 0);
5671#endif
5672}
5673
5674static void register_power8_rpr_sprs(CPUPPCState *env)
5675{
5676#if !defined(CONFIG_USER_ONLY)
5677 spr_register_hv(env, SPR_RPR, "RPR",
5678 SPR_NOACCESS, SPR_NOACCESS,
5679 SPR_NOACCESS, SPR_NOACCESS,
5680 &spr_read_generic, &spr_write_generic,
5681 0x00000103070F1F3F);
5682#endif
5683}
5684
5685static void register_power9_mmu_sprs(CPUPPCState *env)
5686{
5687#if !defined(CONFIG_USER_ONLY)
5688
5689 spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
5690 SPR_NOACCESS, SPR_NOACCESS,
5691 SPR_NOACCESS, SPR_NOACCESS,
5692 &spr_read_generic, &spr_write_ptcr,
5693 KVM_REG_PPC_PTCR, 0x00000000);
5694
5695 spr_register_hv(env, SPR_ASDR, "ASDR",
5696 SPR_NOACCESS, SPR_NOACCESS,
5697 SPR_NOACCESS, SPR_NOACCESS,
5698 &spr_read_generic, &spr_write_generic,
5699 0x0000000000000000);
5700#endif
5701}
5702
5703
5704
5705
5706
5707static void init_tcg_pmu_power8(CPUPPCState *env)
5708{
5709
5710 if (tcg_enabled()) {
5711 cpu_ppc_pmu_init(env);
5712 }
5713}
5714
5715static void init_proc_book3s_common(CPUPPCState *env)
5716{
5717 register_non_embedded_sprs(env);
5718 register_book3s_altivec_sprs(env);
5719 register_book3s_pmu_sup_sprs(env);
5720 register_book3s_pmu_user_sprs(env);
5721 register_book3s_ctrl_sprs(env);
5722
5723
5724
5725
5726 vscr_init(env, 0x00010000);
5727
5728 spr_register(env, SPR_USPRG3, "USPRG3",
5729 &spr_read_ureg, SPR_NOACCESS,
5730 &spr_read_ureg, SPR_NOACCESS,
5731 0x00000000);
5732}
5733
5734static void init_proc_970(CPUPPCState *env)
5735{
5736
5737 init_proc_book3s_common(env);
5738 register_sdr1_sprs(env);
5739 register_book3s_dbg_sprs(env);
5740
5741
5742 register_970_hid_sprs(env);
5743 register_970_hior_sprs(env);
5744 register_low_BATs(env);
5745 register_970_pmu_sup_sprs(env);
5746 register_970_pmu_user_sprs(env);
5747 register_970_lpar_sprs(env);
5748 register_970_dbg_sprs(env);
5749
5750
5751 env->dcache_line_size = 128;
5752 env->icache_line_size = 128;
5753
5754
5755 init_excp_970(env);
5756 ppc970_irq_init(env_archcpu(env));
5757}
5758
5759POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
5760{
5761 DeviceClass *dc = DEVICE_CLASS(oc);
5762 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5763
5764 dc->desc = "PowerPC 970";
5765 pcc->init_proc = init_proc_970;
5766 pcc->check_pow = check_pow_970;
5767 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5768 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5769 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5770 PPC_FLOAT_STFIWX |
5771 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5772 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5773 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5774 PPC_64B | PPC_ALTIVEC |
5775 PPC_SEGMENT_64B | PPC_SLBI;
5776 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC;
5777 pcc->msr_mask = (1ull << MSR_SF) |
5778 (1ull << MSR_VR) |
5779 (1ull << MSR_POW) |
5780 (1ull << MSR_EE) |
5781 (1ull << MSR_PR) |
5782 (1ull << MSR_FP) |
5783 (1ull << MSR_ME) |
5784 (1ull << MSR_FE0) |
5785 (1ull << MSR_SE) |
5786 (1ull << MSR_DE) |
5787 (1ull << MSR_FE1) |
5788 (1ull << MSR_IR) |
5789 (1ull << MSR_DR) |
5790 (1ull << MSR_PMM) |
5791 (1ull << MSR_RI);
5792 pcc->mmu_model = POWERPC_MMU_64B;
5793#if defined(CONFIG_SOFTMMU)
5794 pcc->hash64_opts = &ppc_hash64_opts_basic;
5795#endif
5796 pcc->excp_model = POWERPC_EXCP_970;
5797 pcc->bus_model = PPC_FLAGS_INPUT_970;
5798 pcc->bfd_mach = bfd_mach_ppc64;
5799 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5800 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5801 POWERPC_FLAG_BUS_CLK;
5802 pcc->l1_dcache_size = 0x8000;
5803 pcc->l1_icache_size = 0x10000;
5804}
5805
5806static void init_proc_power5plus(CPUPPCState *env)
5807{
5808
5809 init_proc_book3s_common(env);
5810 register_sdr1_sprs(env);
5811 register_book3s_dbg_sprs(env);
5812
5813
5814 register_970_hid_sprs(env);
5815 register_970_hior_sprs(env);
5816 register_low_BATs(env);
5817 register_970_pmu_sup_sprs(env);
5818 register_970_pmu_user_sprs(env);
5819 register_power5p_common_sprs(env);
5820 register_power5p_lpar_sprs(env);
5821 register_power5p_ear_sprs(env);
5822 register_power5p_tb_sprs(env);
5823
5824
5825 env->dcache_line_size = 128;
5826 env->icache_line_size = 128;
5827
5828
5829 init_excp_970(env);
5830 ppc970_irq_init(env_archcpu(env));
5831}
5832
5833POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
5834{
5835 DeviceClass *dc = DEVICE_CLASS(oc);
5836 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5837
5838 dc->fw_name = "PowerPC,POWER5";
5839 dc->desc = "POWER5+";
5840 pcc->init_proc = init_proc_power5plus;
5841 pcc->check_pow = check_pow_970;
5842 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5843 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5844 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5845 PPC_FLOAT_STFIWX |
5846 PPC_FLOAT_EXT |
5847 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5848 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5849 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5850 PPC_64B |
5851 PPC_POPCNTB |
5852 PPC_SEGMENT_64B | PPC_SLBI;
5853 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC;
5854 pcc->msr_mask = (1ull << MSR_SF) |
5855 (1ull << MSR_VR) |
5856 (1ull << MSR_POW) |
5857 (1ull << MSR_EE) |
5858 (1ull << MSR_PR) |
5859 (1ull << MSR_FP) |
5860 (1ull << MSR_ME) |
5861 (1ull << MSR_FE0) |
5862 (1ull << MSR_SE) |
5863 (1ull << MSR_DE) |
5864 (1ull << MSR_FE1) |
5865 (1ull << MSR_IR) |
5866 (1ull << MSR_DR) |
5867 (1ull << MSR_PMM) |
5868 (1ull << MSR_RI);
5869 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
5870 LPCR_RMI | LPCR_HDICE;
5871 pcc->mmu_model = POWERPC_MMU_2_03;
5872#if defined(CONFIG_SOFTMMU)
5873 pcc->hash64_opts = &ppc_hash64_opts_basic;
5874 pcc->lrg_decr_bits = 32;
5875#endif
5876 pcc->excp_model = POWERPC_EXCP_970;
5877 pcc->bus_model = PPC_FLAGS_INPUT_970;
5878 pcc->bfd_mach = bfd_mach_ppc64;
5879 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5880 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5881 POWERPC_FLAG_BUS_CLK;
5882 pcc->l1_dcache_size = 0x8000;
5883 pcc->l1_icache_size = 0x10000;
5884}
5885
5886static void init_proc_POWER7(CPUPPCState *env)
5887{
5888
5889 init_proc_book3s_common(env);
5890 register_sdr1_sprs(env);
5891 register_book3s_dbg_sprs(env);
5892
5893
5894 register_book3s_ids_sprs(env);
5895 register_rmor_sprs(env);
5896 register_amr_sprs(env);
5897 register_book3s_purr_sprs(env);
5898 register_power5p_common_sprs(env);
5899 register_power5p_lpar_sprs(env);
5900 register_power5p_ear_sprs(env);
5901 register_power5p_tb_sprs(env);
5902 register_power6_common_sprs(env);
5903 register_power6_dbg_sprs(env);
5904 register_power7_book4_sprs(env);
5905
5906
5907 env->dcache_line_size = 128;
5908 env->icache_line_size = 128;
5909
5910
5911 init_excp_POWER7(env);
5912 ppcPOWER7_irq_init(env_archcpu(env));
5913}
5914
5915static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
5916{
5917 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
5918 return true;
5919 }
5920 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
5921 return true;
5922 }
5923 return false;
5924}
5925
5926static bool cpu_has_work_POWER7(CPUState *cs)
5927{
5928 PowerPCCPU *cpu = POWERPC_CPU(cs);
5929 CPUPPCState *env = &cpu->env;
5930
5931 if (cs->halted) {
5932 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
5933 return false;
5934 }
5935 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
5936 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
5937 return true;
5938 }
5939 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
5940 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
5941 return true;
5942 }
5943 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
5944 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
5945 return true;
5946 }
5947 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
5948 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
5949 return true;
5950 }
5951 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
5952 return true;
5953 }
5954 return false;
5955 } else {
5956 return FIELD_EX64(env->msr, MSR, EE) &&
5957 (cs->interrupt_request & CPU_INTERRUPT_HARD);
5958 }
5959}
5960
5961POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
5962{
5963 DeviceClass *dc = DEVICE_CLASS(oc);
5964 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5965 CPUClass *cc = CPU_CLASS(oc);
5966
5967 dc->fw_name = "PowerPC,POWER7";
5968 dc->desc = "POWER7";
5969 pcc->pvr_match = ppc_pvr_match_power7;
5970 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
5971 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
5972 pcc->init_proc = init_proc_POWER7;
5973 pcc->check_pow = check_pow_nocheck;
5974 cc->has_work = cpu_has_work_POWER7;
5975 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
5976 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5977 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5978 PPC_FLOAT_FRSQRTES |
5979 PPC_FLOAT_STFIWX |
5980 PPC_FLOAT_EXT |
5981 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5982 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5983 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5984 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
5985 PPC_SEGMENT_64B | PPC_SLBI |
5986 PPC_POPCNTB | PPC_POPCNTWD |
5987 PPC_CILDST;
5988 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
5989 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
5990 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
5991 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
5992 PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206;
5993 pcc->msr_mask = (1ull << MSR_SF) |
5994 (1ull << MSR_VR) |
5995 (1ull << MSR_VSX) |
5996 (1ull << MSR_EE) |
5997 (1ull << MSR_PR) |
5998 (1ull << MSR_FP) |
5999 (1ull << MSR_ME) |
6000 (1ull << MSR_FE0) |
6001 (1ull << MSR_SE) |
6002 (1ull << MSR_DE) |
6003 (1ull << MSR_FE1) |
6004 (1ull << MSR_IR) |
6005 (1ull << MSR_DR) |
6006 (1ull << MSR_PMM) |
6007 (1ull << MSR_RI) |
6008 (1ull << MSR_LE);
6009 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
6010 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6011 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
6012 LPCR_MER | LPCR_TC |
6013 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
6014 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
6015 pcc->mmu_model = POWERPC_MMU_2_06;
6016#if defined(CONFIG_SOFTMMU)
6017 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6018 pcc->lrg_decr_bits = 32;
6019#endif
6020 pcc->excp_model = POWERPC_EXCP_POWER7;
6021 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6022 pcc->bfd_mach = bfd_mach_ppc64;
6023 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6024 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6025 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6026 POWERPC_FLAG_VSX;
6027 pcc->l1_dcache_size = 0x8000;
6028 pcc->l1_icache_size = 0x8000;
6029}
6030
6031static void init_proc_POWER8(CPUPPCState *env)
6032{
6033
6034 init_proc_book3s_common(env);
6035 register_sdr1_sprs(env);
6036 register_book3s_207_dbg_sprs(env);
6037
6038
6039 init_tcg_pmu_power8(env);
6040
6041
6042 register_book3s_ids_sprs(env);
6043 register_rmor_sprs(env);
6044 register_amr_sprs(env);
6045 register_iamr_sprs(env);
6046 register_book3s_purr_sprs(env);
6047 register_power5p_common_sprs(env);
6048 register_power5p_lpar_sprs(env);
6049 register_power5p_ear_sprs(env);
6050 register_power5p_tb_sprs(env);
6051 register_power6_common_sprs(env);
6052 register_power6_dbg_sprs(env);
6053 register_power8_tce_address_control_sprs(env);
6054 register_power8_ids_sprs(env);
6055 register_power8_ebb_sprs(env);
6056 register_power8_fscr_sprs(env);
6057 register_power8_pmu_sup_sprs(env);
6058 register_power8_pmu_user_sprs(env);
6059 register_power8_tm_sprs(env);
6060 register_power8_pspb_sprs(env);
6061 register_power8_dpdes_sprs(env);
6062 register_vtb_sprs(env);
6063 register_power8_ic_sprs(env);
6064 register_power8_book4_sprs(env);
6065 register_power8_rpr_sprs(env);
6066
6067
6068 env->dcache_line_size = 128;
6069 env->icache_line_size = 128;
6070
6071
6072 init_excp_POWER8(env);
6073 ppcPOWER7_irq_init(env_archcpu(env));
6074}
6075
6076static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
6077{
6078 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
6079 return true;
6080 }
6081 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
6082 return true;
6083 }
6084 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
6085 return true;
6086 }
6087 return false;
6088}
6089
6090static bool cpu_has_work_POWER8(CPUState *cs)
6091{
6092 PowerPCCPU *cpu = POWERPC_CPU(cs);
6093 CPUPPCState *env = &cpu->env;
6094
6095 if (cs->halted) {
6096 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6097 return false;
6098 }
6099 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6100 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
6101 return true;
6102 }
6103 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6104 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
6105 return true;
6106 }
6107 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
6108 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
6109 return true;
6110 }
6111 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
6112 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
6113 return true;
6114 }
6115 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
6116 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
6117 return true;
6118 }
6119 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
6120 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
6121 return true;
6122 }
6123 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6124 return true;
6125 }
6126 return false;
6127 } else {
6128 return FIELD_EX64(env->msr, MSR, EE) &&
6129 (cs->interrupt_request & CPU_INTERRUPT_HARD);
6130 }
6131}
6132
6133POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
6134{
6135 DeviceClass *dc = DEVICE_CLASS(oc);
6136 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6137 CPUClass *cc = CPU_CLASS(oc);
6138
6139 dc->fw_name = "PowerPC,POWER8";
6140 dc->desc = "POWER8";
6141 pcc->pvr_match = ppc_pvr_match_power8;
6142 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6143 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6144 pcc->init_proc = init_proc_POWER8;
6145 pcc->check_pow = check_pow_nocheck;
6146 cc->has_work = cpu_has_work_POWER8;
6147 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6148 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6149 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6150 PPC_FLOAT_FRSQRTES |
6151 PPC_FLOAT_STFIWX |
6152 PPC_FLOAT_EXT |
6153 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6154 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6155 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6156 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6157 PPC_SEGMENT_64B | PPC_SLBI |
6158 PPC_POPCNTB | PPC_POPCNTWD |
6159 PPC_CILDST;
6160 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6161 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6162 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6163 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6164 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6165 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6166 PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC |
6167 PPC2_BCDA_ISA206;
6168 pcc->msr_mask = (1ull << MSR_SF) |
6169 (1ull << MSR_HV) |
6170 (1ull << MSR_TM) |
6171 (1ull << MSR_VR) |
6172 (1ull << MSR_VSX) |
6173 (1ull << MSR_EE) |
6174 (1ull << MSR_PR) |
6175 (1ull << MSR_FP) |
6176 (1ull << MSR_ME) |
6177 (1ull << MSR_FE0) |
6178 (1ull << MSR_SE) |
6179 (1ull << MSR_DE) |
6180 (1ull << MSR_FE1) |
6181 (1ull << MSR_IR) |
6182 (1ull << MSR_DR) |
6183 (1ull << MSR_PMM) |
6184 (1ull << MSR_RI) |
6185 (1ull << MSR_TS0) |
6186 (1ull << MSR_TS1) |
6187 (1ull << MSR_LE);
6188 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
6189 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6190 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
6191 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
6192 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
6193 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
6194 LPCR_P8_PECE3 | LPCR_P8_PECE4;
6195 pcc->mmu_model = POWERPC_MMU_2_07;
6196#if defined(CONFIG_SOFTMMU)
6197 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6198 pcc->lrg_decr_bits = 32;
6199 pcc->n_host_threads = 8;
6200#endif
6201 pcc->excp_model = POWERPC_EXCP_POWER8;
6202 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6203 pcc->bfd_mach = bfd_mach_ppc64;
6204 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6205 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6206 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6207 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
6208 pcc->l1_dcache_size = 0x8000;
6209 pcc->l1_icache_size = 0x8000;
6210}
6211
6212#ifdef CONFIG_SOFTMMU
6213
6214
6215
6216
6217
6218
6219
6220static struct ppc_radix_page_info POWER9_radix_page_info = {
6221 .count = 4,
6222 .entries = {
6223 0x0000000c,
6224 0xa0000010,
6225 0x20000015,
6226 0x4000001e
6227 }
6228};
6229#endif
6230
6231static void init_proc_POWER9(CPUPPCState *env)
6232{
6233
6234 init_proc_book3s_common(env);
6235 register_book3s_207_dbg_sprs(env);
6236
6237
6238 init_tcg_pmu_power8(env);
6239
6240
6241 register_book3s_ids_sprs(env);
6242 register_amr_sprs(env);
6243 register_iamr_sprs(env);
6244 register_book3s_purr_sprs(env);
6245 register_power5p_common_sprs(env);
6246 register_power5p_lpar_sprs(env);
6247 register_power5p_ear_sprs(env);
6248 register_power5p_tb_sprs(env);
6249 register_power6_common_sprs(env);
6250 register_power6_dbg_sprs(env);
6251 register_power8_tce_address_control_sprs(env);
6252 register_power8_ids_sprs(env);
6253 register_power8_ebb_sprs(env);
6254 register_power8_fscr_sprs(env);
6255 register_power8_pmu_sup_sprs(env);
6256 register_power8_pmu_user_sprs(env);
6257 register_power8_tm_sprs(env);
6258 register_power8_pspb_sprs(env);
6259 register_power8_dpdes_sprs(env);
6260 register_vtb_sprs(env);
6261 register_power8_ic_sprs(env);
6262 register_power8_book4_sprs(env);
6263 register_power8_rpr_sprs(env);
6264 register_power9_mmu_sprs(env);
6265
6266
6267 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
6268 spr_read_generic, spr_write_generic,
6269 KVM_REG_PPC_TIDR, 0);
6270
6271
6272 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
6273 spr_read_generic, spr_write_generic,
6274 KVM_REG_PPC_PSSCR, 0);
6275
6276
6277 env->dcache_line_size = 128;
6278 env->icache_line_size = 128;
6279
6280
6281 init_excp_POWER9(env);
6282 ppcPOWER9_irq_init(env_archcpu(env));
6283}
6284
6285static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
6286{
6287 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
6288 return true;
6289 }
6290 return false;
6291}
6292
6293static bool cpu_has_work_POWER9(CPUState *cs)
6294{
6295 PowerPCCPU *cpu = POWERPC_CPU(cs);
6296 CPUPPCState *env = &cpu->env;
6297
6298 if (cs->halted) {
6299 uint64_t psscr = env->spr[SPR_PSSCR];
6300
6301 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6302 return false;
6303 }
6304
6305
6306 if (!(psscr & PSSCR_EC)) {
6307 return true;
6308 }
6309
6310 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6311 (env->spr[SPR_LPCR] & LPCR_EEE)) {
6312 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
6313 if (!heic || !FIELD_EX64_HV(env->msr) ||
6314 FIELD_EX64(env->msr, MSR, PR)) {
6315 return true;
6316 }
6317 }
6318
6319 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6320 (env->spr[SPR_LPCR] & LPCR_DEE)) {
6321 return true;
6322 }
6323
6324 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
6325 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
6326 return true;
6327 }
6328
6329 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
6330 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
6331 return true;
6332 }
6333
6334 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
6335 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
6336 return true;
6337 }
6338
6339 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
6340 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
6341 return true;
6342 }
6343 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6344 return true;
6345 }
6346 return false;
6347 } else {
6348 return FIELD_EX64(env->msr, MSR, EE) &&
6349 (cs->interrupt_request & CPU_INTERRUPT_HARD);
6350 }
6351}
6352
6353POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
6354{
6355 DeviceClass *dc = DEVICE_CLASS(oc);
6356 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6357 CPUClass *cc = CPU_CLASS(oc);
6358
6359 dc->fw_name = "PowerPC,POWER9";
6360 dc->desc = "POWER9";
6361 pcc->pvr_match = ppc_pvr_match_power9;
6362 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
6363 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
6364 PCR_COMPAT_2_05;
6365 pcc->init_proc = init_proc_POWER9;
6366 pcc->check_pow = check_pow_nocheck;
6367 cc->has_work = cpu_has_work_POWER9;
6368 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6369 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6370 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6371 PPC_FLOAT_FRSQRTES |
6372 PPC_FLOAT_STFIWX |
6373 PPC_FLOAT_EXT |
6374 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6375 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6376 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6377 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6378 PPC_SEGMENT_64B | PPC_SLBI |
6379 PPC_POPCNTB | PPC_POPCNTWD |
6380 PPC_CILDST;
6381 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6382 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6383 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6384 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6385 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6386 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6387 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_MEM_LWSYNC |
6388 PPC2_BCDA_ISA206;
6389 pcc->msr_mask = (1ull << MSR_SF) |
6390 (1ull << MSR_HV) |
6391 (1ull << MSR_TM) |
6392 (1ull << MSR_VR) |
6393 (1ull << MSR_VSX) |
6394 (1ull << MSR_EE) |
6395 (1ull << MSR_PR) |
6396 (1ull << MSR_FP) |
6397 (1ull << MSR_ME) |
6398 (1ull << MSR_FE0) |
6399 (1ull << MSR_SE) |
6400 (1ull << MSR_DE) |
6401 (1ull << MSR_FE1) |
6402 (1ull << MSR_IR) |
6403 (1ull << MSR_DR) |
6404 (1ull << MSR_PMM) |
6405 (1ull << MSR_RI) |
6406 (1ull << MSR_LE);
6407 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
6408 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
6409 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
6410 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
6411 LPCR_DEE | LPCR_OEE))
6412 | LPCR_MER | LPCR_GTSE | LPCR_TC |
6413 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
6414 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6415 pcc->mmu_model = POWERPC_MMU_3_00;
6416#if defined(CONFIG_SOFTMMU)
6417
6418 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6419 pcc->radix_page_info = &POWER9_radix_page_info;
6420 pcc->lrg_decr_bits = 56;
6421 pcc->n_host_threads = 4;
6422#endif
6423 pcc->excp_model = POWERPC_EXCP_POWER9;
6424 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6425 pcc->bfd_mach = bfd_mach_ppc64;
6426 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6427 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6428 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6429 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
6430 pcc->l1_dcache_size = 0x8000;
6431 pcc->l1_icache_size = 0x8000;
6432}
6433
6434#ifdef CONFIG_SOFTMMU
6435
6436
6437
6438
6439
6440
6441
6442static struct ppc_radix_page_info POWER10_radix_page_info = {
6443 .count = 4,
6444 .entries = {
6445 0x0000000c,
6446 0xa0000010,
6447 0x20000015,
6448 0x4000001e
6449 }
6450};
6451#endif
6452
6453static void init_proc_POWER10(CPUPPCState *env)
6454{
6455
6456 init_proc_book3s_common(env);
6457 register_book3s_207_dbg_sprs(env);
6458
6459
6460 init_tcg_pmu_power8(env);
6461
6462
6463 register_book3s_ids_sprs(env);
6464 register_amr_sprs(env);
6465 register_iamr_sprs(env);
6466 register_book3s_purr_sprs(env);
6467 register_power5p_common_sprs(env);
6468 register_power5p_lpar_sprs(env);
6469 register_power5p_ear_sprs(env);
6470 register_power5p_tb_sprs(env);
6471 register_power6_common_sprs(env);
6472 register_power6_dbg_sprs(env);
6473 register_power8_tce_address_control_sprs(env);
6474 register_power8_ids_sprs(env);
6475 register_power8_ebb_sprs(env);
6476 register_power8_fscr_sprs(env);
6477 register_power8_pmu_sup_sprs(env);
6478 register_power8_pmu_user_sprs(env);
6479 register_power8_tm_sprs(env);
6480 register_power8_pspb_sprs(env);
6481 register_power8_dpdes_sprs(env);
6482 register_vtb_sprs(env);
6483 register_power8_ic_sprs(env);
6484 register_power8_book4_sprs(env);
6485 register_power8_rpr_sprs(env);
6486 register_power9_mmu_sprs(env);
6487
6488
6489 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
6490 spr_read_generic, spr_write_generic,
6491 KVM_REG_PPC_PSSCR, 0);
6492
6493
6494 env->dcache_line_size = 128;
6495 env->icache_line_size = 128;
6496
6497
6498 init_excp_POWER10(env);
6499 ppcPOWER9_irq_init(env_archcpu(env));
6500}
6501
6502static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr)
6503{
6504 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) {
6505 return true;
6506 }
6507 return false;
6508}
6509
6510static bool cpu_has_work_POWER10(CPUState *cs)
6511{
6512 PowerPCCPU *cpu = POWERPC_CPU(cs);
6513 CPUPPCState *env = &cpu->env;
6514
6515 if (cs->halted) {
6516 uint64_t psscr = env->spr[SPR_PSSCR];
6517
6518 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6519 return false;
6520 }
6521
6522
6523 if (!(psscr & PSSCR_EC)) {
6524 return true;
6525 }
6526
6527 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6528 (env->spr[SPR_LPCR] & LPCR_EEE)) {
6529 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
6530 if (!heic || !FIELD_EX64_HV(env->msr) ||
6531 FIELD_EX64(env->msr, MSR, PR)) {
6532 return true;
6533 }
6534 }
6535
6536 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6537 (env->spr[SPR_LPCR] & LPCR_DEE)) {
6538 return true;
6539 }
6540
6541 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
6542 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
6543 return true;
6544 }
6545
6546 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
6547 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
6548 return true;
6549 }
6550
6551 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
6552 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
6553 return true;
6554 }
6555
6556 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
6557 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
6558 return true;
6559 }
6560 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6561 return true;
6562 }
6563 return false;
6564 } else {
6565 return FIELD_EX64(env->msr, MSR, EE) &&
6566 (cs->interrupt_request & CPU_INTERRUPT_HARD);
6567 }
6568}
6569
6570POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
6571{
6572 DeviceClass *dc = DEVICE_CLASS(oc);
6573 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6574 CPUClass *cc = CPU_CLASS(oc);
6575
6576 dc->fw_name = "PowerPC,POWER10";
6577 dc->desc = "POWER10";
6578 pcc->pvr_match = ppc_pvr_match_power10;
6579 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
6580 PCR_COMPAT_3_00;
6581 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
6582 PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6583 pcc->init_proc = init_proc_POWER10;
6584 pcc->check_pow = check_pow_nocheck;
6585 cc->has_work = cpu_has_work_POWER10;
6586 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6587 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6588 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6589 PPC_FLOAT_FRSQRTES |
6590 PPC_FLOAT_STFIWX |
6591 PPC_FLOAT_EXT |
6592 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6593 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6594 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6595 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6596 PPC_SEGMENT_64B | PPC_SLBI |
6597 PPC_POPCNTB | PPC_POPCNTWD |
6598 PPC_CILDST;
6599 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6600 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6601 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6602 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6603 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6604 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6605 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 |
6606 PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206;
6607 pcc->msr_mask = (1ull << MSR_SF) |
6608 (1ull << MSR_HV) |
6609 (1ull << MSR_TM) |
6610 (1ull << MSR_VR) |
6611 (1ull << MSR_VSX) |
6612 (1ull << MSR_EE) |
6613 (1ull << MSR_PR) |
6614 (1ull << MSR_FP) |
6615 (1ull << MSR_ME) |
6616 (1ull << MSR_FE0) |
6617 (1ull << MSR_SE) |
6618 (1ull << MSR_DE) |
6619 (1ull << MSR_FE1) |
6620 (1ull << MSR_IR) |
6621 (1ull << MSR_DR) |
6622 (1ull << MSR_PMM) |
6623 (1ull << MSR_RI) |
6624 (1ull << MSR_LE);
6625 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
6626 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
6627 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
6628 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
6629 LPCR_DEE | LPCR_OEE))
6630 | LPCR_MER | LPCR_GTSE | LPCR_TC |
6631 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
6632
6633 pcc->lpcr_mask |= LPCR_HAIL;
6634
6635 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6636 pcc->mmu_model = POWERPC_MMU_3_00;
6637#if defined(CONFIG_SOFTMMU)
6638
6639 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6640 pcc->radix_page_info = &POWER10_radix_page_info;
6641 pcc->lrg_decr_bits = 56;
6642#endif
6643 pcc->excp_model = POWERPC_EXCP_POWER10;
6644 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6645 pcc->bfd_mach = bfd_mach_ppc64;
6646 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6647 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6648 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6649 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
6650 pcc->l1_dcache_size = 0x8000;
6651 pcc->l1_icache_size = 0x8000;
6652}
6653
6654#if !defined(CONFIG_USER_ONLY)
6655void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
6656{
6657 CPUPPCState *env = &cpu->env;
6658
6659 cpu->vhyp = vhyp;
6660
6661
6662
6663
6664
6665 env->msr_mask &= ~MSR_HVB;
6666}
6667
6668#endif
6669
6670#endif
6671
6672
6673
6674static void init_ppc_proc(PowerPCCPU *cpu)
6675{
6676 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6677 CPUPPCState *env = &cpu->env;
6678#if !defined(CONFIG_USER_ONLY)
6679 int i;
6680
6681
6682 for (i = 0; i < POWERPC_EXCP_NB; i++) {
6683 env->excp_vectors[i] = (target_ulong)(-1ULL);
6684 }
6685 env->ivor_mask = 0x00000000;
6686 env->ivpr_mask = 0x00000000;
6687
6688 env->nb_BATs = 0;
6689 env->nb_tlb = 0;
6690 env->nb_ways = 0;
6691 env->tlb_type = TLB_NONE;
6692#endif
6693
6694 register_generic_sprs(cpu);
6695
6696
6697 (*pcc->init_proc)(env);
6698
6699#if !defined(CONFIG_USER_ONLY)
6700 ppc_gdb_gen_spr_xml(cpu);
6701#endif
6702
6703
6704 if (env->msr_mask & (1 << 25)) {
6705 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
6706 case POWERPC_FLAG_SPE:
6707 case POWERPC_FLAG_VRE:
6708 break;
6709 default:
6710 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6711 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
6712 exit(1);
6713 }
6714 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
6715 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6716 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
6717 exit(1);
6718 }
6719 if (env->msr_mask & (1 << 17)) {
6720 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
6721 case POWERPC_FLAG_TGPR:
6722 case POWERPC_FLAG_CE:
6723 break;
6724 default:
6725 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6726 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
6727 exit(1);
6728 }
6729 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
6730 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6731 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
6732 exit(1);
6733 }
6734 if (env->msr_mask & (1 << 10)) {
6735 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
6736 POWERPC_FLAG_UBLE)) {
6737 case POWERPC_FLAG_SE:
6738 case POWERPC_FLAG_DWE:
6739 case POWERPC_FLAG_UBLE:
6740 break;
6741 default:
6742 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6743 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
6744 "POWERPC_FLAG_UBLE\n");
6745 exit(1);
6746 }
6747 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
6748 POWERPC_FLAG_UBLE)) {
6749 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6750 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
6751 "POWERPC_FLAG_UBLE\n");
6752 exit(1);
6753 }
6754 if (env->msr_mask & (1 << 9)) {
6755 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6756 case POWERPC_FLAG_BE:
6757 case POWERPC_FLAG_DE:
6758 break;
6759 default:
6760 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6761 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
6762 exit(1);
6763 }
6764 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6765 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6766 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
6767 exit(1);
6768 }
6769 if (env->msr_mask & (1 << 2)) {
6770 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6771 case POWERPC_FLAG_PX:
6772 case POWERPC_FLAG_PMM:
6773 break;
6774 default:
6775 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6776 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
6777 exit(1);
6778 }
6779 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6780 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6781 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
6782 exit(1);
6783 }
6784 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) {
6785 fprintf(stderr, "PowerPC flags inconsistency\n"
6786 "Should define the time-base and decrementer clock source\n");
6787 exit(1);
6788 }
6789
6790#if !defined(CONFIG_USER_ONLY)
6791 if (env->nb_tlb != 0) {
6792 int nb_tlb = env->nb_tlb;
6793 if (env->id_tlbs != 0) {
6794 nb_tlb *= 2;
6795 }
6796 switch (env->tlb_type) {
6797 case TLB_6XX:
6798 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
6799 break;
6800 case TLB_EMB:
6801 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
6802 break;
6803 case TLB_MAS:
6804 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
6805 break;
6806 }
6807
6808 env->tlb_per_way = env->nb_tlb / env->nb_ways;
6809 }
6810#endif
6811 if (env->check_pow == NULL) {
6812 warn_report("no power management check handler registered."
6813 " Attempt QEMU to crash very soon !");
6814 }
6815}
6816
6817
6818static void ppc_cpu_realize(DeviceState *dev, Error **errp)
6819{
6820 CPUState *cs = CPU(dev);
6821 PowerPCCPU *cpu = POWERPC_CPU(dev);
6822 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6823 Error *local_err = NULL;
6824
6825 cpu_exec_realizefn(cs, &local_err);
6826 if (local_err != NULL) {
6827 error_propagate(errp, local_err);
6828 return;
6829 }
6830 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
6831 cpu->vcpu_id = cs->cpu_index;
6832 }
6833
6834 if (tcg_enabled()) {
6835 if (ppc_fixup_cpu(cpu) != 0) {
6836 error_setg(errp, "Unable to emulate selected CPU with TCG");
6837 goto unrealize;
6838 }
6839 }
6840
6841 create_ppc_opcodes(cpu, &local_err);
6842 if (local_err != NULL) {
6843 error_propagate(errp, local_err);
6844 goto unrealize;
6845 }
6846 init_ppc_proc(cpu);
6847
6848 ppc_gdb_init(cs, pcc);
6849 qemu_init_vcpu(cs);
6850
6851 pcc->parent_realize(dev, errp);
6852
6853 return;
6854
6855unrealize:
6856 cpu_exec_unrealizefn(cs);
6857}
6858
6859static void ppc_cpu_unrealize(DeviceState *dev)
6860{
6861 PowerPCCPU *cpu = POWERPC_CPU(dev);
6862 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6863
6864 pcc->parent_unrealize(dev);
6865
6866 cpu_remove_sync(CPU(cpu));
6867
6868 destroy_ppc_opcodes(cpu);
6869}
6870
6871static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
6872{
6873 ObjectClass *oc = (ObjectClass *)a;
6874 uint32_t pvr = *(uint32_t *)b;
6875 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
6876
6877
6878 if (unlikely(strcmp(object_class_get_name(oc),
6879 TYPE_HOST_POWERPC_CPU) == 0)) {
6880 return -1;
6881 }
6882
6883 return pcc->pvr == pvr ? 0 : -1;
6884}
6885
6886PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
6887{
6888 GSList *list, *item;
6889 PowerPCCPUClass *pcc = NULL;
6890
6891 list = object_class_get_list(TYPE_POWERPC_CPU, false);
6892 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
6893 if (item != NULL) {
6894 pcc = POWERPC_CPU_CLASS(item->data);
6895 }
6896 g_slist_free(list);
6897
6898 return pcc;
6899}
6900
6901static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
6902{
6903 ObjectClass *oc = (ObjectClass *)a;
6904 uint32_t pvr = *(uint32_t *)b;
6905 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
6906
6907
6908 if (unlikely(strcmp(object_class_get_name(oc),
6909 TYPE_HOST_POWERPC_CPU) == 0)) {
6910 return -1;
6911 }
6912
6913 if (pcc->pvr_match(pcc, pvr)) {
6914 return 0;
6915 }
6916
6917 return -1;
6918}
6919
6920PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
6921{
6922 GSList *list, *item;
6923 PowerPCCPUClass *pcc = NULL;
6924
6925 list = object_class_get_list(TYPE_POWERPC_CPU, true);
6926 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
6927 if (item != NULL) {
6928 pcc = POWERPC_CPU_CLASS(item->data);
6929 }
6930 g_slist_free(list);
6931
6932 return pcc;
6933}
6934
6935static const char *ppc_cpu_lookup_alias(const char *alias)
6936{
6937 int ai;
6938
6939 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
6940 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
6941 return ppc_cpu_aliases[ai].model;
6942 }
6943 }
6944
6945 return NULL;
6946}
6947
6948static ObjectClass *ppc_cpu_class_by_name(const char *name)
6949{
6950 char *cpu_model, *typename;
6951 ObjectClass *oc;
6952 const char *p;
6953 unsigned long pvr;
6954
6955
6956
6957
6958
6959 if (!qemu_strtoul(name, &p, 16, &pvr)) {
6960 int len = p - name;
6961 len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
6962 if ((len == 8) && (*p == '\0')) {
6963 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
6964 }
6965 }
6966
6967
6968
6969
6970
6971
6972
6973#if !defined(CONFIG_USER_ONLY)
6974 if (strcmp(name, "max") == 0) {
6975 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
6976 if (mc) {
6977 return object_class_by_name(mc->default_cpu_type);
6978 }
6979 }
6980#endif
6981
6982 cpu_model = g_ascii_strdown(name, -1);
6983 p = ppc_cpu_lookup_alias(cpu_model);
6984 if (p) {
6985 g_free(cpu_model);
6986 cpu_model = g_strdup(p);
6987 }
6988
6989 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
6990 oc = object_class_by_name(typename);
6991 g_free(typename);
6992 g_free(cpu_model);
6993
6994 return oc;
6995}
6996
6997PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
6998{
6999 ObjectClass *oc = OBJECT_CLASS(pcc);
7000
7001 while (oc && !object_class_is_abstract(oc)) {
7002 oc = object_class_get_parent(oc);
7003 }
7004 assert(oc);
7005
7006 return POWERPC_CPU_CLASS(oc);
7007}
7008
7009
7010static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
7011{
7012 ObjectClass *oc_a = (ObjectClass *)a;
7013 ObjectClass *oc_b = (ObjectClass *)b;
7014 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
7015 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
7016 const char *name_a = object_class_get_name(oc_a);
7017 const char *name_b = object_class_get_name(oc_b);
7018
7019 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
7020 return 1;
7021 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
7022 return -1;
7023 } else {
7024
7025 if (pcc_a->pvr < pcc_b->pvr) {
7026 return -1;
7027 } else if (pcc_a->pvr > pcc_b->pvr) {
7028 return 1;
7029 } else {
7030 return 0;
7031 }
7032 }
7033}
7034
7035static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
7036{
7037 ObjectClass *oc = data;
7038 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7039 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
7040 const char *typename = object_class_get_name(oc);
7041 char *name;
7042 int i;
7043
7044 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
7045 return;
7046 }
7047
7048 name = g_strndup(typename,
7049 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
7050 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr);
7051 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
7052 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
7053 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
7054
7055 if (alias_oc != oc) {
7056 continue;
7057 }
7058
7059
7060
7061
7062 if (strcmp(alias->alias, family->desc) == 0) {
7063 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n",
7064 alias->alias, family->desc);
7065 } else {
7066 qemu_printf("PowerPC %-16s (alias for %s)\n",
7067 alias->alias, name);
7068 }
7069 }
7070 g_free(name);
7071}
7072
7073void ppc_cpu_list(void)
7074{
7075 GSList *list;
7076
7077 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7078 list = g_slist_sort(list, ppc_cpu_list_compare);
7079 g_slist_foreach(list, ppc_cpu_list_entry, NULL);
7080 g_slist_free(list);
7081
7082#ifdef CONFIG_KVM
7083 qemu_printf("\n");
7084 qemu_printf("PowerPC %s\n", "host");
7085#endif
7086}
7087
7088static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
7089{
7090 ObjectClass *oc = data;
7091 CpuDefinitionInfoList **first = user_data;
7092 const char *typename;
7093 CpuDefinitionInfo *info;
7094
7095 typename = object_class_get_name(oc);
7096 info = g_malloc0(sizeof(*info));
7097 info->name = g_strndup(typename,
7098 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
7099
7100 QAPI_LIST_PREPEND(*first, info);
7101}
7102
7103CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
7104{
7105 CpuDefinitionInfoList *cpu_list = NULL;
7106 GSList *list;
7107 int i;
7108
7109 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7110 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
7111 g_slist_free(list);
7112
7113 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
7114 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
7115 ObjectClass *oc;
7116 CpuDefinitionInfo *info;
7117
7118 oc = ppc_cpu_class_by_name(alias->model);
7119 if (oc == NULL) {
7120 continue;
7121 }
7122
7123 info = g_malloc0(sizeof(*info));
7124 info->name = g_strdup(alias->alias);
7125 info->q_typename = g_strdup(object_class_get_name(oc));
7126
7127 QAPI_LIST_PREPEND(cpu_list, info);
7128 }
7129
7130 return cpu_list;
7131}
7132
7133static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
7134{
7135 PowerPCCPU *cpu = POWERPC_CPU(cs);
7136
7137 cpu->env.nip = value;
7138}
7139
7140static bool ppc_cpu_has_work(CPUState *cs)
7141{
7142 PowerPCCPU *cpu = POWERPC_CPU(cs);
7143 CPUPPCState *env = &cpu->env;
7144
7145 return FIELD_EX64(env->msr, MSR, EE) &&
7146 (cs->interrupt_request & CPU_INTERRUPT_HARD);
7147}
7148
7149static void ppc_cpu_reset(DeviceState *dev)
7150{
7151 CPUState *s = CPU(dev);
7152 PowerPCCPU *cpu = POWERPC_CPU(s);
7153 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7154 CPUPPCState *env = &cpu->env;
7155 target_ulong msr;
7156 int i;
7157
7158 pcc->parent_reset(dev);
7159
7160 msr = (target_ulong)0;
7161 msr |= (target_ulong)MSR_HVB;
7162 msr |= (target_ulong)1 << MSR_EP;
7163#if defined(DO_SINGLE_STEP) && 0
7164
7165 msr |= (target_ulong)1 << MSR_SE;
7166 msr |= (target_ulong)1 << MSR_BE;
7167#endif
7168#if defined(CONFIG_USER_ONLY)
7169 msr |= (target_ulong)1 << MSR_FP;
7170 msr |= (target_ulong)1 << MSR_FE0;
7171 msr |= (target_ulong)1 << MSR_FE1;
7172 msr |= (target_ulong)1 << MSR_VR;
7173 msr |= (target_ulong)1 << MSR_VSX;
7174 msr |= (target_ulong)1 << MSR_SPE;
7175 msr |= (target_ulong)1 << MSR_PR;
7176#if defined(TARGET_PPC64)
7177 msr |= (target_ulong)1 << MSR_TM;
7178#endif
7179#if !TARGET_BIG_ENDIAN
7180 msr |= (target_ulong)1 << MSR_LE;
7181 if (!((env->msr_mask >> MSR_LE) & 1)) {
7182 fprintf(stderr, "Selected CPU does not support little-endian.\n");
7183 exit(1);
7184 }
7185#endif
7186#endif
7187
7188#if defined(TARGET_PPC64)
7189 if (mmu_is_64bit(env->mmu_model)) {
7190 msr |= (1ULL << MSR_SF);
7191 }
7192#endif
7193
7194 hreg_store_msr(env, msr, 1);
7195
7196#if !defined(CONFIG_USER_ONLY)
7197 env->nip = env->hreset_vector | env->excp_prefix;
7198
7199 if (tcg_enabled()) {
7200 if (env->mmu_model != POWERPC_MMU_REAL) {
7201 ppc_tlb_invalidate_all(env);
7202 }
7203 pmu_update_summaries(env);
7204 }
7205
7206
7207 env->resume_as_sreset = 0;
7208#endif
7209 hreg_compute_hflags(env);
7210 env->reserve_addr = (target_ulong)-1ULL;
7211
7212 env->pending_interrupts = 0;
7213 s->exception_index = POWERPC_EXCP_NONE;
7214 env->error_code = 0;
7215 ppc_irq_reset(cpu);
7216
7217
7218 set_float_detect_tininess(float_tininess_before_rounding,
7219 &env->fp_status);
7220
7221 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
7222 ppc_spr_t *spr = &env->spr_cb[i];
7223
7224 if (!spr->name) {
7225 continue;
7226 }
7227 env->spr[i] = spr->default_value;
7228 }
7229}
7230
7231#ifndef CONFIG_USER_ONLY
7232
7233static bool ppc_cpu_is_big_endian(CPUState *cs)
7234{
7235 PowerPCCPU *cpu = POWERPC_CPU(cs);
7236 CPUPPCState *env = &cpu->env;
7237
7238 cpu_synchronize_state(cs);
7239
7240 return !FIELD_EX64(env->msr, MSR, LE);
7241}
7242
7243#ifdef CONFIG_TCG
7244static void ppc_cpu_exec_enter(CPUState *cs)
7245{
7246 PowerPCCPU *cpu = POWERPC_CPU(cs);
7247
7248 if (cpu->vhyp) {
7249 PPCVirtualHypervisorClass *vhc =
7250 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
7251 vhc->cpu_exec_enter(cpu->vhyp, cpu);
7252 }
7253}
7254
7255static void ppc_cpu_exec_exit(CPUState *cs)
7256{
7257 PowerPCCPU *cpu = POWERPC_CPU(cs);
7258
7259 if (cpu->vhyp) {
7260 PPCVirtualHypervisorClass *vhc =
7261 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
7262 vhc->cpu_exec_exit(cpu->vhyp, cpu);
7263 }
7264}
7265#endif
7266
7267#endif
7268
7269static void ppc_cpu_instance_init(Object *obj)
7270{
7271 PowerPCCPU *cpu = POWERPC_CPU(obj);
7272 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7273 CPUPPCState *env = &cpu->env;
7274
7275 cpu_set_cpustate_pointers(cpu);
7276 cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
7277
7278 env->msr_mask = pcc->msr_mask;
7279 env->mmu_model = pcc->mmu_model;
7280 env->excp_model = pcc->excp_model;
7281 env->bus_model = pcc->bus_model;
7282 env->insns_flags = pcc->insns_flags;
7283 env->insns_flags2 = pcc->insns_flags2;
7284 env->flags = pcc->flags;
7285 env->bfd_mach = pcc->bfd_mach;
7286 env->check_pow = pcc->check_pow;
7287
7288
7289
7290
7291
7292
7293
7294
7295
7296
7297#if !defined(CONFIG_USER_ONLY)
7298 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
7299#endif
7300
7301 ppc_hash64_init(cpu);
7302}
7303
7304static void ppc_cpu_instance_finalize(Object *obj)
7305{
7306 PowerPCCPU *cpu = POWERPC_CPU(obj);
7307
7308 ppc_hash64_finalize(cpu);
7309}
7310
7311static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
7312{
7313 return pcc->pvr == pvr;
7314}
7315
7316static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
7317{
7318 PowerPCCPU *cpu = POWERPC_CPU(cs);
7319 CPUPPCState *env = &cpu->env;
7320
7321 if ((env->hflags >> MSR_LE) & 1) {
7322 info->endian = BFD_ENDIAN_LITTLE;
7323 }
7324 info->mach = env->bfd_mach;
7325 if (!env->bfd_mach) {
7326#ifdef TARGET_PPC64
7327 info->mach = bfd_mach_ppc64;
7328#else
7329 info->mach = bfd_mach_ppc;
7330#endif
7331 }
7332
7333 info->cap_arch = CS_ARCH_PPC;
7334#ifdef TARGET_PPC64
7335 info->cap_mode = CS_MODE_64;
7336#endif
7337}
7338
7339static Property ppc_cpu_properties[] = {
7340 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
7341 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
7342 false),
7343 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
7344 false),
7345 DEFINE_PROP_END_OF_LIST(),
7346};
7347
7348#ifndef CONFIG_USER_ONLY
7349#include "hw/core/sysemu-cpu-ops.h"
7350
7351static const struct SysemuCPUOps ppc_sysemu_ops = {
7352 .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
7353 .write_elf32_note = ppc32_cpu_write_elf32_note,
7354 .write_elf64_note = ppc64_cpu_write_elf64_note,
7355 .virtio_is_big_endian = ppc_cpu_is_big_endian,
7356 .legacy_vmsd = &vmstate_ppc_cpu,
7357};
7358#endif
7359
7360#ifdef CONFIG_TCG
7361#include "hw/core/tcg-cpu-ops.h"
7362
7363static const struct TCGCPUOps ppc_tcg_ops = {
7364 .initialize = ppc_translate_init,
7365
7366#ifdef CONFIG_USER_ONLY
7367 .record_sigsegv = ppc_cpu_record_sigsegv,
7368#else
7369 .tlb_fill = ppc_cpu_tlb_fill,
7370 .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
7371 .do_interrupt = ppc_cpu_do_interrupt,
7372 .cpu_exec_enter = ppc_cpu_exec_enter,
7373 .cpu_exec_exit = ppc_cpu_exec_exit,
7374 .do_unaligned_access = ppc_cpu_do_unaligned_access,
7375#endif
7376};
7377#endif
7378
7379static void ppc_cpu_class_init(ObjectClass *oc, void *data)
7380{
7381 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7382 CPUClass *cc = CPU_CLASS(oc);
7383 DeviceClass *dc = DEVICE_CLASS(oc);
7384
7385 device_class_set_parent_realize(dc, ppc_cpu_realize,
7386 &pcc->parent_realize);
7387 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
7388 &pcc->parent_unrealize);
7389 pcc->pvr_match = ppc_pvr_match_default;
7390 device_class_set_props(dc, ppc_cpu_properties);
7391
7392 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
7393
7394 cc->class_by_name = ppc_cpu_class_by_name;
7395 cc->has_work = ppc_cpu_has_work;
7396 cc->dump_state = ppc_cpu_dump_state;
7397 cc->set_pc = ppc_cpu_set_pc;
7398 cc->gdb_read_register = ppc_cpu_gdb_read_register;
7399 cc->gdb_write_register = ppc_cpu_gdb_write_register;
7400#ifndef CONFIG_USER_ONLY
7401 cc->sysemu_ops = &ppc_sysemu_ops;
7402#endif
7403
7404 cc->gdb_num_core_regs = 71;
7405#ifndef CONFIG_USER_ONLY
7406 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml;
7407#endif
7408#ifdef USE_APPLE_GDB
7409 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
7410 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
7411 cc->gdb_num_core_regs = 71 + 32;
7412#endif
7413
7414 cc->gdb_arch_name = ppc_gdb_arch_name;
7415#if defined(TARGET_PPC64)
7416 cc->gdb_core_xml_file = "power64-core.xml";
7417#else
7418 cc->gdb_core_xml_file = "power-core.xml";
7419#endif
7420 cc->disas_set_info = ppc_disas_set_info;
7421
7422 dc->fw_name = "PowerPC,UNKNOWN";
7423
7424#ifdef CONFIG_TCG
7425 cc->tcg_ops = &ppc_tcg_ops;
7426#endif
7427}
7428
7429static const TypeInfo ppc_cpu_type_info = {
7430 .name = TYPE_POWERPC_CPU,
7431 .parent = TYPE_CPU,
7432 .instance_size = sizeof(PowerPCCPU),
7433 .instance_align = __alignof__(PowerPCCPU),
7434 .instance_init = ppc_cpu_instance_init,
7435 .instance_finalize = ppc_cpu_instance_finalize,
7436 .abstract = true,
7437 .class_size = sizeof(PowerPCCPUClass),
7438 .class_init = ppc_cpu_class_init,
7439};
7440
7441#ifndef CONFIG_USER_ONLY
7442static const TypeInfo ppc_vhyp_type_info = {
7443 .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
7444 .parent = TYPE_INTERFACE,
7445 .class_size = sizeof(PPCVirtualHypervisorClass),
7446};
7447#endif
7448
7449static void ppc_cpu_register_types(void)
7450{
7451 type_register_static(&ppc_cpu_type_info);
7452#ifndef CONFIG_USER_ONLY
7453 type_register_static(&ppc_vhyp_type_info);
7454#endif
7455}
7456
7457void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
7458{
7459#define RGPL 4
7460#define RFPL 4
7461
7462 PowerPCCPU *cpu = POWERPC_CPU(cs);
7463 CPUPPCState *env = &cpu->env;
7464 int i;
7465
7466 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
7467 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
7468 env->nip, env->lr, env->ctr, cpu_read_xer(env),
7469 cs->cpu_index);
7470 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
7471 "%08x iidx %d didx %d\n",
7472 env->msr, env->spr[SPR_HID0], env->hflags,
7473 cpu_mmu_index(env, true), cpu_mmu_index(env, false));
7474#if !defined(CONFIG_USER_ONLY)
7475 if (env->tb_env) {
7476 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7477 " DECR " TARGET_FMT_lu "\n", cpu_ppc_load_tbu(env),
7478 cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env));
7479 }
7480#else
7481 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 "\n", cpu_ppc_load_tbu(env),
7482 cpu_ppc_load_tbl(env));
7483#endif
7484 for (i = 0; i < 32; i++) {
7485 if ((i & (RGPL - 1)) == 0) {
7486 qemu_fprintf(f, "GPR%02d", i);
7487 }
7488 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7489 if ((i & (RGPL - 1)) == (RGPL - 1)) {
7490 qemu_fprintf(f, "\n");
7491 }
7492 }
7493 qemu_fprintf(f, "CR ");
7494 for (i = 0; i < 8; i++)
7495 qemu_fprintf(f, "%01x", env->crf[i]);
7496 qemu_fprintf(f, " [");
7497 for (i = 0; i < 8; i++) {
7498 char a = '-';
7499 if (env->crf[i] & 0x08) {
7500 a = 'L';
7501 } else if (env->crf[i] & 0x04) {
7502 a = 'G';
7503 } else if (env->crf[i] & 0x02) {
7504 a = 'E';
7505 }
7506 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7507 }
7508 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
7509 env->reserve_addr);
7510
7511 if (flags & CPU_DUMP_FPU) {
7512 for (i = 0; i < 32; i++) {
7513 if ((i & (RFPL - 1)) == 0) {
7514 qemu_fprintf(f, "FPR%02d", i);
7515 }
7516 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
7517 if ((i & (RFPL - 1)) == (RFPL - 1)) {
7518 qemu_fprintf(f, "\n");
7519 }
7520 }
7521 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
7522 }
7523
7524#if !defined(CONFIG_USER_ONLY)
7525 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
7526 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
7527 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
7528 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
7529
7530 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
7531 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
7532 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
7533 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
7534
7535 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
7536 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
7537 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
7538 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
7539
7540 switch (env->excp_model) {
7541#if defined(TARGET_PPC64)
7542 case POWERPC_EXCP_POWER7:
7543 case POWERPC_EXCP_POWER8:
7544 case POWERPC_EXCP_POWER9:
7545 case POWERPC_EXCP_POWER10:
7546 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
7547 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
7548 break;
7549#endif
7550 case POWERPC_EXCP_BOOKE:
7551 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
7552 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
7553 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
7554 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
7555
7556 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7557 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7558 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
7559 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
7560
7561 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
7562 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
7563 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
7564 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
7565
7566 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
7567 " EPR " TARGET_FMT_lx "\n",
7568 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
7569 env->spr[SPR_BOOKE_EPR]);
7570
7571
7572 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
7573 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
7574 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
7575 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
7576
7577
7578
7579
7580
7581 break;
7582 case POWERPC_EXCP_40x:
7583 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7584 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7585 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
7586 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]);
7587
7588 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx
7589 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7590 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2],
7591 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]);
7592 break;
7593 default:
7594 break;
7595 }
7596
7597#if defined(TARGET_PPC64)
7598 if (env->flags & POWERPC_FLAG_CFAR) {
7599 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
7600 }
7601#endif
7602
7603 if (env->spr_cb[SPR_LPCR].name) {
7604 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
7605 }
7606
7607 switch (env->mmu_model) {
7608 case POWERPC_MMU_32B:
7609 case POWERPC_MMU_SOFT_6xx:
7610#if defined(TARGET_PPC64)
7611 case POWERPC_MMU_64B:
7612 case POWERPC_MMU_2_03:
7613 case POWERPC_MMU_2_06:
7614 case POWERPC_MMU_2_07:
7615 case POWERPC_MMU_3_00:
7616#endif
7617 if (env->spr_cb[SPR_SDR1].name) {
7618 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
7619 }
7620 if (env->spr_cb[SPR_PTCR].name) {
7621 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
7622 }
7623 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
7624 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
7625 break;
7626 case POWERPC_MMU_BOOKE206:
7627 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
7628 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
7629 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
7630 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
7631
7632 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
7633 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7634 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
7635 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
7636
7637 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
7638 " TLB1CFG " TARGET_FMT_lx "\n",
7639 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
7640 env->spr[SPR_BOOKE_TLB1CFG]);
7641 break;
7642 default:
7643 break;
7644 }
7645#endif
7646
7647#undef RGPL
7648#undef RFPL
7649}
7650type_init(ppc_cpu_register_types)
7651
