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20#include "qemu/osdep.h"
21#include "qemu/log.h"
22#include "cpu.h"
23#include "exec/exec-all.h"
24#include "exec/helper-proto.h"
25#include "qemu/error-report.h"
26#include "qemu/main-loop.h"
27#include "mmu-book3s-v3.h"
28
29#include "helper_regs.h"
30
31
32
33void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn)
34{
35 qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn,
36 env->spr[sprn]);
37}
38
39void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
40{
41 qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
42 env->spr[sprn]);
43}
44
45#ifdef TARGET_PPC64
46static void raise_hv_fu_exception(CPUPPCState *env, uint32_t bit,
47 const char *caller, uint32_t cause,
48 uintptr_t raddr)
49{
50 qemu_log_mask(CPU_LOG_INT, "HV Facility %d is unavailable (%s)\n",
51 bit, caller);
52
53 env->spr[SPR_HFSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS);
54
55 raise_exception_err_ra(env, POWERPC_EXCP_HV_FU, cause, raddr);
56}
57
58static void raise_fu_exception(CPUPPCState *env, uint32_t bit,
59 uint32_t sprn, uint32_t cause,
60 uintptr_t raddr)
61{
62 qemu_log("Facility SPR %d is unavailable (SPR FSCR:%d)\n", sprn, bit);
63
64 env->spr[SPR_FSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS);
65 cause &= FSCR_IC_MASK;
66 env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS;
67
68 raise_exception_err_ra(env, POWERPC_EXCP_FU, 0, raddr);
69}
70#endif
71
72void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
73 const char *caller, uint32_t cause)
74{
75#ifdef TARGET_PPC64
76 if ((env->msr_mask & MSR_HVB) && !FIELD_EX64(env->msr, MSR, HV) &&
77 !(env->spr[SPR_HFSCR] & (1UL << bit))) {
78 raise_hv_fu_exception(env, bit, caller, cause, GETPC());
79 }
80#endif
81}
82
83void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit,
84 uint32_t sprn, uint32_t cause)
85{
86#ifdef TARGET_PPC64
87 if (env->spr[SPR_FSCR] & (1ULL << bit)) {
88
89 return;
90 }
91 raise_fu_exception(env, bit, sprn, cause, GETPC());
92#endif
93}
94
95void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,
96 uint32_t sprn, uint32_t cause)
97{
98#ifdef TARGET_PPC64
99 if (env->msr & (1ULL << bit)) {
100
101 return;
102 }
103 raise_fu_exception(env, bit, sprn, cause, GETPC());
104#endif
105}
106
107#if !defined(CONFIG_USER_ONLY)
108
109void helper_store_sdr1(CPUPPCState *env, target_ulong val)
110{
111 if (env->spr[SPR_SDR1] != val) {
112 ppc_store_sdr1(env, val);
113 tlb_flush(env_cpu(env));
114 }
115}
116
117#if defined(TARGET_PPC64)
118void helper_store_ptcr(CPUPPCState *env, target_ulong val)
119{
120 if (env->spr[SPR_PTCR] != val) {
121 PowerPCCPU *cpu = env_archcpu(env);
122 target_ulong ptcr_mask = PTCR_PATB | PTCR_PATS;
123 target_ulong patbsize = val & PTCR_PATS;
124
125 qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, val);
126
127 assert(!cpu->vhyp);
128 assert(env->mmu_model & POWERPC_MMU_3_00);
129
130 if (val & ~ptcr_mask) {
131 error_report("Invalid bits 0x"TARGET_FMT_lx" set in PTCR",
132 val & ~ptcr_mask);
133 val &= ptcr_mask;
134 }
135
136 if (patbsize > 24) {
137 error_report("Invalid Partition Table size 0x" TARGET_FMT_lx
138 " stored in PTCR", patbsize);
139 return;
140 }
141
142 env->spr[SPR_PTCR] = val;
143 tlb_flush(env_cpu(env));
144 }
145}
146
147void helper_store_pcr(CPUPPCState *env, target_ulong value)
148{
149 PowerPCCPU *cpu = env_archcpu(env);
150 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
151
152 env->spr[SPR_PCR] = value & pcc->pcr_mask;
153}
154
155
156
157
158
159target_ulong helper_load_dpdes(CPUPPCState *env)
160{
161 target_ulong dpdes = 0;
162
163 helper_hfscr_facility_check(env, HFSCR_MSGP, "load DPDES", HFSCR_IC_MSGP);
164
165
166 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
167 dpdes = 1;
168 }
169
170 return dpdes;
171}
172
173void helper_store_dpdes(CPUPPCState *env, target_ulong val)
174{
175 PowerPCCPU *cpu = env_archcpu(env);
176 CPUState *cs = CPU(cpu);
177
178 helper_hfscr_facility_check(env, HFSCR_MSGP, "store DPDES", HFSCR_IC_MSGP);
179
180
181 if (val & ~0x1) {
182 qemu_log_mask(LOG_GUEST_ERROR, "Invalid DPDES register value "
183 TARGET_FMT_lx"\n", val);
184 return;
185 }
186
187 if (val & 0x1) {
188 env->pending_interrupts |= 1 << PPC_INTERRUPT_DOORBELL;
189 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
190 } else {
191 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
192 }
193}
194#endif
195
196void helper_store_pidr(CPUPPCState *env, target_ulong val)
197{
198 env->spr[SPR_BOOKS_PID] = val;
199 tlb_flush(env_cpu(env));
200}
201
202void helper_store_lpidr(CPUPPCState *env, target_ulong val)
203{
204 env->spr[SPR_LPIDR] = val;
205
206
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209
210
211
212 tlb_flush(env_cpu(env));
213}
214
215void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
216{
217
218 hreg_compute_hflags(env);
219
220 store_40x_dbcr0(env, val);
221}
222
223void helper_store_40x_sler(CPUPPCState *env, target_ulong val)
224{
225 store_40x_sler(env, val);
226}
227#endif
228
229
230
231
232
233
234
235
236
237
238void helper_fixup_thrm(CPUPPCState *env)
239{
240 target_ulong v, t;
241 int i;
242
243#define THRM1_TIN (1 << 31)
244#define THRM1_TIV (1 << 30)
245#define THRM1_THRES(x) (((x) & 0x7f) << 23)
246#define THRM1_TID (1 << 2)
247#define THRM1_TIE (1 << 1)
248#define THRM1_V (1 << 0)
249#define THRM3_E (1 << 0)
250
251 if (!(env->spr[SPR_THRM3] & THRM3_E)) {
252 return;
253 }
254
255
256 for (i = SPR_THRM1; i <= SPR_THRM2; i++) {
257 v = env->spr[i];
258 if (!(v & THRM1_V)) {
259 continue;
260 }
261 v |= THRM1_TIV;
262 v &= ~THRM1_TIN;
263 t = v & THRM1_THRES(127);
264 if ((v & THRM1_TID) && t < THRM1_THRES(24)) {
265 v |= THRM1_TIN;
266 }
267 if (!(v & THRM1_TID) && t > THRM1_THRES(24)) {
268 v |= THRM1_TIN;
269 }
270 env->spr[i] = v;
271 }
272}
273