LXR qemu/target/ppc/mmu-hash32.h

   1#ifndef MMU_HASH32_H
   2#define MMU_HASH32_H
   3
   4#ifndef CONFIG_USER_ONLY
   5
   6hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash);
   7bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
   8                      hwaddr *raddrp, int *psizep, int *protp, int mmu_idx,
   9                      bool guest_visible);
  10
  11/*
  12 * Segment register definitions
  13 */
  14
  15#define SR32_T                  0x80000000
  16#define SR32_KS                 0x40000000
  17#define SR32_KP                 0x20000000
  18#define SR32_NX                 0x10000000
  19#define SR32_VSID               0x00ffffff
  20
  21/*
  22 * Block Address Translation (BAT) definitions
  23 */
  24
  25#define BATU32_BEPIU            0xf0000000
  26#define BATU32_BEPIL            0x0ffe0000
  27#define BATU32_BEPI             0xfffe0000
  28#define BATU32_BL               0x00001ffc
  29#define BATU32_VS               0x00000002
  30#define BATU32_VP               0x00000001
  31
  32
  33#define BATL32_BRPN             0xfffe0000
  34#define BATL32_WIMG             0x00000078
  35#define BATL32_PP               0x00000003
  36
  37/*
  38 * Hash page table definitions
  39 */
  40#define SDR_32_HTABORG         0xFFFF0000UL
  41#define SDR_32_HTABMASK        0x000001FFUL
  42
  43#define HPTES_PER_GROUP         8
  44#define HASH_PTE_SIZE_32        8
  45#define HASH_PTEG_SIZE_32       (HASH_PTE_SIZE_32 * HPTES_PER_GROUP)
  46
  47#define HPTE32_V_VALID          0x80000000
  48#define HPTE32_V_VSID           0x7fffff80
  49#define HPTE32_V_SECONDARY      0x00000040
  50#define HPTE32_V_API            0x0000003f
  51#define HPTE32_V_COMPARE(x, y)  (!(((x) ^ (y)) & 0x7fffffbf))
  52
  53#define HPTE32_R_RPN            0xfffff000
  54#define HPTE32_R_R              0x00000100
  55#define HPTE32_R_C              0x00000080
  56#define HPTE32_R_W              0x00000040
  57#define HPTE32_R_I              0x00000020
  58#define HPTE32_R_M              0x00000010
  59#define HPTE32_R_G              0x00000008
  60#define HPTE32_R_WIMG           0x00000078
  61#define HPTE32_R_PP             0x00000003
  62
  63static inline hwaddr ppc_hash32_hpt_base(PowerPCCPU *cpu)
  64{
  65    return cpu->env.spr[SPR_SDR1] & SDR_32_HTABORG;
  66}
  67
  68static inline hwaddr ppc_hash32_hpt_mask(PowerPCCPU *cpu)
  69{
  70    return ((cpu->env.spr[SPR_SDR1] & SDR_32_HTABMASK) << 16) | 0xFFFF;
  71}
  72
  73static inline target_ulong ppc_hash32_load_hpte0(PowerPCCPU *cpu,
  74                                                 hwaddr pte_offset)
  75{
  76    target_ulong base = ppc_hash32_hpt_base(cpu);
  77
  78    return ldl_phys(CPU(cpu)->as, base + pte_offset);
  79}
  80
  81static inline target_ulong ppc_hash32_load_hpte1(PowerPCCPU *cpu,
  82                                                 hwaddr pte_offset)
  83{
  84    target_ulong base = ppc_hash32_hpt_base(cpu);
  85
  86    return ldl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2);
  87}
  88
  89static inline void ppc_hash32_store_hpte0(PowerPCCPU *cpu,
  90                                          hwaddr pte_offset, target_ulong pte0)
  91{
  92    target_ulong base = ppc_hash32_hpt_base(cpu);
  93
  94    stl_phys(CPU(cpu)->as, base + pte_offset, pte0);
  95}
  96
  97static inline void ppc_hash32_store_hpte1(PowerPCCPU *cpu,
  98                                          hwaddr pte_offset, target_ulong pte1)
  99{
 100    target_ulong base = ppc_hash32_hpt_base(cpu);
 101
 102    stl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2, pte1);
 103}
 104
 105typedef struct {
 106    uint32_t pte0, pte1;
 107} ppc_hash_pte32_t;
 108
 109#endif /* CONFIG_USER_ONLY */
 110
 111#endif /* MMU_HASH32_H */
 112