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19#ifndef RISCV_CPU_INTERNALS_H
20#define RISCV_CPU_INTERNALS_H
21
22#include "hw/registerfields.h"
23
24
25FIELD(VDATA, VM, 0, 1)
26FIELD(VDATA, LMUL, 1, 3)
27FIELD(VDATA, VTA, 4, 1)
28FIELD(VDATA, VTA_ALL_1S, 5, 1)
29FIELD(VDATA, NF, 6, 4)
30FIELD(VDATA, WD, 6, 1)
31
32
33target_ulong fclass_h(uint64_t frs1);
34target_ulong fclass_s(uint64_t frs1);
35target_ulong fclass_d(uint64_t frs1);
36
37#ifndef CONFIG_USER_ONLY
38extern const VMStateDescription vmstate_riscv_cpu;
39#endif
40
41enum {
42 RISCV_FRM_RNE = 0,
43 RISCV_FRM_RTZ = 1,
44 RISCV_FRM_RDN = 2,
45 RISCV_FRM_RUP = 3,
46 RISCV_FRM_RMM = 4,
47 RISCV_FRM_DYN = 7,
48 RISCV_FRM_ROD = 8,
49};
50
51static inline uint64_t nanbox_s(CPURISCVState *env, float32 f)
52{
53
54 if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
55 return (int32_t)f;
56 } else {
57 return f | MAKE_64BIT_MASK(32, 32);
58 }
59}
60
61static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f)
62{
63
64 if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
65 return (uint32_t)f;
66 }
67
68 uint64_t mask = MAKE_64BIT_MASK(32, 32);
69
70 if (likely((f & mask) == mask)) {
71 return (uint32_t)f;
72 } else {
73 return 0x7fc00000u;
74 }
75}
76
77static inline uint64_t nanbox_h(CPURISCVState *env, float16 f)
78{
79
80 if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
81 return (int16_t)f;
82 } else {
83 return f | MAKE_64BIT_MASK(16, 48);
84 }
85}
86
87static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f)
88{
89
90 if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
91 return (uint16_t)f;
92 }
93
94 uint64_t mask = MAKE_64BIT_MASK(16, 48);
95
96 if (likely((f & mask) == mask)) {
97 return (uint16_t)f;
98 } else {
99 return 0x7E00u;
100 }
101}
102
103#endif
104